agp_intel.c revision 1.13
1 /* $NetBSD: agp_intel.c,v 1.13 2003/08/26 17:28:13 tron Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/pci/agp_intel.c,v 1.4 2001/07/05 21:28:47 jhb Exp $ 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: agp_intel.c,v 1.13 2003/08/26 17:28:13 tron Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/proc.h> 40 #include <sys/agpio.h> 41 #include <sys/device.h> 42 #include <sys/agpio.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcidevs.h> 49 #include <dev/pci/agpvar.h> 50 #include <dev/pci/agpreg.h> 51 52 #include <machine/bus.h> 53 54 struct agp_intel_softc { 55 u_int32_t initial_aperture; 56 /* aperture size at startup */ 57 struct agp_gatt *gatt; 58 struct pci_attach_args vga_pa; 59 u_int aperture_mask; 60 int chiptype; /* Chip type */ 61 #define CHIP_INTEL 0x0 62 #define CHIP_I443 0x1 63 #define CHIP_I840 0x2 64 #define CHIP_I845 0x3 65 #define CHIP_I850 0x4 66 }; 67 68 static u_int32_t agp_intel_get_aperture(struct agp_softc *); 69 static int agp_intel_set_aperture(struct agp_softc *, u_int32_t); 70 static int agp_intel_bind_page(struct agp_softc *, off_t, bus_addr_t); 71 static int agp_intel_unbind_page(struct agp_softc *, off_t); 72 static void agp_intel_flush_tlb(struct agp_softc *); 73 74 struct agp_methods agp_intel_methods = { 75 agp_intel_get_aperture, 76 agp_intel_set_aperture, 77 agp_intel_bind_page, 78 agp_intel_unbind_page, 79 agp_intel_flush_tlb, 80 agp_generic_enable, 81 agp_generic_alloc_memory, 82 agp_generic_free_memory, 83 agp_generic_bind_memory, 84 agp_generic_unbind_memory, 85 }; 86 87 static int 88 agp_intel_vgamatch(struct pci_attach_args *pa) 89 { 90 switch (PCI_PRODUCT(pa->pa_id)) { 91 case PCI_PRODUCT_INTEL_82855PM_AGP: 92 case PCI_PRODUCT_INTEL_82443LX_AGP: 93 case PCI_PRODUCT_INTEL_82443BX_AGP: 94 case PCI_PRODUCT_INTEL_82443GX_AGP: 95 case PCI_PRODUCT_INTEL_82850_AGP: /* i850/i860 */ 96 case PCI_PRODUCT_INTEL_82845_AGP: 97 case PCI_PRODUCT_INTEL_82840_AGP: 98 case PCI_PRODUCT_INTEL_82865_AGP: 99 case PCI_PRODUCT_INTEL_82875P_AGP: 100 return (1); 101 } 102 103 return (0); 104 } 105 106 int 107 agp_intel_attach(struct device *parent, struct device *self, void *aux) 108 { 109 struct agp_softc *sc = (struct agp_softc *)self; 110 struct pci_attach_args *pa= aux; 111 struct agp_intel_softc *isc; 112 struct agp_gatt *gatt; 113 pcireg_t reg; 114 u_int32_t value; 115 116 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 117 if (isc == NULL) { 118 aprint_error(": can't allocate chipset-specific softc\n"); 119 return ENOMEM; 120 } 121 122 sc->as_methods = &agp_intel_methods; 123 sc->as_chipc = isc; 124 125 if (pci_find_device(&isc->vga_pa, agp_intel_vgamatch) == 0) { 126 aprint_normal(": using generic initialization for Intel AGP\n"); 127 aprint_normal("%s", sc->as_dev.dv_xname); 128 isc->chiptype = CHIP_INTEL; 129 } 130 131 pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, &sc->as_capoff, 132 NULL); 133 134 if (agp_map_aperture(pa, sc) != 0) { 135 aprint_error(": can't map aperture\n"); 136 free(isc, M_AGP); 137 sc->as_chipc = NULL; 138 return ENXIO; 139 } 140 141 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 142 case PCI_PRODUCT_INTEL_82855PM_AGP: 143 case PCI_PRODUCT_INTEL_82845_AGP: 144 case PCI_PRODUCT_INTEL_82865_AGP: 145 case PCI_PRODUCT_INTEL_82875P_AGP: 146 isc->chiptype = CHIP_I845; 147 break; 148 case PCI_PRODUCT_INTEL_82840_AGP: 149 isc->chiptype = CHIP_I840; 150 break; 151 case PCI_PRODUCT_INTEL_82850_AGP: 152 isc->chiptype = CHIP_I850; 153 break; 154 case PCI_PRODUCT_INTEL_82443LX_AGP: 155 case PCI_PRODUCT_INTEL_82443BX_AGP: 156 case PCI_PRODUCT_INTEL_82443GX_AGP: 157 isc->chiptype = CHIP_I443; 158 break; 159 } 160 161 /* Determine maximum supported aperture size. */ 162 value = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE); 163 pci_conf_write(sc->as_pc, sc->as_tag, 164 AGP_INTEL_APSIZE, APSIZE_MASK); 165 isc->aperture_mask = pci_conf_read(sc->as_pc, sc->as_tag, 166 AGP_INTEL_APSIZE) & APSIZE_MASK; 167 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE, value); 168 isc->initial_aperture = AGP_GET_APERTURE(sc); 169 170 for (;;) { 171 gatt = agp_alloc_gatt(sc); 172 if (gatt) 173 break; 174 175 /* 176 * Probably contigmalloc failure. Try reducing the 177 * aperture so that the gatt size reduces. 178 */ 179 if (AGP_SET_APERTURE(sc, AGP_GET_APERTURE(sc) / 2)) { 180 agp_generic_detach(sc); 181 aprint_error(": failed to set aperture\n"); 182 return ENOMEM; 183 } 184 } 185 isc->gatt = gatt; 186 187 /* Install the gatt. */ 188 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 189 gatt->ag_physical); 190 191 /* Enable the GLTB and setup the control register. */ 192 switch (isc->chiptype) { 193 case CHIP_I443: 194 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 195 AGPCTRL_AGPRSE | AGPCTRL_GTLB); 196 197 default: 198 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 199 pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL) 200 | AGPCTRL_GTLB); 201 } 202 203 /* Enable things, clear errors etc. */ 204 switch (isc->chiptype) { 205 case CHIP_I845: 206 { 207 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD, 208 AGPCMD_SBA | AGPCMD_AGPEN | AGPCMD_RATE_4X); 209 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I845_AGPMISC, AGPMISC_AAGN); 210 break; 211 } 212 case CHIP_I840: 213 case CHIP_I850: 214 { 215 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD); 216 reg |= AGPCMD_AGPEN; 217 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD, 218 reg); 219 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG); 220 reg |= MCHCFG_AAGN; 221 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG, 222 reg); 223 break; 224 } 225 default: 226 { 227 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 228 reg &= ~NBXCFG_APAE; 229 reg |= NBXCFG_AAGN; 230 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 231 } 232 } 233 234 /* Clear Error status */ 235 switch (isc->chiptype) { 236 case CHIP_I840: 237 pci_conf_write(sc->as_pc, sc->as_tag, 238 AGP_INTEL_I8XX_ERRSTS, 0xc000); 239 break; 240 241 case CHIP_I850: 242 case CHIP_I845: 243 pci_conf_write(sc->as_pc, sc->as_tag, 244 AGP_INTEL_I8XX_ERRSTS, 0x00ff); 245 break; 246 247 default: 248 pci_conf_write(sc->as_pc, sc->as_tag, 249 AGP_INTEL_ERRSTS, 0x70); 250 } 251 252 return (0); 253 } 254 255 #if 0 256 static int 257 agp_intel_detach(struct agp_softc *sc) 258 { 259 int error; 260 pcireg_t reg; 261 struct agp_intel_softc *isc = sc->as_chipc; 262 263 error = agp_generic_detach(sc); 264 if (error) 265 return error; 266 267 /* XXX i845/i855PM/i840/i850E */ 268 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 269 reg &= ~(1 << 9); 270 printf("%s: set NBXCFG to %x\n", __FUNCTION__, reg); 271 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 272 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 0); 273 AGP_SET_APERTURE(sc, isc->initial_aperture); 274 agp_free_gatt(sc, isc->gatt); 275 276 return 0; 277 } 278 #endif 279 280 static u_int32_t 281 agp_intel_get_aperture(struct agp_softc *sc) 282 { 283 struct agp_intel_softc *isc = sc->as_chipc; 284 u_int32_t apsize; 285 286 apsize = pci_conf_read(sc->as_pc, sc->as_tag, 287 AGP_INTEL_APSIZE) & isc->aperture_mask; 288 289 /* 290 * The size is determined by the number of low bits of 291 * register APBASE which are forced to zero. The low 22 bits 292 * are always forced to zero and each zero bit in the apsize 293 * field just read forces the corresponding bit in the 27:22 294 * to be zero. We calculate the aperture size accordingly. 295 */ 296 return (((apsize ^ isc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1; 297 } 298 299 static int 300 agp_intel_set_aperture(struct agp_softc *sc, u_int32_t aperture) 301 { 302 struct agp_intel_softc *isc = sc->as_chipc; 303 u_int32_t apsize; 304 305 /* 306 * Reverse the magic from get_aperture. 307 */ 308 apsize = ((aperture - 1) >> 22) ^ isc->aperture_mask; 309 310 /* 311 * Double check for sanity. 312 */ 313 if ((((apsize ^ isc->aperture_mask) << 22) | 314 ((1 << 22) - 1)) + 1 != aperture) 315 return EINVAL; 316 317 pci_conf_write(sc->as_pc, sc->as_tag, 318 AGP_INTEL_APSIZE, apsize); 319 320 return 0; 321 } 322 323 static int 324 agp_intel_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 325 { 326 struct agp_intel_softc *isc = sc->as_chipc; 327 328 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 329 return EINVAL; 330 331 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 332 return 0; 333 } 334 335 static int 336 agp_intel_unbind_page(struct agp_softc *sc, off_t offset) 337 { 338 struct agp_intel_softc *isc = sc->as_chipc; 339 340 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 341 return EINVAL; 342 343 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 344 return 0; 345 } 346 347 static void 348 agp_intel_flush_tlb(struct agp_softc *sc) 349 { 350 struct agp_intel_softc *isc = sc->as_chipc; 351 pcireg_t reg; 352 353 switch (isc->chiptype) { 354 case CHIP_I850: 355 case CHIP_I845: 356 case CHIP_I840: 357 case CHIP_I443: 358 { 359 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL); 360 reg &= ~AGPCTRL_GTLB; 361 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 362 reg); 363 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 364 reg | AGPCTRL_GTLB); 365 break; 366 } 367 default: /* XXX */ 368 { 369 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 370 0x2200); 371 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 372 0x2280); 373 } 374 } 375 } 376
Indexes created Sun Sep 21 20:09:37 GMT 2025