agp_intel.c revision 1.15.2.4
1 /* $NetBSD: agp_intel.c,v 1.15.2.4 2007/10/27 11:32:31 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/pci/agp_intel.c,v 1.4 2001/07/05 21:28:47 jhb Exp $ 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: agp_intel.c,v 1.15.2.4 2007/10/27 11:32:31 yamt Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/proc.h> 40 #include <sys/agpio.h> 41 #include <sys/device.h> 42 43 #include <uvm/uvm_extern.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/agpvar.h> 49 #include <dev/pci/agpreg.h> 50 51 #include <sys/bus.h> 52 53 struct agp_intel_softc { 54 u_int32_t initial_aperture; 55 /* aperture size at startup */ 56 struct agp_gatt *gatt; 57 struct pci_attach_args vga_pa; 58 u_int aperture_mask; 59 int chiptype; /* Chip type */ 60 #define CHIP_INTEL 0x0 61 #define CHIP_I443 0x1 62 #define CHIP_I840 0x2 63 #define CHIP_I845 0x3 64 #define CHIP_I850 0x4 65 #define CHIP_I865 0x5 66 67 void *sc_powerhook; 68 struct pci_conf_state sc_pciconf; 69 }; 70 71 static u_int32_t agp_intel_get_aperture(struct agp_softc *); 72 static int agp_intel_set_aperture(struct agp_softc *, u_int32_t); 73 static int agp_intel_bind_page(struct agp_softc *, off_t, bus_addr_t); 74 static int agp_intel_unbind_page(struct agp_softc *, off_t); 75 static void agp_intel_flush_tlb(struct agp_softc *); 76 static void agp_intel_powerhook(int, void *); 77 78 static struct agp_methods agp_intel_methods = { 79 agp_intel_get_aperture, 80 agp_intel_set_aperture, 81 agp_intel_bind_page, 82 agp_intel_unbind_page, 83 agp_intel_flush_tlb, 84 agp_generic_enable, 85 agp_generic_alloc_memory, 86 agp_generic_free_memory, 87 agp_generic_bind_memory, 88 agp_generic_unbind_memory, 89 }; 90 91 static int 92 agp_intel_vgamatch(struct pci_attach_args *pa) 93 { 94 switch (PCI_PRODUCT(pa->pa_id)) { 95 case PCI_PRODUCT_INTEL_82855PM_AGP: 96 case PCI_PRODUCT_INTEL_82443LX_AGP: 97 case PCI_PRODUCT_INTEL_82443BX_AGP: 98 case PCI_PRODUCT_INTEL_82443GX_AGP: 99 case PCI_PRODUCT_INTEL_82850_AGP: /* i850/i860 */ 100 case PCI_PRODUCT_INTEL_82845_AGP: 101 case PCI_PRODUCT_INTEL_82840_AGP: 102 case PCI_PRODUCT_INTEL_82865_AGP: 103 case PCI_PRODUCT_INTEL_82875P_AGP: 104 return (1); 105 } 106 107 return (0); 108 } 109 110 int 111 agp_intel_attach(struct device *parent, struct device *self, void *aux) 112 { 113 struct agp_softc *sc = (struct agp_softc *)self; 114 struct pci_attach_args *pa= aux; 115 struct agp_intel_softc *isc; 116 struct agp_gatt *gatt; 117 pcireg_t reg; 118 u_int32_t value; 119 120 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 121 if (isc == NULL) { 122 aprint_error(": can't allocate chipset-specific softc\n"); 123 return ENOMEM; 124 } 125 126 sc->as_methods = &agp_intel_methods; 127 sc->as_chipc = isc; 128 129 if (pci_find_device(&isc->vga_pa, agp_intel_vgamatch) == 0) { 130 aprint_normal(": using generic initialization for Intel AGP\n"); 131 aprint_normal("%s", sc->as_dev.dv_xname); 132 isc->chiptype = CHIP_INTEL; 133 } 134 135 pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, &sc->as_capoff, 136 NULL); 137 138 if (agp_map_aperture(pa, sc, AGP_APBASE) != 0) { 139 aprint_error(": can't map aperture\n"); 140 free(isc, M_AGP); 141 sc->as_chipc = NULL; 142 return ENXIO; 143 } 144 145 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 146 case PCI_PRODUCT_INTEL_82443LX_AGP: 147 case PCI_PRODUCT_INTEL_82443BX_AGP: 148 case PCI_PRODUCT_INTEL_82443GX_AGP: 149 isc->chiptype = CHIP_I443; 150 break; 151 case PCI_PRODUCT_INTEL_82840_AGP: 152 isc->chiptype = CHIP_I840; 153 break; 154 case PCI_PRODUCT_INTEL_82855PM_AGP: 155 case PCI_PRODUCT_INTEL_82845_AGP: 156 isc->chiptype = CHIP_I845; 157 break; 158 case PCI_PRODUCT_INTEL_82850_AGP: 159 isc->chiptype = CHIP_I850; 160 break; 161 case PCI_PRODUCT_INTEL_82865_AGP: 162 case PCI_PRODUCT_INTEL_82875P_AGP: 163 isc->chiptype = CHIP_I865; 164 break; 165 } 166 167 /* Determine maximum supported aperture size. */ 168 value = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE); 169 pci_conf_write(sc->as_pc, sc->as_tag, 170 AGP_INTEL_APSIZE, APSIZE_MASK); 171 isc->aperture_mask = pci_conf_read(sc->as_pc, sc->as_tag, 172 AGP_INTEL_APSIZE) & APSIZE_MASK; 173 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE, value); 174 isc->initial_aperture = AGP_GET_APERTURE(sc); 175 176 for (;;) { 177 gatt = agp_alloc_gatt(sc); 178 if (gatt) 179 break; 180 181 /* 182 * Probably contigmalloc failure. Try reducing the 183 * aperture so that the gatt size reduces. 184 */ 185 if (AGP_SET_APERTURE(sc, AGP_GET_APERTURE(sc) / 2)) { 186 agp_generic_detach(sc); 187 aprint_error(": failed to set aperture\n"); 188 return ENOMEM; 189 } 190 } 191 isc->gatt = gatt; 192 193 /* Install the gatt. */ 194 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 195 gatt->ag_physical); 196 197 /* Enable the GLTB and setup the control register. */ 198 switch (isc->chiptype) { 199 case CHIP_I443: 200 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 201 AGPCTRL_AGPRSE | AGPCTRL_GTLB); 202 203 default: 204 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 205 pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL) 206 | AGPCTRL_GTLB); 207 } 208 209 /* Enable things, clear errors etc. */ 210 switch (isc->chiptype) { 211 case CHIP_I845: 212 case CHIP_I865: 213 { 214 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG); 215 reg |= MCHCFG_AAGN; 216 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG, reg); 217 break; 218 } 219 case CHIP_I840: 220 case CHIP_I850: 221 { 222 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD); 223 reg |= AGPCMD_AGPEN; 224 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD, 225 reg); 226 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG); 227 reg |= MCHCFG_AAGN; 228 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG, 229 reg); 230 break; 231 } 232 default: 233 { 234 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 235 reg &= ~NBXCFG_APAE; 236 reg |= NBXCFG_AAGN; 237 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 238 } 239 } 240 241 /* Clear Error status */ 242 switch (isc->chiptype) { 243 case CHIP_I840: 244 pci_conf_write(sc->as_pc, sc->as_tag, 245 AGP_INTEL_I8XX_ERRSTS, 0xc000); 246 break; 247 248 case CHIP_I845: 249 case CHIP_I850: 250 case CHIP_I865: 251 pci_conf_write(sc->as_pc, sc->as_tag, 252 AGP_INTEL_I8XX_ERRSTS, 0x00ff); 253 break; 254 255 default: 256 pci_conf_write(sc->as_pc, sc->as_tag, 257 AGP_INTEL_ERRSTS, 0x70); 258 } 259 260 isc->sc_powerhook = powerhook_establish(sc->as_dev.dv_xname, 261 agp_intel_powerhook, sc); 262 if (isc->sc_powerhook == NULL) 263 aprint_error("%s: couldn't establish powerhook\n", 264 sc->as_dev.dv_xname); 265 266 return (0); 267 } 268 269 #if 0 270 static int 271 agp_intel_detach(struct agp_softc *sc) 272 { 273 int error; 274 pcireg_t reg; 275 struct agp_intel_softc *isc = sc->as_chipc; 276 277 if (isc->sc_powerhook) 278 powerhook_disestablish(isc->sc_powerhook); 279 280 error = agp_generic_detach(sc); 281 if (error) 282 return error; 283 284 /* XXX i845/i855PM/i840/i850E */ 285 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 286 reg &= ~(1 << 9); 287 printf("%s: set NBXCFG to %x\n", __FUNCTION__, reg); 288 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 289 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 0); 290 AGP_SET_APERTURE(sc, isc->initial_aperture); 291 agp_free_gatt(sc, isc->gatt); 292 293 return 0; 294 } 295 #endif 296 297 static u_int32_t 298 agp_intel_get_aperture(struct agp_softc *sc) 299 { 300 struct agp_intel_softc *isc = sc->as_chipc; 301 u_int32_t apsize; 302 303 apsize = pci_conf_read(sc->as_pc, sc->as_tag, 304 AGP_INTEL_APSIZE) & isc->aperture_mask; 305 306 /* 307 * The size is determined by the number of low bits of 308 * register APBASE which are forced to zero. The low 22 bits 309 * are always forced to zero and each zero bit in the apsize 310 * field just read forces the corresponding bit in the 27:22 311 * to be zero. We calculate the aperture size accordingly. 312 */ 313 return (((apsize ^ isc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1; 314 } 315 316 static int 317 agp_intel_set_aperture(struct agp_softc *sc, u_int32_t aperture) 318 { 319 struct agp_intel_softc *isc = sc->as_chipc; 320 u_int32_t apsize; 321 322 /* 323 * Reverse the magic from get_aperture. 324 */ 325 apsize = ((aperture - 1) >> 22) ^ isc->aperture_mask; 326 327 /* 328 * Double check for sanity. 329 */ 330 if ((((apsize ^ isc->aperture_mask) << 22) | 331 ((1 << 22) - 1)) + 1 != aperture) 332 return EINVAL; 333 334 pci_conf_write(sc->as_pc, sc->as_tag, 335 AGP_INTEL_APSIZE, apsize); 336 337 return 0; 338 } 339 340 static int 341 agp_intel_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 342 { 343 struct agp_intel_softc *isc = sc->as_chipc; 344 345 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 346 return EINVAL; 347 348 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 349 return 0; 350 } 351 352 static int 353 agp_intel_unbind_page(struct agp_softc *sc, off_t offset) 354 { 355 struct agp_intel_softc *isc = sc->as_chipc; 356 357 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 358 return EINVAL; 359 360 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 361 return 0; 362 } 363 364 static void 365 agp_intel_flush_tlb(struct agp_softc *sc) 366 { 367 struct agp_intel_softc *isc = sc->as_chipc; 368 pcireg_t reg; 369 370 switch (isc->chiptype) { 371 case CHIP_I865: 372 case CHIP_I850: 373 case CHIP_I845: 374 case CHIP_I840: 375 case CHIP_I443: 376 { 377 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL); 378 reg &= ~AGPCTRL_GTLB; 379 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 380 reg); 381 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 382 reg | AGPCTRL_GTLB); 383 break; 384 } 385 default: /* XXX */ 386 { 387 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 388 0x2200); 389 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 390 0x2280); 391 } 392 } 393 } 394 395 static void 396 agp_intel_powerhook(int why, void *opaque) 397 { 398 struct agp_softc *sc; 399 struct agp_intel_softc *isc; 400 401 sc = (struct agp_softc *)opaque; 402 isc = (struct agp_intel_softc *)sc->as_chipc; 403 404 switch (why) { 405 case PWR_SUSPEND: 406 case PWR_STANDBY: 407 pci_conf_capture(sc->as_pc, sc->as_tag, &isc->sc_pciconf); 408 break; 409 case PWR_RESUME: 410 pci_conf_restore(sc->as_pc, sc->as_tag, &isc->sc_pciconf); 411 agp_flush_cache(); 412 break; 413 case PWR_SOFTSUSPEND: 414 case PWR_SOFTSTANDBY: 415 case PWR_SOFTRESUME: 416 break; 417 } 418 419 return; 420 } 421
Indexes created Thu Oct 02 01:09:59 GMT 2025