agp_intel.c revision 1.22.8.1
1 /* $NetBSD: agp_intel.c,v 1.22.8.1 2007/08/08 11:51:31 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/pci/agp_intel.c,v 1.4 2001/07/05 21:28:47 jhb Exp $ 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: agp_intel.c,v 1.22.8.1 2007/08/08 11:51:31 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/proc.h> 40 #include <sys/agpio.h> 41 #include <sys/device.h> 42 43 #include <uvm/uvm_extern.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/agpvar.h> 49 #include <dev/pci/agpreg.h> 50 51 #include <machine/bus.h> 52 53 struct agp_intel_softc { 54 u_int32_t initial_aperture; 55 /* aperture size at startup */ 56 struct agp_gatt *gatt; 57 struct pci_attach_args vga_pa; 58 u_int aperture_mask; 59 int chiptype; /* Chip type */ 60 #define CHIP_INTEL 0x0 61 #define CHIP_I443 0x1 62 #define CHIP_I840 0x2 63 #define CHIP_I845 0x3 64 #define CHIP_I850 0x4 65 #define CHIP_I865 0x5 66 67 }; 68 69 static u_int32_t agp_intel_get_aperture(struct agp_softc *); 70 static int agp_intel_set_aperture(struct agp_softc *, u_int32_t); 71 static int agp_intel_bind_page(struct agp_softc *, off_t, bus_addr_t); 72 static int agp_intel_unbind_page(struct agp_softc *, off_t); 73 static void agp_intel_flush_tlb(struct agp_softc *); 74 static pnp_status_t agp_intel_power(device_t, pnp_request_t, void *); 75 static int agp_intel_init(struct agp_softc *); 76 77 static struct agp_methods agp_intel_methods = { 78 agp_intel_get_aperture, 79 agp_intel_set_aperture, 80 agp_intel_bind_page, 81 agp_intel_unbind_page, 82 agp_intel_flush_tlb, 83 agp_generic_enable, 84 agp_generic_alloc_memory, 85 agp_generic_free_memory, 86 agp_generic_bind_memory, 87 agp_generic_unbind_memory, 88 }; 89 90 static int 91 agp_intel_vgamatch(struct pci_attach_args *pa) 92 { 93 switch (PCI_PRODUCT(pa->pa_id)) { 94 case PCI_PRODUCT_INTEL_82855PM_AGP: 95 case PCI_PRODUCT_INTEL_82443LX_AGP: 96 case PCI_PRODUCT_INTEL_82443BX_AGP: 97 case PCI_PRODUCT_INTEL_82443GX_AGP: 98 case PCI_PRODUCT_INTEL_82850_AGP: /* i850/i860 */ 99 case PCI_PRODUCT_INTEL_82845_AGP: 100 case PCI_PRODUCT_INTEL_82840_AGP: 101 case PCI_PRODUCT_INTEL_82865_AGP: 102 case PCI_PRODUCT_INTEL_82875P_AGP: 103 return (1); 104 } 105 106 return (0); 107 } 108 109 int 110 agp_intel_attach(struct device *parent, struct device *self, void *aux) 111 { 112 struct agp_softc *sc = (struct agp_softc *)self; 113 struct pci_attach_args *pa= aux; 114 struct agp_intel_softc *isc; 115 struct agp_gatt *gatt; 116 u_int32_t value; 117 118 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 119 if (isc == NULL) { 120 aprint_error(": can't allocate chipset-specific softc\n"); 121 return ENOMEM; 122 } 123 124 sc->as_methods = &agp_intel_methods; 125 sc->as_chipc = isc; 126 127 if (pci_find_device(&isc->vga_pa, agp_intel_vgamatch) == 0) { 128 aprint_normal(": using generic initialization for Intel AGP\n"); 129 aprint_normal("%s", sc->as_dev.dv_xname); 130 isc->chiptype = CHIP_INTEL; 131 } 132 133 pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, &sc->as_capoff, 134 NULL); 135 136 if (agp_map_aperture(pa, sc, AGP_APBASE) != 0) { 137 aprint_error(": can't map aperture\n"); 138 free(isc, M_AGP); 139 sc->as_chipc = NULL; 140 return ENXIO; 141 } 142 143 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 144 case PCI_PRODUCT_INTEL_82443LX_AGP: 145 case PCI_PRODUCT_INTEL_82443BX_AGP: 146 case PCI_PRODUCT_INTEL_82443GX_AGP: 147 isc->chiptype = CHIP_I443; 148 break; 149 case PCI_PRODUCT_INTEL_82840_AGP: 150 isc->chiptype = CHIP_I840; 151 break; 152 case PCI_PRODUCT_INTEL_82855PM_AGP: 153 case PCI_PRODUCT_INTEL_82845_AGP: 154 isc->chiptype = CHIP_I845; 155 break; 156 case PCI_PRODUCT_INTEL_82850_AGP: 157 isc->chiptype = CHIP_I850; 158 break; 159 case PCI_PRODUCT_INTEL_82865_AGP: 160 case PCI_PRODUCT_INTEL_82875P_AGP: 161 isc->chiptype = CHIP_I865; 162 break; 163 } 164 165 /* Determine maximum supported aperture size. */ 166 value = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE); 167 pci_conf_write(sc->as_pc, sc->as_tag, 168 AGP_INTEL_APSIZE, APSIZE_MASK); 169 isc->aperture_mask = pci_conf_read(sc->as_pc, sc->as_tag, 170 AGP_INTEL_APSIZE) & APSIZE_MASK; 171 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE, value); 172 isc->initial_aperture = AGP_GET_APERTURE(sc); 173 174 for (;;) { 175 gatt = agp_alloc_gatt(sc); 176 if (gatt) 177 break; 178 179 /* 180 * Probably contigmalloc failure. Try reducing the 181 * aperture so that the gatt size reduces. 182 */ 183 if (AGP_SET_APERTURE(sc, AGP_GET_APERTURE(sc) / 2)) { 184 agp_generic_detach(sc); 185 aprint_error(": failed to set aperture\n"); 186 return ENOMEM; 187 } 188 } 189 isc->gatt = gatt; 190 191 if (pnp_register(self, agp_intel_power) != PNP_STATUS_SUCCESS) 192 aprint_error("%s: couldn't establish power handler\n", 193 device_xname(self)); 194 195 return agp_intel_init(sc); 196 } 197 198 static int 199 agp_intel_init(struct agp_softc *sc) 200 { 201 struct agp_intel_softc *isc = sc->as_chipc; 202 struct agp_gatt *gatt = isc->gatt; 203 pcireg_t reg; 204 205 /* Install the gatt. */ 206 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 207 gatt->ag_physical); 208 209 /* Enable the GLTB and setup the control register. */ 210 switch (isc->chiptype) { 211 case CHIP_I443: 212 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 213 AGPCTRL_AGPRSE | AGPCTRL_GTLB); 214 215 default: 216 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 217 pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL) 218 | AGPCTRL_GTLB); 219 } 220 221 /* Enable things, clear errors etc. */ 222 switch (isc->chiptype) { 223 case CHIP_I845: 224 case CHIP_I865: 225 { 226 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG); 227 reg |= MCHCFG_AAGN; 228 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG, reg); 229 break; 230 } 231 case CHIP_I840: 232 case CHIP_I850: 233 { 234 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD); 235 reg |= AGPCMD_AGPEN; 236 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD, 237 reg); 238 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG); 239 reg |= MCHCFG_AAGN; 240 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG, 241 reg); 242 break; 243 } 244 default: 245 { 246 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 247 reg &= ~NBXCFG_APAE; 248 reg |= NBXCFG_AAGN; 249 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 250 } 251 } 252 253 /* Clear Error status */ 254 switch (isc->chiptype) { 255 case CHIP_I840: 256 pci_conf_write(sc->as_pc, sc->as_tag, 257 AGP_INTEL_I8XX_ERRSTS, 0xc000); 258 break; 259 260 case CHIP_I845: 261 case CHIP_I850: 262 case CHIP_I865: 263 pci_conf_write(sc->as_pc, sc->as_tag, 264 AGP_INTEL_I8XX_ERRSTS, 0x00ff); 265 break; 266 267 default: 268 pci_conf_write(sc->as_pc, sc->as_tag, 269 AGP_INTEL_ERRSTS, 0x70); 270 } 271 272 return (0); 273 } 274 275 #if 0 276 static int 277 agp_intel_detach(struct agp_softc *sc) 278 { 279 int error; 280 pcireg_t reg; 281 struct agp_intel_softc *isc = sc->as_chipc; 282 283 error = agp_generic_detach(sc); 284 if (error) 285 return error; 286 287 /* XXX i845/i855PM/i840/i850E */ 288 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 289 reg &= ~(1 << 9); 290 printf("%s: set NBXCFG to %x\n", __FUNCTION__, reg); 291 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 292 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 0); 293 AGP_SET_APERTURE(sc, isc->initial_aperture); 294 agp_free_gatt(sc, isc->gatt); 295 296 return 0; 297 } 298 #endif 299 300 static u_int32_t 301 agp_intel_get_aperture(struct agp_softc *sc) 302 { 303 struct agp_intel_softc *isc = sc->as_chipc; 304 u_int32_t apsize; 305 306 apsize = pci_conf_read(sc->as_pc, sc->as_tag, 307 AGP_INTEL_APSIZE) & isc->aperture_mask; 308 309 /* 310 * The size is determined by the number of low bits of 311 * register APBASE which are forced to zero. The low 22 bits 312 * are always forced to zero and each zero bit in the apsize 313 * field just read forces the corresponding bit in the 27:22 314 * to be zero. We calculate the aperture size accordingly. 315 */ 316 return (((apsize ^ isc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1; 317 } 318 319 static int 320 agp_intel_set_aperture(struct agp_softc *sc, u_int32_t aperture) 321 { 322 struct agp_intel_softc *isc = sc->as_chipc; 323 u_int32_t apsize; 324 325 /* 326 * Reverse the magic from get_aperture. 327 */ 328 apsize = ((aperture - 1) >> 22) ^ isc->aperture_mask; 329 330 /* 331 * Double check for sanity. 332 */ 333 if ((((apsize ^ isc->aperture_mask) << 22) | 334 ((1 << 22) - 1)) + 1 != aperture) 335 return EINVAL; 336 337 pci_conf_write(sc->as_pc, sc->as_tag, 338 AGP_INTEL_APSIZE, apsize); 339 340 return 0; 341 } 342 343 static int 344 agp_intel_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 345 { 346 struct agp_intel_softc *isc = sc->as_chipc; 347 348 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 349 return EINVAL; 350 351 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 352 return 0; 353 } 354 355 static int 356 agp_intel_unbind_page(struct agp_softc *sc, off_t offset) 357 { 358 struct agp_intel_softc *isc = sc->as_chipc; 359 360 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 361 return EINVAL; 362 363 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 364 return 0; 365 } 366 367 static void 368 agp_intel_flush_tlb(struct agp_softc *sc) 369 { 370 struct agp_intel_softc *isc = sc->as_chipc; 371 pcireg_t reg; 372 373 switch (isc->chiptype) { 374 case CHIP_I865: 375 case CHIP_I850: 376 case CHIP_I845: 377 case CHIP_I840: 378 case CHIP_I443: 379 { 380 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL); 381 reg &= ~AGPCTRL_GTLB; 382 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 383 reg); 384 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 385 reg | AGPCTRL_GTLB); 386 break; 387 } 388 default: /* XXX */ 389 { 390 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 391 0x2200); 392 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 393 0x2280); 394 } 395 } 396 } 397 398 static pnp_status_t 399 agp_intel_power(device_t dv, pnp_request_t req, void *opaque) 400 { 401 struct agp_softc *sc; 402 pnp_capabilities_t *pcaps; 403 pnp_state_t *pstate; 404 405 sc = (struct agp_softc *)dv; 406 407 switch (req) { 408 case PNP_REQUEST_GET_CAPABILITIES: 409 pcaps = opaque; 410 pcaps->state = PNP_STATE_D0 | PNP_STATE_D3; 411 break; 412 case PNP_REQUEST_GET_STATE: 413 pstate = opaque; 414 *pstate = PNP_STATE_D0; /* XXX */ 415 break; 416 case PNP_REQUEST_SET_STATE: 417 pstate = opaque; 418 switch (*pstate) { 419 case PNP_STATE_D0: 420 (void)agp_power(dv, req, opaque); 421 agp_intel_init(sc); 422 agp_flush_cache(); 423 break; 424 case PNP_STATE_D3: 425 (void)agp_power(dv, req, opaque); 426 break; 427 default: 428 return PNP_STATUS_UNSUPPORTED; 429 } 430 break; 431 default: 432 return PNP_STATUS_UNSUPPORTED; 433 } 434 435 return PNP_STATUS_SUCCESS; 436 } 437
Indexes created Thu Oct 02 01:09:59 GMT 2025