agp_intel.c revision 1.22.8.2
1 /* $NetBSD: agp_intel.c,v 1.22.8.2 2007/10/01 05:37:32 joerg Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/pci/agp_intel.c,v 1.4 2001/07/05 21:28:47 jhb Exp $ 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: agp_intel.c,v 1.22.8.2 2007/10/01 05:37:32 joerg Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/proc.h> 40 #include <sys/agpio.h> 41 #include <sys/device.h> 42 43 #include <uvm/uvm_extern.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/agpvar.h> 49 #include <dev/pci/agpreg.h> 50 51 #include <machine/bus.h> 52 53 struct agp_intel_softc { 54 u_int32_t initial_aperture; 55 /* aperture size at startup */ 56 struct agp_gatt *gatt; 57 struct pci_attach_args vga_pa; 58 u_int aperture_mask; 59 int chiptype; /* Chip type */ 60 #define CHIP_INTEL 0x0 61 #define CHIP_I443 0x1 62 #define CHIP_I840 0x2 63 #define CHIP_I845 0x3 64 #define CHIP_I850 0x4 65 #define CHIP_I865 0x5 66 67 }; 68 69 static u_int32_t agp_intel_get_aperture(struct agp_softc *); 70 static int agp_intel_set_aperture(struct agp_softc *, u_int32_t); 71 static int agp_intel_bind_page(struct agp_softc *, off_t, bus_addr_t); 72 static int agp_intel_unbind_page(struct agp_softc *, off_t); 73 static void agp_intel_flush_tlb(struct agp_softc *); 74 static int agp_intel_init(struct agp_softc *); 75 static void agp_intel_resume(device_t); 76 77 static struct agp_methods agp_intel_methods = { 78 agp_intel_get_aperture, 79 agp_intel_set_aperture, 80 agp_intel_bind_page, 81 agp_intel_unbind_page, 82 agp_intel_flush_tlb, 83 agp_generic_enable, 84 agp_generic_alloc_memory, 85 agp_generic_free_memory, 86 agp_generic_bind_memory, 87 agp_generic_unbind_memory, 88 }; 89 90 static int 91 agp_intel_vgamatch(struct pci_attach_args *pa) 92 { 93 switch (PCI_PRODUCT(pa->pa_id)) { 94 case PCI_PRODUCT_INTEL_82855PM_AGP: 95 case PCI_PRODUCT_INTEL_82443LX_AGP: 96 case PCI_PRODUCT_INTEL_82443BX_AGP: 97 case PCI_PRODUCT_INTEL_82443GX_AGP: 98 case PCI_PRODUCT_INTEL_82850_AGP: /* i850/i860 */ 99 case PCI_PRODUCT_INTEL_82845_AGP: 100 case PCI_PRODUCT_INTEL_82840_AGP: 101 case PCI_PRODUCT_INTEL_82865_AGP: 102 case PCI_PRODUCT_INTEL_82875P_AGP: 103 return (1); 104 } 105 106 return (0); 107 } 108 109 int 110 agp_intel_attach(struct device *parent, struct device *self, void *aux) 111 { 112 struct agp_softc *sc = (struct agp_softc *)self; 113 struct pci_attach_args *pa= aux; 114 struct agp_intel_softc *isc; 115 struct agp_gatt *gatt; 116 u_int32_t value; 117 pnp_status_t pnp_status; 118 119 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 120 if (isc == NULL) { 121 aprint_error(": can't allocate chipset-specific softc\n"); 122 return ENOMEM; 123 } 124 125 sc->as_methods = &agp_intel_methods; 126 sc->as_chipc = isc; 127 128 if (pci_find_device(&isc->vga_pa, agp_intel_vgamatch) == 0) { 129 aprint_normal(": using generic initialization for Intel AGP\n"); 130 aprint_normal("%s", sc->as_dev.dv_xname); 131 isc->chiptype = CHIP_INTEL; 132 } 133 134 pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, &sc->as_capoff, 135 NULL); 136 137 if (agp_map_aperture(pa, sc, AGP_APBASE) != 0) { 138 aprint_error(": can't map aperture\n"); 139 free(isc, M_AGP); 140 sc->as_chipc = NULL; 141 return ENXIO; 142 } 143 144 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 145 case PCI_PRODUCT_INTEL_82443LX_AGP: 146 case PCI_PRODUCT_INTEL_82443BX_AGP: 147 case PCI_PRODUCT_INTEL_82443GX_AGP: 148 isc->chiptype = CHIP_I443; 149 break; 150 case PCI_PRODUCT_INTEL_82840_AGP: 151 isc->chiptype = CHIP_I840; 152 break; 153 case PCI_PRODUCT_INTEL_82855PM_AGP: 154 case PCI_PRODUCT_INTEL_82845_AGP: 155 isc->chiptype = CHIP_I845; 156 break; 157 case PCI_PRODUCT_INTEL_82850_AGP: 158 isc->chiptype = CHIP_I850; 159 break; 160 case PCI_PRODUCT_INTEL_82865_AGP: 161 case PCI_PRODUCT_INTEL_82875P_AGP: 162 isc->chiptype = CHIP_I865; 163 break; 164 } 165 166 /* Determine maximum supported aperture size. */ 167 value = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE); 168 pci_conf_write(sc->as_pc, sc->as_tag, 169 AGP_INTEL_APSIZE, APSIZE_MASK); 170 isc->aperture_mask = pci_conf_read(sc->as_pc, sc->as_tag, 171 AGP_INTEL_APSIZE) & APSIZE_MASK; 172 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE, value); 173 isc->initial_aperture = AGP_GET_APERTURE(sc); 174 175 for (;;) { 176 gatt = agp_alloc_gatt(sc); 177 if (gatt) 178 break; 179 180 /* 181 * Probably contigmalloc failure. Try reducing the 182 * aperture so that the gatt size reduces. 183 */ 184 if (AGP_SET_APERTURE(sc, AGP_GET_APERTURE(sc) / 2)) { 185 agp_generic_detach(sc); 186 aprint_error(": failed to set aperture\n"); 187 return ENOMEM; 188 } 189 } 190 isc->gatt = gatt; 191 192 pnp_status = pci_generic_power_register(self, 193 pa->pa_pc, pa->pa_tag, NULL, agp_intel_resume); 194 195 if (pnp_status != PNP_STATUS_SUCCESS) 196 aprint_error("%s: couldn't establish power handler\n", 197 device_xname(self)); 198 199 return agp_intel_init(sc); 200 } 201 202 static int 203 agp_intel_init(struct agp_softc *sc) 204 { 205 struct agp_intel_softc *isc = sc->as_chipc; 206 struct agp_gatt *gatt = isc->gatt; 207 pcireg_t reg; 208 209 /* Install the gatt. */ 210 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 211 gatt->ag_physical); 212 213 /* Enable the GLTB and setup the control register. */ 214 switch (isc->chiptype) { 215 case CHIP_I443: 216 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 217 AGPCTRL_AGPRSE | AGPCTRL_GTLB); 218 219 default: 220 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 221 pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL) 222 | AGPCTRL_GTLB); 223 } 224 225 /* Enable things, clear errors etc. */ 226 switch (isc->chiptype) { 227 case CHIP_I845: 228 case CHIP_I865: 229 { 230 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG); 231 reg |= MCHCFG_AAGN; 232 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG, reg); 233 break; 234 } 235 case CHIP_I840: 236 case CHIP_I850: 237 { 238 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD); 239 reg |= AGPCMD_AGPEN; 240 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD, 241 reg); 242 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG); 243 reg |= MCHCFG_AAGN; 244 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG, 245 reg); 246 break; 247 } 248 default: 249 { 250 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 251 reg &= ~NBXCFG_APAE; 252 reg |= NBXCFG_AAGN; 253 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 254 } 255 } 256 257 /* Clear Error status */ 258 switch (isc->chiptype) { 259 case CHIP_I840: 260 pci_conf_write(sc->as_pc, sc->as_tag, 261 AGP_INTEL_I8XX_ERRSTS, 0xc000); 262 break; 263 264 case CHIP_I845: 265 case CHIP_I850: 266 case CHIP_I865: 267 pci_conf_write(sc->as_pc, sc->as_tag, 268 AGP_INTEL_I8XX_ERRSTS, 0x00ff); 269 break; 270 271 default: 272 pci_conf_write(sc->as_pc, sc->as_tag, 273 AGP_INTEL_ERRSTS, 0x70); 274 } 275 276 return (0); 277 } 278 279 #if 0 280 static int 281 agp_intel_detach(struct agp_softc *sc) 282 { 283 int error; 284 pcireg_t reg; 285 struct agp_intel_softc *isc = sc->as_chipc; 286 287 error = agp_generic_detach(sc); 288 if (error) 289 return error; 290 291 /* XXX i845/i855PM/i840/i850E */ 292 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 293 reg &= ~(1 << 9); 294 printf("%s: set NBXCFG to %x\n", __FUNCTION__, reg); 295 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 296 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 0); 297 AGP_SET_APERTURE(sc, isc->initial_aperture); 298 agp_free_gatt(sc, isc->gatt); 299 300 return 0; 301 } 302 #endif 303 304 static u_int32_t 305 agp_intel_get_aperture(struct agp_softc *sc) 306 { 307 struct agp_intel_softc *isc = sc->as_chipc; 308 u_int32_t apsize; 309 310 apsize = pci_conf_read(sc->as_pc, sc->as_tag, 311 AGP_INTEL_APSIZE) & isc->aperture_mask; 312 313 /* 314 * The size is determined by the number of low bits of 315 * register APBASE which are forced to zero. The low 22 bits 316 * are always forced to zero and each zero bit in the apsize 317 * field just read forces the corresponding bit in the 27:22 318 * to be zero. We calculate the aperture size accordingly. 319 */ 320 return (((apsize ^ isc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1; 321 } 322 323 static int 324 agp_intel_set_aperture(struct agp_softc *sc, u_int32_t aperture) 325 { 326 struct agp_intel_softc *isc = sc->as_chipc; 327 u_int32_t apsize; 328 329 /* 330 * Reverse the magic from get_aperture. 331 */ 332 apsize = ((aperture - 1) >> 22) ^ isc->aperture_mask; 333 334 /* 335 * Double check for sanity. 336 */ 337 if ((((apsize ^ isc->aperture_mask) << 22) | 338 ((1 << 22) - 1)) + 1 != aperture) 339 return EINVAL; 340 341 pci_conf_write(sc->as_pc, sc->as_tag, 342 AGP_INTEL_APSIZE, apsize); 343 344 return 0; 345 } 346 347 static int 348 agp_intel_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 349 { 350 struct agp_intel_softc *isc = sc->as_chipc; 351 352 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 353 return EINVAL; 354 355 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 356 return 0; 357 } 358 359 static int 360 agp_intel_unbind_page(struct agp_softc *sc, off_t offset) 361 { 362 struct agp_intel_softc *isc = sc->as_chipc; 363 364 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 365 return EINVAL; 366 367 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 368 return 0; 369 } 370 371 static void 372 agp_intel_flush_tlb(struct agp_softc *sc) 373 { 374 struct agp_intel_softc *isc = sc->as_chipc; 375 pcireg_t reg; 376 377 switch (isc->chiptype) { 378 case CHIP_I865: 379 case CHIP_I850: 380 case CHIP_I845: 381 case CHIP_I840: 382 case CHIP_I443: 383 { 384 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL); 385 reg &= ~AGPCTRL_GTLB; 386 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 387 reg); 388 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 389 reg | AGPCTRL_GTLB); 390 break; 391 } 392 default: /* XXX */ 393 { 394 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 395 0x2200); 396 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 397 0x2280); 398 } 399 } 400 } 401 402 static 403 void agp_intel_resume(device_t dv) 404 { 405 struct agp_softc *sc = device_private(dv); 406 407 agp_intel_init(sc); 408 agp_flush_cache(); 409 } 410
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