agp_intel.c revision 1.24
1 /* $NetBSD: agp_intel.c,v 1.24 2007/11/12 20:00:17 joerg Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/pci/agp_intel.c,v 1.4 2001/07/05 21:28:47 jhb Exp $ 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: agp_intel.c,v 1.24 2007/11/12 20:00:17 joerg Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/proc.h> 40 #include <sys/agpio.h> 41 #include <sys/device.h> 42 43 #include <uvm/uvm_extern.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/agpvar.h> 49 #include <dev/pci/agpreg.h> 50 51 #include <sys/bus.h> 52 53 struct agp_intel_softc { 54 u_int32_t initial_aperture; 55 /* aperture size at startup */ 56 struct agp_gatt *gatt; 57 struct pci_attach_args vga_pa; 58 u_int aperture_mask; 59 int chiptype; /* Chip type */ 60 #define CHIP_INTEL 0x0 61 #define CHIP_I443 0x1 62 #define CHIP_I840 0x2 63 #define CHIP_I845 0x3 64 #define CHIP_I850 0x4 65 #define CHIP_I865 0x5 66 67 void *sc_powerhook; 68 struct pci_conf_state sc_pciconf; 69 }; 70 71 static u_int32_t agp_intel_get_aperture(struct agp_softc *); 72 static int agp_intel_set_aperture(struct agp_softc *, u_int32_t); 73 static int agp_intel_bind_page(struct agp_softc *, off_t, bus_addr_t); 74 static int agp_intel_unbind_page(struct agp_softc *, off_t); 75 static void agp_intel_flush_tlb(struct agp_softc *); 76 static void agp_intel_powerhook(int, void *); 77 static int agp_intel_init(struct agp_softc *); 78 79 static struct agp_methods agp_intel_methods = { 80 agp_intel_get_aperture, 81 agp_intel_set_aperture, 82 agp_intel_bind_page, 83 agp_intel_unbind_page, 84 agp_intel_flush_tlb, 85 agp_generic_enable, 86 agp_generic_alloc_memory, 87 agp_generic_free_memory, 88 agp_generic_bind_memory, 89 agp_generic_unbind_memory, 90 }; 91 92 static int 93 agp_intel_vgamatch(struct pci_attach_args *pa) 94 { 95 switch (PCI_PRODUCT(pa->pa_id)) { 96 case PCI_PRODUCT_INTEL_82855PM_AGP: 97 case PCI_PRODUCT_INTEL_82443LX_AGP: 98 case PCI_PRODUCT_INTEL_82443BX_AGP: 99 case PCI_PRODUCT_INTEL_82443GX_AGP: 100 case PCI_PRODUCT_INTEL_82850_AGP: /* i850/i860 */ 101 case PCI_PRODUCT_INTEL_82845_AGP: 102 case PCI_PRODUCT_INTEL_82840_AGP: 103 case PCI_PRODUCT_INTEL_82865_AGP: 104 case PCI_PRODUCT_INTEL_82875P_AGP: 105 return (1); 106 } 107 108 return (0); 109 } 110 111 int 112 agp_intel_attach(struct device *parent, struct device *self, void *aux) 113 { 114 struct agp_softc *sc = (struct agp_softc *)self; 115 struct pci_attach_args *pa= aux; 116 struct agp_intel_softc *isc; 117 struct agp_gatt *gatt; 118 u_int32_t value; 119 120 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 121 if (isc == NULL) { 122 aprint_error(": can't allocate chipset-specific softc\n"); 123 return ENOMEM; 124 } 125 126 sc->as_methods = &agp_intel_methods; 127 sc->as_chipc = isc; 128 129 if (pci_find_device(&isc->vga_pa, agp_intel_vgamatch) == 0) { 130 aprint_normal(": using generic initialization for Intel AGP\n"); 131 aprint_normal("%s", sc->as_dev.dv_xname); 132 isc->chiptype = CHIP_INTEL; 133 } 134 135 pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, &sc->as_capoff, 136 NULL); 137 138 if (agp_map_aperture(pa, sc, AGP_APBASE) != 0) { 139 aprint_error(": can't map aperture\n"); 140 free(isc, M_AGP); 141 sc->as_chipc = NULL; 142 return ENXIO; 143 } 144 145 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 146 case PCI_PRODUCT_INTEL_82443LX_AGP: 147 case PCI_PRODUCT_INTEL_82443BX_AGP: 148 case PCI_PRODUCT_INTEL_82443GX_AGP: 149 isc->chiptype = CHIP_I443; 150 break; 151 case PCI_PRODUCT_INTEL_82840_AGP: 152 isc->chiptype = CHIP_I840; 153 break; 154 case PCI_PRODUCT_INTEL_82855PM_AGP: 155 case PCI_PRODUCT_INTEL_82845_AGP: 156 isc->chiptype = CHIP_I845; 157 break; 158 case PCI_PRODUCT_INTEL_82850_AGP: 159 isc->chiptype = CHIP_I850; 160 break; 161 case PCI_PRODUCT_INTEL_82865_AGP: 162 case PCI_PRODUCT_INTEL_82875P_AGP: 163 isc->chiptype = CHIP_I865; 164 break; 165 } 166 167 /* Determine maximum supported aperture size. */ 168 value = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE); 169 pci_conf_write(sc->as_pc, sc->as_tag, 170 AGP_INTEL_APSIZE, APSIZE_MASK); 171 isc->aperture_mask = pci_conf_read(sc->as_pc, sc->as_tag, 172 AGP_INTEL_APSIZE) & APSIZE_MASK; 173 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE, value); 174 isc->initial_aperture = AGP_GET_APERTURE(sc); 175 176 for (;;) { 177 gatt = agp_alloc_gatt(sc); 178 if (gatt) 179 break; 180 181 /* 182 * Probably contigmalloc failure. Try reducing the 183 * aperture so that the gatt size reduces. 184 */ 185 if (AGP_SET_APERTURE(sc, AGP_GET_APERTURE(sc) / 2)) { 186 agp_generic_detach(sc); 187 aprint_error(": failed to set aperture\n"); 188 return ENOMEM; 189 } 190 } 191 isc->gatt = gatt; 192 193 return agp_intel_init(sc); 194 } 195 196 static int 197 agp_intel_init(struct agp_softc *sc) 198 { 199 struct agp_intel_softc *isc = sc->as_chipc; 200 struct agp_gatt *gatt = isc->gatt; 201 pcireg_t reg; 202 203 /* Install the gatt. */ 204 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 205 gatt->ag_physical); 206 207 /* Enable the GLTB and setup the control register. */ 208 switch (isc->chiptype) { 209 case CHIP_I443: 210 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 211 AGPCTRL_AGPRSE | AGPCTRL_GTLB); 212 213 default: 214 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 215 pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL) 216 | AGPCTRL_GTLB); 217 } 218 219 /* Enable things, clear errors etc. */ 220 switch (isc->chiptype) { 221 case CHIP_I845: 222 case CHIP_I865: 223 { 224 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG); 225 reg |= MCHCFG_AAGN; 226 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG, reg); 227 break; 228 } 229 case CHIP_I840: 230 case CHIP_I850: 231 { 232 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD); 233 reg |= AGPCMD_AGPEN; 234 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD, 235 reg); 236 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG); 237 reg |= MCHCFG_AAGN; 238 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG, 239 reg); 240 break; 241 } 242 default: 243 { 244 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 245 reg &= ~NBXCFG_APAE; 246 reg |= NBXCFG_AAGN; 247 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 248 } 249 } 250 251 /* Clear Error status */ 252 switch (isc->chiptype) { 253 case CHIP_I840: 254 pci_conf_write(sc->as_pc, sc->as_tag, 255 AGP_INTEL_I8XX_ERRSTS, 0xc000); 256 break; 257 258 case CHIP_I845: 259 case CHIP_I850: 260 case CHIP_I865: 261 pci_conf_write(sc->as_pc, sc->as_tag, 262 AGP_INTEL_I8XX_ERRSTS, 0x00ff); 263 break; 264 265 default: 266 pci_conf_write(sc->as_pc, sc->as_tag, 267 AGP_INTEL_ERRSTS, 0x70); 268 } 269 270 isc->sc_powerhook = powerhook_establish(sc->as_dev.dv_xname, 271 agp_intel_powerhook, sc); 272 if (isc->sc_powerhook == NULL) 273 aprint_error("%s: couldn't establish powerhook\n", 274 sc->as_dev.dv_xname); 275 276 return (0); 277 } 278 279 #if 0 280 static int 281 agp_intel_detach(struct agp_softc *sc) 282 { 283 int error; 284 pcireg_t reg; 285 struct agp_intel_softc *isc = sc->as_chipc; 286 287 if (isc->sc_powerhook) 288 powerhook_disestablish(isc->sc_powerhook); 289 290 error = agp_generic_detach(sc); 291 if (error) 292 return error; 293 294 /* XXX i845/i855PM/i840/i850E */ 295 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 296 reg &= ~(1 << 9); 297 printf("%s: set NBXCFG to %x\n", __FUNCTION__, reg); 298 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 299 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 0); 300 AGP_SET_APERTURE(sc, isc->initial_aperture); 301 agp_free_gatt(sc, isc->gatt); 302 303 return 0; 304 } 305 #endif 306 307 static u_int32_t 308 agp_intel_get_aperture(struct agp_softc *sc) 309 { 310 struct agp_intel_softc *isc = sc->as_chipc; 311 u_int32_t apsize; 312 313 apsize = pci_conf_read(sc->as_pc, sc->as_tag, 314 AGP_INTEL_APSIZE) & isc->aperture_mask; 315 316 /* 317 * The size is determined by the number of low bits of 318 * register APBASE which are forced to zero. The low 22 bits 319 * are always forced to zero and each zero bit in the apsize 320 * field just read forces the corresponding bit in the 27:22 321 * to be zero. We calculate the aperture size accordingly. 322 */ 323 return (((apsize ^ isc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1; 324 } 325 326 static int 327 agp_intel_set_aperture(struct agp_softc *sc, u_int32_t aperture) 328 { 329 struct agp_intel_softc *isc = sc->as_chipc; 330 u_int32_t apsize; 331 332 /* 333 * Reverse the magic from get_aperture. 334 */ 335 apsize = ((aperture - 1) >> 22) ^ isc->aperture_mask; 336 337 /* 338 * Double check for sanity. 339 */ 340 if ((((apsize ^ isc->aperture_mask) << 22) | 341 ((1 << 22) - 1)) + 1 != aperture) 342 return EINVAL; 343 344 pci_conf_write(sc->as_pc, sc->as_tag, 345 AGP_INTEL_APSIZE, apsize); 346 347 return 0; 348 } 349 350 static int 351 agp_intel_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 352 { 353 struct agp_intel_softc *isc = sc->as_chipc; 354 355 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 356 return EINVAL; 357 358 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 359 return 0; 360 } 361 362 static int 363 agp_intel_unbind_page(struct agp_softc *sc, off_t offset) 364 { 365 struct agp_intel_softc *isc = sc->as_chipc; 366 367 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 368 return EINVAL; 369 370 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 371 return 0; 372 } 373 374 static void 375 agp_intel_flush_tlb(struct agp_softc *sc) 376 { 377 struct agp_intel_softc *isc = sc->as_chipc; 378 pcireg_t reg; 379 380 switch (isc->chiptype) { 381 case CHIP_I865: 382 case CHIP_I850: 383 case CHIP_I845: 384 case CHIP_I840: 385 case CHIP_I443: 386 { 387 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL); 388 reg &= ~AGPCTRL_GTLB; 389 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 390 reg); 391 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 392 reg | AGPCTRL_GTLB); 393 break; 394 } 395 default: /* XXX */ 396 { 397 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 398 0x2200); 399 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 400 0x2280); 401 } 402 } 403 } 404 405 static void 406 agp_intel_powerhook(int why, void *opaque) 407 { 408 struct agp_softc *sc; 409 struct agp_intel_softc *isc; 410 411 sc = (struct agp_softc *)opaque; 412 isc = (struct agp_intel_softc *)sc->as_chipc; 413 414 switch (why) { 415 case PWR_SUSPEND: 416 case PWR_STANDBY: 417 pci_conf_capture(sc->as_pc, sc->as_tag, &isc->sc_pciconf); 418 break; 419 case PWR_RESUME: 420 pci_conf_restore(sc->as_pc, sc->as_tag, &isc->sc_pciconf); 421 agp_flush_cache(); 422 break; 423 case PWR_SOFTSUSPEND: 424 case PWR_SOFTSTANDBY: 425 case PWR_SOFTRESUME: 426 break; 427 } 428 429 return; 430 } 431
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