agp_intel.c revision 1.25
1 /* $NetBSD: agp_intel.c,v 1.25 2007/12/09 20:28:05 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/pci/agp_intel.c,v 1.4 2001/07/05 21:28:47 jhb Exp $ 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: agp_intel.c,v 1.25 2007/12/09 20:28:05 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/proc.h> 40 #include <sys/agpio.h> 41 #include <sys/device.h> 42 43 #include <uvm/uvm_extern.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/agpvar.h> 49 #include <dev/pci/agpreg.h> 50 51 #include <sys/bus.h> 52 53 struct agp_intel_softc { 54 u_int32_t initial_aperture; 55 /* aperture size at startup */ 56 struct agp_gatt *gatt; 57 struct pci_attach_args vga_pa; 58 u_int aperture_mask; 59 int chiptype; /* Chip type */ 60 #define CHIP_INTEL 0x0 61 #define CHIP_I443 0x1 62 #define CHIP_I840 0x2 63 #define CHIP_I845 0x3 64 #define CHIP_I850 0x4 65 #define CHIP_I865 0x5 66 67 }; 68 69 static u_int32_t agp_intel_get_aperture(struct agp_softc *); 70 static int agp_intel_set_aperture(struct agp_softc *, u_int32_t); 71 static int agp_intel_bind_page(struct agp_softc *, off_t, bus_addr_t); 72 static int agp_intel_unbind_page(struct agp_softc *, off_t); 73 static void agp_intel_flush_tlb(struct agp_softc *); 74 static int agp_intel_init(struct agp_softc *); 75 static bool agp_intel_resume(device_t); 76 77 static struct agp_methods agp_intel_methods = { 78 agp_intel_get_aperture, 79 agp_intel_set_aperture, 80 agp_intel_bind_page, 81 agp_intel_unbind_page, 82 agp_intel_flush_tlb, 83 agp_generic_enable, 84 agp_generic_alloc_memory, 85 agp_generic_free_memory, 86 agp_generic_bind_memory, 87 agp_generic_unbind_memory, 88 }; 89 90 static int 91 agp_intel_vgamatch(struct pci_attach_args *pa) 92 { 93 switch (PCI_PRODUCT(pa->pa_id)) { 94 case PCI_PRODUCT_INTEL_82855PM_AGP: 95 case PCI_PRODUCT_INTEL_82443LX_AGP: 96 case PCI_PRODUCT_INTEL_82443BX_AGP: 97 case PCI_PRODUCT_INTEL_82443GX_AGP: 98 case PCI_PRODUCT_INTEL_82850_AGP: /* i850/i860 */ 99 case PCI_PRODUCT_INTEL_82845_AGP: 100 case PCI_PRODUCT_INTEL_82840_AGP: 101 case PCI_PRODUCT_INTEL_82865_AGP: 102 case PCI_PRODUCT_INTEL_82875P_AGP: 103 return (1); 104 } 105 106 return (0); 107 } 108 109 int 110 agp_intel_attach(struct device *parent, struct device *self, void *aux) 111 { 112 struct agp_softc *sc = (struct agp_softc *)self; 113 struct pci_attach_args *pa= aux; 114 struct agp_intel_softc *isc; 115 struct agp_gatt *gatt; 116 u_int32_t value; 117 118 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 119 if (isc == NULL) { 120 aprint_error(": can't allocate chipset-specific softc\n"); 121 return ENOMEM; 122 } 123 124 sc->as_methods = &agp_intel_methods; 125 sc->as_chipc = isc; 126 127 if (pci_find_device(&isc->vga_pa, agp_intel_vgamatch) == 0) { 128 aprint_normal(": using generic initialization for Intel AGP\n"); 129 aprint_normal("%s", sc->as_dev.dv_xname); 130 isc->chiptype = CHIP_INTEL; 131 } 132 133 pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, &sc->as_capoff, 134 NULL); 135 136 if (agp_map_aperture(pa, sc, AGP_APBASE) != 0) { 137 aprint_error(": can't map aperture\n"); 138 free(isc, M_AGP); 139 sc->as_chipc = NULL; 140 return ENXIO; 141 } 142 143 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 144 case PCI_PRODUCT_INTEL_82443LX_AGP: 145 case PCI_PRODUCT_INTEL_82443BX_AGP: 146 case PCI_PRODUCT_INTEL_82443GX_AGP: 147 isc->chiptype = CHIP_I443; 148 break; 149 case PCI_PRODUCT_INTEL_82840_AGP: 150 isc->chiptype = CHIP_I840; 151 break; 152 case PCI_PRODUCT_INTEL_82855PM_AGP: 153 case PCI_PRODUCT_INTEL_82845_AGP: 154 isc->chiptype = CHIP_I845; 155 break; 156 case PCI_PRODUCT_INTEL_82850_AGP: 157 isc->chiptype = CHIP_I850; 158 break; 159 case PCI_PRODUCT_INTEL_82865_AGP: 160 case PCI_PRODUCT_INTEL_82875P_AGP: 161 isc->chiptype = CHIP_I865; 162 break; 163 } 164 165 /* Determine maximum supported aperture size. */ 166 value = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE); 167 pci_conf_write(sc->as_pc, sc->as_tag, 168 AGP_INTEL_APSIZE, APSIZE_MASK); 169 isc->aperture_mask = pci_conf_read(sc->as_pc, sc->as_tag, 170 AGP_INTEL_APSIZE) & APSIZE_MASK; 171 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE, value); 172 isc->initial_aperture = AGP_GET_APERTURE(sc); 173 174 for (;;) { 175 gatt = agp_alloc_gatt(sc); 176 if (gatt) 177 break; 178 179 /* 180 * Probably contigmalloc failure. Try reducing the 181 * aperture so that the gatt size reduces. 182 */ 183 if (AGP_SET_APERTURE(sc, AGP_GET_APERTURE(sc) / 2)) { 184 agp_generic_detach(sc); 185 aprint_error(": failed to set aperture\n"); 186 return ENOMEM; 187 } 188 } 189 isc->gatt = gatt; 190 191 if (!pmf_device_register(self, NULL, agp_intel_resume)) 192 aprint_error_dev(self, "couldn't establish power handler\n"); 193 194 return agp_intel_init(sc); 195 } 196 197 static int 198 agp_intel_init(struct agp_softc *sc) 199 { 200 struct agp_intel_softc *isc = sc->as_chipc; 201 struct agp_gatt *gatt = isc->gatt; 202 pcireg_t reg; 203 204 /* Install the gatt. */ 205 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 206 gatt->ag_physical); 207 208 /* Enable the GLTB and setup the control register. */ 209 switch (isc->chiptype) { 210 case CHIP_I443: 211 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 212 AGPCTRL_AGPRSE | AGPCTRL_GTLB); 213 214 default: 215 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 216 pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL) 217 | AGPCTRL_GTLB); 218 } 219 220 /* Enable things, clear errors etc. */ 221 switch (isc->chiptype) { 222 case CHIP_I845: 223 case CHIP_I865: 224 { 225 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG); 226 reg |= MCHCFG_AAGN; 227 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG, reg); 228 break; 229 } 230 case CHIP_I840: 231 case CHIP_I850: 232 { 233 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD); 234 reg |= AGPCMD_AGPEN; 235 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD, 236 reg); 237 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG); 238 reg |= MCHCFG_AAGN; 239 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG, 240 reg); 241 break; 242 } 243 default: 244 { 245 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 246 reg &= ~NBXCFG_APAE; 247 reg |= NBXCFG_AAGN; 248 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 249 } 250 } 251 252 /* Clear Error status */ 253 switch (isc->chiptype) { 254 case CHIP_I840: 255 pci_conf_write(sc->as_pc, sc->as_tag, 256 AGP_INTEL_I8XX_ERRSTS, 0xc000); 257 break; 258 259 case CHIP_I845: 260 case CHIP_I850: 261 case CHIP_I865: 262 pci_conf_write(sc->as_pc, sc->as_tag, 263 AGP_INTEL_I8XX_ERRSTS, 0x00ff); 264 break; 265 266 default: 267 pci_conf_write(sc->as_pc, sc->as_tag, 268 AGP_INTEL_ERRSTS, 0x70); 269 } 270 271 return (0); 272 } 273 274 #if 0 275 static int 276 agp_intel_detach(struct agp_softc *sc) 277 { 278 int error; 279 pcireg_t reg; 280 struct agp_intel_softc *isc = sc->as_chipc; 281 282 error = agp_generic_detach(sc); 283 if (error) 284 return error; 285 286 /* XXX i845/i855PM/i840/i850E */ 287 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 288 reg &= ~(1 << 9); 289 printf("%s: set NBXCFG to %x\n", __FUNCTION__, reg); 290 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 291 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 0); 292 AGP_SET_APERTURE(sc, isc->initial_aperture); 293 agp_free_gatt(sc, isc->gatt); 294 295 return 0; 296 } 297 #endif 298 299 static u_int32_t 300 agp_intel_get_aperture(struct agp_softc *sc) 301 { 302 struct agp_intel_softc *isc = sc->as_chipc; 303 u_int32_t apsize; 304 305 apsize = pci_conf_read(sc->as_pc, sc->as_tag, 306 AGP_INTEL_APSIZE) & isc->aperture_mask; 307 308 /* 309 * The size is determined by the number of low bits of 310 * register APBASE which are forced to zero. The low 22 bits 311 * are always forced to zero and each zero bit in the apsize 312 * field just read forces the corresponding bit in the 27:22 313 * to be zero. We calculate the aperture size accordingly. 314 */ 315 return (((apsize ^ isc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1; 316 } 317 318 static int 319 agp_intel_set_aperture(struct agp_softc *sc, u_int32_t aperture) 320 { 321 struct agp_intel_softc *isc = sc->as_chipc; 322 u_int32_t apsize; 323 324 /* 325 * Reverse the magic from get_aperture. 326 */ 327 apsize = ((aperture - 1) >> 22) ^ isc->aperture_mask; 328 329 /* 330 * Double check for sanity. 331 */ 332 if ((((apsize ^ isc->aperture_mask) << 22) | 333 ((1 << 22) - 1)) + 1 != aperture) 334 return EINVAL; 335 336 pci_conf_write(sc->as_pc, sc->as_tag, 337 AGP_INTEL_APSIZE, apsize); 338 339 return 0; 340 } 341 342 static int 343 agp_intel_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 344 { 345 struct agp_intel_softc *isc = sc->as_chipc; 346 347 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 348 return EINVAL; 349 350 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 351 return 0; 352 } 353 354 static int 355 agp_intel_unbind_page(struct agp_softc *sc, off_t offset) 356 { 357 struct agp_intel_softc *isc = sc->as_chipc; 358 359 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 360 return EINVAL; 361 362 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 363 return 0; 364 } 365 366 static void 367 agp_intel_flush_tlb(struct agp_softc *sc) 368 { 369 struct agp_intel_softc *isc = sc->as_chipc; 370 pcireg_t reg; 371 372 switch (isc->chiptype) { 373 case CHIP_I865: 374 case CHIP_I850: 375 case CHIP_I845: 376 case CHIP_I840: 377 case CHIP_I443: 378 { 379 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL); 380 reg &= ~AGPCTRL_GTLB; 381 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 382 reg); 383 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 384 reg | AGPCTRL_GTLB); 385 break; 386 } 387 default: /* XXX */ 388 { 389 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 390 0x2200); 391 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 392 0x2280); 393 } 394 } 395 } 396 397 static bool 398 agp_intel_resume(device_t dv) 399 { 400 struct agp_softc *sc = device_private(dv); 401 402 agp_intel_init(sc); 403 agp_flush_cache(); 404 405 return true; 406 } 407
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