agp_intel.c revision 1.35
1 /* $NetBSD: agp_intel.c,v 1.35 2010/04/04 14:40:05 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/pci/agp_intel.c,v 1.4 2001/07/05 21:28:47 jhb Exp $ 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: agp_intel.c,v 1.35 2010/04/04 14:40:05 jakllsch Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/kernel.h> 38 #include <sys/proc.h> 39 #include <sys/agpio.h> 40 #include <sys/device.h> 41 42 #include <uvm/uvm_extern.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcidevs.h> 47 #include <dev/pci/agpvar.h> 48 #include <dev/pci/agpreg.h> 49 50 #include <sys/bus.h> 51 52 struct agp_intel_softc { 53 u_int32_t initial_aperture; 54 /* aperture size at startup */ 55 struct agp_gatt *gatt; 56 struct pci_attach_args vga_pa; 57 u_int aperture_mask; 58 int chiptype; /* Chip type */ 59 #define CHIP_INTEL 0x0 60 #define CHIP_I443 0x1 61 #define CHIP_I840 0x2 62 #define CHIP_I845 0x3 63 #define CHIP_I850 0x4 64 #define CHIP_I865 0x5 65 66 }; 67 68 static u_int32_t agp_intel_get_aperture(struct agp_softc *); 69 static int agp_intel_set_aperture(struct agp_softc *, u_int32_t); 70 static int agp_intel_bind_page(struct agp_softc *, off_t, bus_addr_t); 71 static int agp_intel_unbind_page(struct agp_softc *, off_t); 72 static void agp_intel_flush_tlb(struct agp_softc *); 73 static int agp_intel_init(struct agp_softc *); 74 static bool agp_intel_resume(device_t, const pmf_qual_t *); 75 76 static struct agp_methods agp_intel_methods = { 77 agp_intel_get_aperture, 78 agp_intel_set_aperture, 79 agp_intel_bind_page, 80 agp_intel_unbind_page, 81 agp_intel_flush_tlb, 82 agp_generic_enable, 83 agp_generic_alloc_memory, 84 agp_generic_free_memory, 85 agp_generic_bind_memory, 86 agp_generic_unbind_memory, 87 }; 88 89 static int 90 agp_intel_vgamatch(struct pci_attach_args *pa) 91 { 92 switch (PCI_PRODUCT(pa->pa_id)) { 93 case PCI_PRODUCT_INTEL_82855GM_AGP: 94 case PCI_PRODUCT_INTEL_82855PM_AGP: 95 case PCI_PRODUCT_INTEL_82443LX_AGP: 96 case PCI_PRODUCT_INTEL_82443BX_AGP: 97 case PCI_PRODUCT_INTEL_82443GX_AGP: 98 case PCI_PRODUCT_INTEL_82850_AGP: /* i850/i860 */ 99 case PCI_PRODUCT_INTEL_82845_AGP: 100 case PCI_PRODUCT_INTEL_82840_AGP: 101 case PCI_PRODUCT_INTEL_82865_AGP: 102 case PCI_PRODUCT_INTEL_82875P_AGP: 103 return (1); 104 } 105 106 return (0); 107 } 108 109 int 110 agp_intel_attach(device_t parent, device_t self, void *aux) 111 { 112 struct agp_softc *sc = device_private(self); 113 struct pci_attach_args *pa = aux; 114 struct agp_intel_softc *isc; 115 struct agp_gatt *gatt; 116 u_int32_t value; 117 118 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 119 if (isc == NULL) { 120 aprint_error(": can't allocate chipset-specific softc\n"); 121 return ENOMEM; 122 } 123 124 sc->as_methods = &agp_intel_methods; 125 sc->as_chipc = isc; 126 127 if (pci_find_device(&isc->vga_pa, agp_intel_vgamatch) == 0) { 128 aprint_normal(": using generic initialization for Intel AGP\n"); 129 aprint_normal_dev(sc->as_dev, ""); 130 isc->chiptype = CHIP_INTEL; 131 } 132 133 pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, &sc->as_capoff, 134 NULL); 135 136 if (agp_map_aperture(pa, sc, AGP_APBASE) != 0) { 137 aprint_error(": can't map aperture\n"); 138 free(isc, M_AGP); 139 sc->as_chipc = NULL; 140 return ENXIO; 141 } 142 143 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 144 case PCI_PRODUCT_INTEL_82443LX_AGP: 145 case PCI_PRODUCT_INTEL_82443BX_AGP: 146 case PCI_PRODUCT_INTEL_82443GX_AGP: 147 isc->chiptype = CHIP_I443; 148 break; 149 case PCI_PRODUCT_INTEL_82840_AGP: 150 isc->chiptype = CHIP_I840; 151 break; 152 case PCI_PRODUCT_INTEL_82855GM_AGP: 153 case PCI_PRODUCT_INTEL_82855PM_AGP: 154 case PCI_PRODUCT_INTEL_82845_AGP: 155 isc->chiptype = CHIP_I845; 156 break; 157 case PCI_PRODUCT_INTEL_82850_AGP: 158 isc->chiptype = CHIP_I850; 159 break; 160 case PCI_PRODUCT_INTEL_82865_AGP: 161 case PCI_PRODUCT_INTEL_82875P_AGP: 162 isc->chiptype = CHIP_I865; 163 break; 164 } 165 166 /* Determine maximum supported aperture size. */ 167 value = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE); 168 pci_conf_write(sc->as_pc, sc->as_tag, 169 AGP_INTEL_APSIZE, APSIZE_MASK); 170 isc->aperture_mask = pci_conf_read(sc->as_pc, sc->as_tag, 171 AGP_INTEL_APSIZE) & APSIZE_MASK; 172 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE, value); 173 isc->initial_aperture = AGP_GET_APERTURE(sc); 174 175 for (;;) { 176 gatt = agp_alloc_gatt(sc); 177 if (gatt) 178 break; 179 180 /* 181 * Probably contigmalloc failure. Try reducing the 182 * aperture so that the gatt size reduces. 183 */ 184 if (AGP_SET_APERTURE(sc, AGP_GET_APERTURE(sc) / 2)) { 185 agp_generic_detach(sc); 186 aprint_error(": failed to set aperture\n"); 187 return ENOMEM; 188 } 189 } 190 isc->gatt = gatt; 191 192 if (!pmf_device_register(self, NULL, agp_intel_resume)) 193 aprint_error_dev(self, "couldn't establish power handler\n"); 194 195 return agp_intel_init(sc); 196 } 197 198 static int 199 agp_intel_init(struct agp_softc *sc) 200 { 201 struct agp_intel_softc *isc = sc->as_chipc; 202 struct agp_gatt *gatt = isc->gatt; 203 pcireg_t reg; 204 205 /* Install the gatt. */ 206 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 207 gatt->ag_physical); 208 209 /* Enable the GLTB and setup the control register. */ 210 switch (isc->chiptype) { 211 case CHIP_I443: 212 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 213 AGPCTRL_AGPRSE | AGPCTRL_GTLB); 214 215 default: 216 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 217 pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL) 218 | AGPCTRL_GTLB); 219 } 220 221 /* Enable things, clear errors etc. */ 222 switch (isc->chiptype) { 223 case CHIP_I845: 224 case CHIP_I865: 225 { 226 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG); 227 reg |= MCHCFG_AAGN; 228 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG, reg); 229 break; 230 } 231 case CHIP_I840: 232 case CHIP_I850: 233 { 234 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD); 235 reg |= AGPCMD_AGPEN; 236 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD, 237 reg); 238 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG); 239 reg |= MCHCFG_AAGN; 240 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG, 241 reg); 242 break; 243 } 244 default: 245 { 246 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 247 reg &= ~NBXCFG_APAE; 248 reg |= NBXCFG_AAGN; 249 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 250 } 251 } 252 253 /* Clear Error status */ 254 switch (isc->chiptype) { 255 case CHIP_I840: 256 pci_conf_write(sc->as_pc, sc->as_tag, 257 AGP_INTEL_I8XX_ERRSTS, 0xc000); 258 break; 259 260 case CHIP_I845: 261 case CHIP_I850: 262 case CHIP_I865: 263 pci_conf_write(sc->as_pc, sc->as_tag, 264 AGP_INTEL_I8XX_ERRSTS, 0x00ff); 265 break; 266 267 default: 268 { 269 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_ERRSTS); 270 /* clear error bits (write-one-to-clear) - just write back */ 271 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ERRSTS, reg); 272 } 273 } 274 275 return (0); 276 } 277 278 #if 0 279 static int 280 agp_intel_detach(struct agp_softc *sc) 281 { 282 int error; 283 pcireg_t reg; 284 struct agp_intel_softc *isc = sc->as_chipc; 285 286 error = agp_generic_detach(sc); 287 if (error) 288 return error; 289 290 /* XXX i845/i855PM/i840/i850E */ 291 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 292 reg &= ~(1 << 9); 293 printf("%s: set NBXCFG to %x\n", __func__, reg); 294 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 295 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 0); 296 AGP_SET_APERTURE(sc, isc->initial_aperture); 297 agp_free_gatt(sc, isc->gatt); 298 299 return 0; 300 } 301 #endif 302 303 static u_int32_t 304 agp_intel_get_aperture(struct agp_softc *sc) 305 { 306 struct agp_intel_softc *isc = sc->as_chipc; 307 u_int32_t apsize; 308 309 apsize = pci_conf_read(sc->as_pc, sc->as_tag, 310 AGP_INTEL_APSIZE) & isc->aperture_mask; 311 312 /* 313 * The size is determined by the number of low bits of 314 * register APBASE which are forced to zero. The low 22 bits 315 * are always forced to zero and each zero bit in the apsize 316 * field just read forces the corresponding bit in the 27:22 317 * to be zero. We calculate the aperture size accordingly. 318 */ 319 return (((apsize ^ isc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1; 320 } 321 322 static int 323 agp_intel_set_aperture(struct agp_softc *sc, u_int32_t aperture) 324 { 325 struct agp_intel_softc *isc = sc->as_chipc; 326 u_int32_t apsize; 327 328 /* 329 * Reverse the magic from get_aperture. 330 */ 331 apsize = ((aperture - 1) >> 22) ^ isc->aperture_mask; 332 333 /* 334 * Double check for sanity. 335 */ 336 if ((((apsize ^ isc->aperture_mask) << 22) | 337 ((1 << 22) - 1)) + 1 != aperture) 338 return EINVAL; 339 340 pci_conf_write(sc->as_pc, sc->as_tag, 341 AGP_INTEL_APSIZE, apsize); 342 343 return 0; 344 } 345 346 static int 347 agp_intel_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 348 { 349 struct agp_intel_softc *isc = sc->as_chipc; 350 351 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 352 return EINVAL; 353 354 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 355 return 0; 356 } 357 358 static int 359 agp_intel_unbind_page(struct agp_softc *sc, off_t offset) 360 { 361 struct agp_intel_softc *isc = sc->as_chipc; 362 363 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 364 return EINVAL; 365 366 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 367 return 0; 368 } 369 370 static void 371 agp_intel_flush_tlb(struct agp_softc *sc) 372 { 373 struct agp_intel_softc *isc = sc->as_chipc; 374 pcireg_t reg; 375 376 switch (isc->chiptype) { 377 case CHIP_I865: 378 case CHIP_I850: 379 case CHIP_I845: 380 case CHIP_I840: 381 case CHIP_I443: 382 { 383 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL); 384 reg &= ~AGPCTRL_GTLB; 385 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 386 reg); 387 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 388 reg | AGPCTRL_GTLB); 389 break; 390 } 391 default: /* XXX */ 392 { 393 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 394 0x2200); 395 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 396 0x2280); 397 } 398 } 399 } 400 401 static bool 402 agp_intel_resume(device_t dv, const pmf_qual_t *qual) 403 { 404 struct agp_softc *sc = device_private(dv); 405 406 agp_intel_init(sc); 407 agp_flush_cache(); 408 409 return true; 410 } 411
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