agp_intel.c revision 1.7
1 /* $NetBSD: agp_intel.c,v 1.7 2003/06/09 12:16:42 ichiro Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/pci/agp_intel.c,v 1.4 2001/07/05 21:28:47 jhb Exp $ 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: agp_intel.c,v 1.7 2003/06/09 12:16:42 ichiro Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/proc.h> 40 #include <sys/agpio.h> 41 #include <sys/device.h> 42 #include <sys/agpio.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcidevs.h> 49 #include <dev/pci/agpvar.h> 50 #include <dev/pci/agpreg.h> 51 52 #include <machine/bus.h> 53 54 struct agp_intel_softc { 55 u_int32_t initial_aperture; 56 /* aperture size at startup */ 57 struct agp_gatt *gatt; 58 struct pci_attach_args vga_pa; /* child device */ 59 int chiptype; 60 #define CHIP_I845 0x0 61 #define CHIP_I840 0x1 62 #define CHIP_I443 0x2 63 /* Chip type */ 64 }; 65 66 static u_int32_t agp_intel_get_aperture(struct agp_softc *); 67 static int agp_intel_set_aperture(struct agp_softc *, u_int32_t); 68 static int agp_intel_bind_page(struct agp_softc *, off_t, bus_addr_t); 69 static int agp_intel_unbind_page(struct agp_softc *, off_t); 70 static void agp_intel_flush_tlb(struct agp_softc *); 71 72 struct agp_methods agp_intel_methods = { 73 agp_intel_get_aperture, 74 agp_intel_set_aperture, 75 agp_intel_bind_page, 76 agp_intel_unbind_page, 77 agp_intel_flush_tlb, 78 agp_generic_enable, 79 agp_generic_alloc_memory, 80 agp_generic_free_memory, 81 agp_generic_bind_memory, 82 agp_generic_unbind_memory, 83 }; 84 85 static int 86 agp_intel_vgamatch(struct pci_attach_args *pa) 87 { 88 switch (PCI_PRODUCT(pa->pa_id)) { 89 case PCI_PRODUCT_INTEL_82855PM_AGP: 90 case PCI_PRODUCT_INTEL_82443LX_AGP: 91 case PCI_PRODUCT_INTEL_82443BX_AGP: 92 case PCI_PRODUCT_INTEL_82443GX_AGP: 93 case PCI_PRODUCT_INTEL_82850_AGP: 94 case PCI_PRODUCT_INTEL_82845_AGP: 95 case PCI_PRODUCT_INTEL_82840_AGP: 96 return (1); 97 } 98 99 return (0); 100 } 101 102 int 103 agp_intel_attach(struct device *parent, struct device *self, void *aux) 104 { 105 struct agp_softc *sc = (struct agp_softc *)self; 106 struct pci_attach_args *pa= aux; 107 struct agp_intel_softc *isc; 108 struct agp_gatt *gatt; 109 pcireg_t reg; 110 111 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 112 if (isc == NULL) { 113 aprint_error(": can't allocate chipset-specific softc\n"); 114 return ENOMEM; 115 } 116 117 sc->as_methods = &agp_intel_methods; 118 sc->as_chipc = isc; 119 120 if (pci_find_device(&isc->vga_pa, agp_intel_vgamatch) == 0) { 121 aprint_error(": can't find internal VGA device config space\n"); 122 free(isc, M_AGP); 123 return ENOENT; 124 } 125 126 pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, &sc->as_capoff, 127 NULL); 128 129 if (agp_map_aperture(pa, sc) != 0) { 130 aprint_error(": can't map aperture\n"); 131 free(isc, M_AGP); 132 sc->as_chipc = NULL; 133 return ENXIO; 134 } 135 136 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 137 case PCI_PRODUCT_INTEL_82855PM_AGP: 138 case PCI_PRODUCT_INTEL_82845_AGP: 139 isc->chiptype = CHIP_I845; 140 break; 141 case PCI_PRODUCT_INTEL_82840_AGP: 142 case PCI_PRODUCT_INTEL_82850_AGP: 143 isc->chiptype = CHIP_I840; 144 break; 145 case PCI_PRODUCT_INTEL_82443LX_AGP: 146 case PCI_PRODUCT_INTEL_82443BX_AGP: 147 case PCI_PRODUCT_INTEL_82443GX_AGP: 148 isc->chiptype = CHIP_I443; 149 break; 150 } 151 152 isc->initial_aperture = AGP_GET_APERTURE(sc); 153 154 for (;;) { 155 gatt = agp_alloc_gatt(sc); 156 if (gatt) 157 break; 158 159 /* 160 * Probably contigmalloc failure. Try reducing the 161 * aperture so that the gatt size reduces. 162 */ 163 if (AGP_SET_APERTURE(sc, AGP_GET_APERTURE(sc) / 2)) { 164 agp_generic_detach(sc); 165 aprint_error(": failed to set aperture\n"); 166 return ENOMEM; 167 } 168 } 169 isc->gatt = gatt; 170 171 /* Install the gatt. */ 172 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 173 gatt->ag_physical); 174 175 /* Enable things, clear errors etc. */ 176 switch (isc->chiptype) { 177 case CHIP_I845: 178 { 179 pci_conf_write(sc->as_pc, sc->as_tag, 180 AGP_INTEL_AGPCTRL, AGPCTRL_GTLB); 181 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD, 182 AGPCMD_SBA | AGPCMD_AGPEN | AGPCMD_RATE_4X); 183 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I845_AGPMISC, AGPMISC_AAGN); 184 break; 185 } 186 case CHIP_I840: 187 { 188 pci_conf_write(sc->as_pc, sc->as_tag, 189 AGP_INTEL_AGPCTRL, AGPCTRL_GTLB); 190 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD, 191 AGPCMD_SBA | AGPCMD_AGPEN | AGPCMD_RATE_4X); 192 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG, MCHCFG_AAGN); 193 break; 194 } 195 case CHIP_I443: 196 { 197 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 198 AGPCTRL_AGPRSE | AGPCTRL_GTLB); 199 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 200 reg &= ~NBXCFG_APAE; 201 reg |= NBXCFG_AAGN; 202 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 203 204 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_STS); 205 reg &= ~0x00ff0000; 206 reg |= (7 << 16); /* XXX */ 207 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_STS, reg); 208 209 break; 210 } 211 } 212 213 return 0; 214 } 215 216 #if 0 217 static int 218 agp_intel_detach(struct agp_softc *sc) 219 { 220 int error; 221 pcireg_t reg; 222 struct agp_intel_softc *isc = sc->as_chipc; 223 224 error = agp_generic_detach(sc); 225 if (error) 226 return error; 227 228 /* XXX i845/i855PM/i840/i850E */ 229 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 230 reg &= ~(1 << 9); 231 printf("%s: set NBXCFG to %x\n", __FUNCTION__, reg); 232 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 233 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 0); 234 AGP_SET_APERTURE(sc, isc->initial_aperture); 235 agp_free_gatt(sc, isc->gatt); 236 237 return 0; 238 } 239 #endif 240 241 static u_int32_t 242 agp_intel_get_aperture(struct agp_softc *sc) 243 { 244 u_int32_t apsize; 245 246 apsize = pci_conf_read(sc->as_pc, sc->as_tag, 247 AGP_INTEL_APSIZE) & APSIZE_MASK; 248 249 /* 250 * The size is determined by the number of low bits of 251 * register APBASE which are forced to zero. The low 22 bits 252 * are always forced to zero and each zero bit in the apsize 253 * field just read forces the corresponding bit in the 27:22 254 * to be zero. We calculate the aperture size accordingly. 255 */ 256 return (((apsize ^ APSIZE_MASK) << 22) | ((1 << 22) - 1)) + 1; 257 } 258 259 static int 260 agp_intel_set_aperture(struct agp_softc *sc, u_int32_t aperture) 261 { 262 u_int32_t apsize; 263 pcireg_t reg; 264 265 /* 266 * Reverse the magic from get_aperture. 267 */ 268 apsize = ((aperture - 1) >> 22) ^ APSIZE_MASK; 269 270 /* 271 * Double check for sanity. 272 */ 273 if ((((apsize ^ APSIZE_MASK) << 22) | 274 ((1 << 22) - 1)) + 1 != aperture) 275 return EINVAL; 276 277 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE); 278 reg = (reg & 0xffffff00) | apsize; 279 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE, reg); 280 281 return 0; 282 } 283 284 static int 285 agp_intel_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 286 { 287 struct agp_intel_softc *isc = sc->as_chipc; 288 289 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 290 return EINVAL; 291 292 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 293 return 0; 294 } 295 296 static int 297 agp_intel_unbind_page(struct agp_softc *sc, off_t offset) 298 { 299 struct agp_intel_softc *isc = sc->as_chipc; 300 301 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 302 return EINVAL; 303 304 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 305 return 0; 306 } 307 308 static void 309 agp_intel_flush_tlb(struct agp_softc *sc) 310 { 311 struct agp_intel_softc *isc = sc->as_chipc; 312 313 switch (isc->chiptype) { 314 case CHIP_I845: 315 case CHIP_I840: 316 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 317 0x0); 318 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 319 AGPCTRL_GTLB); 320 break; 321 case CHIP_I443: 322 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 323 AGPCTRL_AGPRSE); 324 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 325 AGPCTRL_AGPRSE | AGPCTRL_GTLB); 326 break; 327 } 328 } 329
Indexes created Thu Oct 02 01:09:59 GMT 2025