agp_intel.c revision 1.9
1 /* $NetBSD: agp_intel.c,v 1.9 2003/06/14 11:44:51 ichiro Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/pci/agp_intel.c,v 1.4 2001/07/05 21:28:47 jhb Exp $ 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: agp_intel.c,v 1.9 2003/06/14 11:44:51 ichiro Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/proc.h> 40 #include <sys/agpio.h> 41 #include <sys/device.h> 42 #include <sys/agpio.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcidevs.h> 49 #include <dev/pci/agpvar.h> 50 #include <dev/pci/agpreg.h> 51 52 #include <machine/bus.h> 53 54 struct agp_intel_softc { 55 u_int32_t initial_aperture; 56 /* aperture size at startup */ 57 struct agp_gatt *gatt; 58 struct pci_attach_args vga_pa; /* child device */ 59 int chiptype; 60 #define CHIP_INTEL 0x0 61 #define CHIP_I443 0x1 62 #define CHIP_I840 0x2 63 #define CHIP_I845 0x3 64 #define CHIP_I850 0x4 65 /* Chip type */ 66 }; 67 68 static u_int32_t agp_intel_get_aperture(struct agp_softc *); 69 static int agp_intel_set_aperture(struct agp_softc *, u_int32_t); 70 static int agp_intel_bind_page(struct agp_softc *, off_t, bus_addr_t); 71 static int agp_intel_unbind_page(struct agp_softc *, off_t); 72 static void agp_intel_flush_tlb(struct agp_softc *); 73 74 struct agp_methods agp_intel_methods = { 75 agp_intel_get_aperture, 76 agp_intel_set_aperture, 77 agp_intel_bind_page, 78 agp_intel_unbind_page, 79 agp_intel_flush_tlb, 80 agp_generic_enable, 81 agp_generic_alloc_memory, 82 agp_generic_free_memory, 83 agp_generic_bind_memory, 84 agp_generic_unbind_memory, 85 }; 86 87 static int 88 agp_intel_vgamatch(struct pci_attach_args *pa) 89 { 90 switch (PCI_PRODUCT(pa->pa_id)) { 91 case PCI_PRODUCT_INTEL_82855PM_AGP: 92 case PCI_PRODUCT_INTEL_82443LX_AGP: 93 case PCI_PRODUCT_INTEL_82443BX_AGP: 94 case PCI_PRODUCT_INTEL_82443GX_AGP: 95 case PCI_PRODUCT_INTEL_82850_AGP: 96 case PCI_PRODUCT_INTEL_82845_AGP: 97 case PCI_PRODUCT_INTEL_82840_AGP: 98 return (1); 99 } 100 101 return (0); 102 } 103 104 int 105 agp_intel_attach(struct device *parent, struct device *self, void *aux) 106 { 107 struct agp_softc *sc = (struct agp_softc *)self; 108 struct pci_attach_args *pa= aux; 109 struct agp_intel_softc *isc; 110 struct agp_gatt *gatt; 111 pcireg_t reg; 112 113 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 114 if (isc == NULL) { 115 aprint_error(": can't allocate chipset-specific softc\n"); 116 return ENOMEM; 117 } 118 119 sc->as_methods = &agp_intel_methods; 120 sc->as_chipc = isc; 121 122 if (pci_find_device(&isc->vga_pa, agp_intel_vgamatch) == 0) { 123 aprint_error(": can't find internal VGA device config space\n"); 124 free(isc, M_AGP); 125 return ENOENT; 126 } 127 128 pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, &sc->as_capoff, 129 NULL); 130 131 if (agp_map_aperture(pa, sc) != 0) { 132 aprint_error(": can't map aperture\n"); 133 free(isc, M_AGP); 134 sc->as_chipc = NULL; 135 return ENXIO; 136 } 137 138 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 139 case PCI_PRODUCT_INTEL_82855PM_AGP: 140 case PCI_PRODUCT_INTEL_82845_AGP: 141 isc->chiptype = CHIP_I845; 142 break; 143 case PCI_PRODUCT_INTEL_82840_AGP: 144 isc->chiptype = CHIP_I840; 145 break; 146 case PCI_PRODUCT_INTEL_82850_AGP: 147 isc->chiptype = CHIP_I850; 148 break; 149 case PCI_PRODUCT_INTEL_82443LX_AGP: 150 case PCI_PRODUCT_INTEL_82443BX_AGP: 151 case PCI_PRODUCT_INTEL_82443GX_AGP: 152 isc->chiptype = CHIP_I443; 153 break; 154 default: 155 isc->chiptype = CHIP_INTEL; 156 } 157 158 isc->initial_aperture = AGP_GET_APERTURE(sc); 159 160 for (;;) { 161 gatt = agp_alloc_gatt(sc); 162 if (gatt) 163 break; 164 165 /* 166 * Probably contigmalloc failure. Try reducing the 167 * aperture so that the gatt size reduces. 168 */ 169 if (AGP_SET_APERTURE(sc, AGP_GET_APERTURE(sc) / 2)) { 170 agp_generic_detach(sc); 171 aprint_error(": failed to set aperture\n"); 172 return ENOMEM; 173 } 174 } 175 isc->gatt = gatt; 176 177 /* Install the gatt. */ 178 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 179 gatt->ag_physical); 180 181 /* Enable the GLTB and setup the control register. */ 182 switch (isc->chiptype) { 183 case CHIP_I443: 184 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 185 AGPCTRL_AGPRSE | AGPCTRL_GTLB); 186 187 default: 188 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 189 pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL) 190 | AGPCTRL_GTLB); 191 } 192 193 /* Enable things, clear errors etc. */ 194 switch (isc->chiptype) { 195 case CHIP_I845: 196 { 197 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD, 198 AGPCMD_SBA | AGPCMD_AGPEN | AGPCMD_RATE_4X); 199 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I845_AGPMISC, AGPMISC_AAGN); 200 break; 201 } 202 case CHIP_I840: 203 case CHIP_I850: 204 { 205 #if XXX 206 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD, 207 AGPCMD_SBA | AGPCMD_AGPEN | AGPCMD_RATE_4X); 208 #endif 209 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG, 210 MCHCFG_AAGN); 211 break; 212 } 213 default: 214 { 215 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 216 reg &= ~NBXCFG_APAE; 217 reg |= NBXCFG_AAGN; 218 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 219 } 220 } 221 222 /* Clear Error status */ 223 switch (isc->chiptype) { 224 case CHIP_I840: 225 pci_conf_write(sc->as_pc, sc->as_tag, 226 AGP_INTEL_I8XX_ERRSTS, 0xc000); 227 break; 228 229 case CHIP_I845: 230 case CHIP_I850: 231 pci_conf_write(sc->as_pc, sc->as_tag, 232 AGP_INTEL_I8XX_ERRSTS, 0x00ff); 233 break; 234 235 default: 236 pci_conf_write(sc->as_pc, sc->as_tag, 237 AGP_INTEL_ERRSTS, 0x70); 238 } 239 240 return 0; 241 } 242 243 #if 0 244 static int 245 agp_intel_detach(struct agp_softc *sc) 246 { 247 int error; 248 pcireg_t reg; 249 struct agp_intel_softc *isc = sc->as_chipc; 250 251 error = agp_generic_detach(sc); 252 if (error) 253 return error; 254 255 /* XXX i845/i855PM/i840/i850E */ 256 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 257 reg &= ~(1 << 9); 258 printf("%s: set NBXCFG to %x\n", __FUNCTION__, reg); 259 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 260 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 0); 261 AGP_SET_APERTURE(sc, isc->initial_aperture); 262 agp_free_gatt(sc, isc->gatt); 263 264 return 0; 265 } 266 #endif 267 268 static u_int32_t 269 agp_intel_get_aperture(struct agp_softc *sc) 270 { 271 u_int32_t apsize; 272 273 apsize = pci_conf_read(sc->as_pc, sc->as_tag, 274 AGP_INTEL_APSIZE) & APSIZE_MASK; 275 276 /* 277 * The size is determined by the number of low bits of 278 * register APBASE which are forced to zero. The low 22 bits 279 * are always forced to zero and each zero bit in the apsize 280 * field just read forces the corresponding bit in the 27:22 281 * to be zero. We calculate the aperture size accordingly. 282 */ 283 return (((apsize ^ APSIZE_MASK) << 22) | ((1 << 22) - 1)) + 1; 284 } 285 286 static int 287 agp_intel_set_aperture(struct agp_softc *sc, u_int32_t aperture) 288 { 289 u_int32_t apsize; 290 pcireg_t reg; 291 292 /* 293 * Reverse the magic from get_aperture. 294 */ 295 apsize = ((aperture - 1) >> 22) ^ APSIZE_MASK; 296 297 /* 298 * Double check for sanity. 299 */ 300 if ((((apsize ^ APSIZE_MASK) << 22) | 301 ((1 << 22) - 1)) + 1 != aperture) 302 return EINVAL; 303 304 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE); 305 reg = (reg & 0xffffff00) | apsize; 306 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE, reg); 307 308 return 0; 309 } 310 311 static int 312 agp_intel_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 313 { 314 struct agp_intel_softc *isc = sc->as_chipc; 315 316 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 317 return EINVAL; 318 319 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 320 return 0; 321 } 322 323 static int 324 agp_intel_unbind_page(struct agp_softc *sc, off_t offset) 325 { 326 struct agp_intel_softc *isc = sc->as_chipc; 327 328 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 329 return EINVAL; 330 331 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 332 return 0; 333 } 334 335 static void 336 agp_intel_flush_tlb(struct agp_softc *sc) 337 { 338 struct agp_intel_softc *isc = sc->as_chipc; 339 340 switch (isc->chiptype) { 341 case CHIP_I850: 342 case CHIP_I845: 343 case CHIP_I840: 344 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 345 0x0); 346 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 347 AGPCTRL_GTLB); 348 break; 349 case CHIP_I443: 350 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 351 AGPCTRL_AGPRSE); 352 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 353 AGPCTRL_AGPRSE | AGPCTRL_GTLB); 354 break; 355 } 356 } 357
Indexes created Mon Sep 22 21:09:42 GMT 2025