agpreg.h revision 1.1
1 /* $NetBSD: agpreg.h,v 1.1 2001/09/10 10:01:02 fvdl Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/pci/agpreg.h,v 1.3 2000/07/12 10:13:04 dfr Exp $ 29 */ 30 31 #ifndef _PCI_AGPREG_H_ 32 #define _PCI_AGPREG_H_ 33 34 /* 35 * Offsets for various AGP configuration registers. 36 */ 37 #define AGP_APBASE 0x10 38 39 /* 40 * Offsets from the AGP Capability pointer. 41 */ 42 #define AGP_CAPID 0x02 43 #define AGP_CAPID_GET_MAJOR(x) (((x) & 0x00f00000U) >> 20) 44 #define AGP_CAPID_GET_MINOR(x) (((x) & 0x000f0000U) >> 16) 45 #define AGP_CAPID_GET_NEXT_PTR(x) (((x) & 0x0000ff00U) >> 8) 46 #define AGP_CAPID_GET_CAP_ID(x) (((x) & 0x000000ffU) >> 0) 47 48 #define AGP_STATUS 0x4 49 #define AGP_COMMAND 0x8 50 51 /* 52 * Config offsets for Intel AGP chipsets. 53 */ 54 #define AGP_INTEL_NBXCFG 0x50 55 #define AGP_INTEL_STS 0x90 56 #define AGP_INTEL_AGPCTRL 0xb0 57 #define AGP_INTEL_APSIZE 0xb4 58 #define AGP_INTEL_ATTBASE 0xb8 59 60 /* 61 * Config offsets for VIA AGP chipsets. 62 */ 63 #define AGP_VIA_GARTCTRL 0x80 64 #define AGP_VIA_APSIZE 0x84 65 #define AGP_VIA_ATTBASE 0x88 66 67 /* 68 * Config offsets for SiS AGP chipsets. 69 */ 70 #define AGP_SIS_ATTBASE 0x90 71 #define AGP_SIS_WINCTRL 0x94 72 #define AGP_SIS_TLBCTRL 0x97 73 #define AGP_SIS_TLBFLUSH 0x98 74 75 /* 76 * Config offsets for Ali AGP chipsets. 77 */ 78 #define AGP_ALI_AGPCTRL 0xb8 79 #define AGP_ALI_ATTBASE 0xbc 80 #define AGP_ALI_TLBCTRL 0xc0 81 82 /* 83 * Config offsets for the AMD 751 chipset. 84 */ 85 #define AGP_AMD751_REGISTERS 0x14 86 #define AGP_AMD751_APCTRL 0xac 87 #define AGP_AMD751_MODECTRL 0xb0 88 #define AGP_AMD751_MODECTRL_SYNEN 0x80 89 #define AGP_AMD751_MODECTRL2 0xb2 90 #define AGP_AMD751_MODECTRL2_G1LM 0x01 91 #define AGP_AMD751_MODECTRL2_GPDCE 0x02 92 #define AGP_AMD751_MODECTRL2_NGSE 0x08 93 94 /* 95 * Memory mapped register offsets for AMD 751 chipset. 96 */ 97 #define AGP_AMD751_CAPS 0x00 98 #define AGP_AMD751_CAPS_EHI 0x0800 99 #define AGP_AMD751_CAPS_P2P 0x0400 100 #define AGP_AMD751_CAPS_MPC 0x0200 101 #define AGP_AMD751_CAPS_VBE 0x0100 102 #define AGP_AMD751_CAPS_REV 0x00ff 103 #define AGP_AMD751_STATUS 0x02 104 #define AGP_AMD751_STATUS_P2PS 0x0800 105 #define AGP_AMD751_STATUS_GCS 0x0400 106 #define AGP_AMD751_STATUS_MPS 0x0200 107 #define AGP_AMD751_STATUS_VBES 0x0100 108 #define AGP_AMD751_STATUS_P2PE 0x0008 109 #define AGP_AMD751_STATUS_GCE 0x0004 110 #define AGP_AMD751_STATUS_VBEE 0x0001 111 #define AGP_AMD751_ATTBASE 0x04 112 #define AGP_AMD751_TLBCTRL 0x0c 113 114 /* 115 * Config registers for i810 device 0 116 */ 117 #define AGP_I810_SMRAM 0x70 118 #define AGP_I810_SMRAM_GMS 0xc0 119 #define AGP_I810_SMRAM_GMS_DISABLED 0x00 120 #define AGP_I810_SMRAM_GMS_ENABLED_0 0x40 121 #define AGP_I810_SMRAM_GMS_ENABLED_512 0x80 122 #define AGP_I810_SMRAM_GMS_ENABLED_1024 0xc0 123 #define AGP_I810_MISCC 0x72 124 #define AGP_I810_MISCC_WINSIZE 0x0001 125 #define AGP_I810_MISCC_WINSIZE_64 0x0000 126 #define AGP_I810_MISCC_WINSIZE_32 0x0001 127 #define AGP_I810_MISCC_PLCK 0x0008 128 #define AGP_I810_MISCC_PLCK_UNLOCKED 0x0000 129 #define AGP_I810_MISCC_PLCK_LOCKED 0x0008 130 #define AGP_I810_MISCC_WPTC 0x0030 131 #define AGP_I810_MISCC_WPTC_NOLIMIT 0x0000 132 #define AGP_I810_MISCC_WPTC_62 0x0010 133 #define AGP_I810_MISCC_WPTC_50 0x0020 134 #define AGP_I810_MISCC_WPTC_37 0x0030 135 #define AGP_I810_MISCC_RPTC 0x00c0 136 #define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000 137 #define AGP_I810_MISCC_RPTC_62 0x0040 138 #define AGP_I810_MISCC_RPTC_50 0x0080 139 #define AGP_I810_MISCC_RPTC_37 0x00c0 140 141 /* 142 * Config registers for i810 device 1 143 */ 144 #define AGP_I810_GMADR 0x10 145 #define AGP_I810_MMADR 0x14 146 147 /* 148 * Memory mapped register offsets for i810 chipset. 149 */ 150 #define AGP_I810_PGTBL_CTL 0x2020 151 #define AGP_I810_DRT 0x3000 152 #define AGP_I810_DRT_UNPOPULATED 0x00 153 #define AGP_I810_DRT_POPULATED 0x01 154 #define AGP_I810_GTT 0x10000 155 156 #endif /* !_PCI_AGPREG_H_ */ 157
Indexes created Tue Sep 23 07:09:52 GMT 2025