ahc_pci.c revision 1.10
1 /* $NetBSD: ahc_pci.c,v 1.10 1997/03/13 00:38:52 cgd Exp $ */ 2 3 /* 4 * Product specific probe and attach routines for: 5 * 3940, 2940, aic7880, aic7870, aic7860 and aic7850 SCSI controllers 6 * 7 * Copyright (c) 1995, 1996 Justin T. Gibbs. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice immediately at the beginning of the file, without modification, 15 * this list of conditions, and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from Id: aic7870.c,v 1.37 1996/06/08 06:55:55 gibbs Exp 35 */ 36 37 #if defined(__FreeBSD__) 38 #include <pci.h> 39 #endif 40 #if NPCI > 0 || defined(__NetBSD__) 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/queue.h> 46 #if defined(__NetBSD__) 47 #include <sys/device.h> 48 #include <machine/bus.h> 49 #include <machine/intr.h> 50 #endif /* defined(__NetBSD__) */ 51 52 #include <scsi/scsi_all.h> 53 #include <scsi/scsiconf.h> 54 55 #if defined(__FreeBSD__) 56 57 #include <pci/pcireg.h> 58 #include <pci/pcivar.h> 59 60 #include <machine/clock.h> 61 62 #include <i386/scsi/aic7xxx.h> 63 #include <i386/scsi/93cx6.h> 64 65 #include <dev/aic7xxx/aic7xxx_reg.h> 66 67 #define PCI_BASEADR0 PCI_MAP_REG_START 68 69 #elif defined(__NetBSD__) 70 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 74 #include <dev/ic/aic7xxxreg.h> 75 #include <dev/ic/aic7xxxvar.h> 76 #include <dev/ic/smc93cx6var.h> 77 78 /* 79 * Under normal circumstances, these messages are unnecessary 80 * and not terribly cosmetic. 81 */ 82 #ifdef DEBUG 83 #define bootverbose 1 84 #else 85 #define bootverbose 0 86 #endif 87 88 #define PCI_BASEADR0 PCI_MAPREG_START 89 90 #endif /* defined(__NetBSD__) */ 91 92 #define PCI_DEVICE_ID_ADAPTEC_3940U 0x82789004ul 93 #define PCI_DEVICE_ID_ADAPTEC_2944U 0x84789004ul 94 #define PCI_DEVICE_ID_ADAPTEC_2940U 0x81789004ul 95 #define PCI_DEVICE_ID_ADAPTEC_2940AU 0x61789004ul 96 #define PCI_DEVICE_ID_ADAPTEC_3940 0x72789004ul 97 #define PCI_DEVICE_ID_ADAPTEC_2944 0x74789004ul 98 #define PCI_DEVICE_ID_ADAPTEC_2940 0x71789004ul 99 #define PCI_DEVICE_ID_ADAPTEC_AIC7880 0x80789004ul 100 #define PCI_DEVICE_ID_ADAPTEC_AIC7870 0x70789004ul 101 #define PCI_DEVICE_ID_ADAPTEC_AIC7860 0x60789004ul 102 #define PCI_DEVICE_ID_ADAPTEC_AIC7855 0x55789004ul 103 #define PCI_DEVICE_ID_ADAPTEC_AIC7850 0x50789004ul 104 105 #define DEVCONFIG 0x40 106 #define MPORTMODE 0x00000400ul /* aic7870 only */ 107 #define RAMPSM 0x00000200ul /* aic7870 only */ 108 #define VOLSENSE 0x00000100ul 109 #define SCBRAMSEL 0x00000080ul 110 #define MRDCEN 0x00000040ul 111 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 112 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 113 #define BERREN 0x00000008ul 114 #define DACEN 0x00000004ul 115 #define STPWLEVEL 0x00000002ul 116 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 117 118 #define CSIZE_LATTIME 0x0c 119 #define CACHESIZE 0x0000003ful /* only 5 bits */ 120 #define LATTIME 0x0000ff00ul 121 122 /* 123 * Define the format of the aic78X0 SEEPROM registers (16 bits). 124 * 125 */ 126 127 struct seeprom_config { 128 129 /* 130 * SCSI ID Configuration Flags 131 */ 132 #define CFXFER 0x0007 /* synchronous transfer rate */ 133 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 134 #define CFDISC 0x0010 /* enable disconnection */ 135 #define CFWIDEB 0x0020 /* wide bus device */ 136 /* UNUSED 0x00C0 */ 137 #define CFSTART 0x0100 /* send start unit SCSI command */ 138 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 139 #define CFRNFOUND 0x0400 /* report even if not found */ 140 /* UNUSED 0xf800 */ 141 u_int16_t device_flags[16]; /* words 0-15 */ 142 143 /* 144 * BIOS Control Bits 145 */ 146 #define CFSUPREM 0x0001 /* support all removeable drives */ 147 #define CFSUPREMB 0x0002 /* support removeable drives for boot only */ 148 #define CFBIOSEN 0x0004 /* BIOS enabled */ 149 /* UNUSED 0x0008 */ 150 #define CFSM2DRV 0x0010 /* support more than two drives */ 151 /* UNUSED 0x0060 */ 152 #define CFEXTEND 0x0080 /* extended translation enabled */ 153 /* UNUSED 0xff00 */ 154 u_int16_t bios_control; /* word 16 */ 155 156 /* 157 * Host Adapter Control Bits 158 */ 159 /* UNUSED 0x0001 */ 160 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable (Ultra cards) */ 161 #define CFSTERM 0x0004 /* SCSI low byte termination (non-wide cards) */ 162 #define CFWSTERM 0x0008 /* SCSI high byte termination (wide card) */ 163 #define CFSPARITY 0x0010 /* SCSI parity */ 164 /* UNUSED 0x0020 */ 165 #define CFRESETB 0x0040 /* reset SCSI bus at IC initialization */ 166 /* UNUSED 0xff80 */ 167 u_int16_t adapter_control; /* word 17 */ 168 169 /* 170 * Bus Release, Host Adapter ID 171 */ 172 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 173 /* UNUSED 0x00f0 */ 174 #define CFBRTIME 0xff00 /* bus release time */ 175 u_int16_t brtime_id; /* word 18 */ 176 177 /* 178 * Maximum targets 179 */ 180 #define CFMAXTARG 0x00ff /* maximum targets */ 181 /* UNUSED 0xff00 */ 182 u_int16_t max_targets; /* word 19 */ 183 184 u_int16_t res_1[11]; /* words 20-30 */ 185 u_int16_t checksum; /* word 31 */ 186 }; 187 188 static void load_seeprom __P((struct ahc_data *ahc)); 189 static int acquire_seeprom __P((struct seeprom_descriptor *sd)); 190 static void release_seeprom __P((struct seeprom_descriptor *sd)); 191 192 static u_char aic3940_count; 193 194 #if defined(__FreeBSD__) 195 196 static char* aic7870_probe __P((pcici_t tag, pcidi_t type)); 197 static void aic7870_attach __P((pcici_t config_id, int unit)); 198 199 static struct pci_device ahc_pci_driver = { 200 "ahc", 201 aic7870_probe, 202 aic7870_attach, 203 &ahc_unit, 204 NULL 205 }; 206 207 DATA_SET (pcidevice_set, ahc_pci_driver); 208 209 static char* 210 aic7870_probe (pcici_t tag, pcidi_t type) 211 { 212 switch(type) { 213 case PCI_DEVICE_ID_ADAPTEC_3940U: 214 return ("Adaptec 3940 Ultra SCSI host adapter"); 215 break; 216 case PCI_DEVICE_ID_ADAPTEC_3940: 217 return ("Adaptec 3940 SCSI host adapter"); 218 break; 219 case PCI_DEVICE_ID_ADAPTEC_2944U: 220 return ("Adaptec 2944 Ultra SCSI host adapter"); 221 break; 222 case PCI_DEVICE_ID_ADAPTEC_2940U: 223 return ("Adaptec 2940 Ultra SCSI host adapter"); 224 break; 225 case PCI_DEVICE_ID_ADAPTEC_2944: 226 return ("Adaptec 2944 SCSI host adapter"); 227 break; 228 case PCI_DEVICE_ID_ADAPTEC_2940: 229 return ("Adaptec 2940 SCSI host adapter"); 230 break; 231 case PCI_DEVICE_ID_ADAPTEC_2940AU: 232 return ("Adaptec 2940A Ultra SCSI host adapter"); 233 break; 234 case PCI_DEVICE_ID_ADAPTEC_AIC7880: 235 return ("Adaptec aic7880 Ultra SCSI host adapter"); 236 break; 237 case PCI_DEVICE_ID_ADAPTEC_AIC7870: 238 return ("Adaptec aic7870 SCSI host adapter"); 239 break; 240 case PCI_DEVICE_ID_ADAPTEC_AIC7860: 241 return ("Adaptec aic7860 SCSI host adapter"); 242 break; 243 case PCI_DEVICE_ID_ADAPTEC_AIC7855: 244 return ("Adaptec aic7855 SCSI host adapter"); 245 break; 246 case PCI_DEVICE_ID_ADAPTEC_AIC7850: 247 return ("Adaptec aic7850 SCSI host adapter"); 248 break; 249 default: 250 break; 251 } 252 return (0); 253 254 } 255 256 #elif defined(__NetBSD__) 257 258 #ifdef __BROKEN_INDIRECT_CONFIG 259 int ahc_pci_probe __P((struct device *, void *, void *)); 260 #else 261 int ahc_pci_probe __P((struct device *, struct cfdata *, void *)); 262 #endif 263 void ahc_pci_attach __P((struct device *, struct device *, void *)); 264 265 struct cfattach ahc_pci_ca = { 266 sizeof(struct ahc_data), ahc_pci_probe, ahc_pci_attach 267 }; 268 269 int 270 ahc_pci_probe(parent, match, aux) 271 struct device *parent; 272 #ifdef __BROKEN_INDIRECT_CONFIG 273 void *match, *aux; 274 #else 275 struct cfdata *match; void *aux; 276 #endif 277 { 278 struct pci_attach_args *pa = aux; 279 280 switch (pa->pa_id) { 281 case PCI_DEVICE_ID_ADAPTEC_3940U: 282 case PCI_DEVICE_ID_ADAPTEC_2944U: 283 case PCI_DEVICE_ID_ADAPTEC_2940U: 284 case PCI_DEVICE_ID_ADAPTEC_2940AU: 285 case PCI_DEVICE_ID_ADAPTEC_3940: 286 case PCI_DEVICE_ID_ADAPTEC_2944: 287 case PCI_DEVICE_ID_ADAPTEC_2940: 288 case PCI_DEVICE_ID_ADAPTEC_AIC7880: 289 case PCI_DEVICE_ID_ADAPTEC_AIC7870: 290 case PCI_DEVICE_ID_ADAPTEC_AIC7860: 291 case PCI_DEVICE_ID_ADAPTEC_AIC7855: 292 case PCI_DEVICE_ID_ADAPTEC_AIC7850: 293 return 1; 294 } 295 return 0; 296 } 297 #endif /* defined(__NetBSD__) */ 298 299 #if defined(__FreeBSD__) 300 static void 301 aic7870_attach(config_id, unit) 302 pcici_t config_id; 303 int unit; 304 #elif defined(__NetBSD__) 305 void 306 ahc_pci_attach(parent, self, aux) 307 struct device *parent, *self; 308 void *aux; 309 #endif 310 { 311 #if defined(__FreeBSD__) 312 u_long io_port; 313 int unit = ahc->sc_dev.dv_unit; 314 #elif defined(__NetBSD__) 315 struct pci_attach_args *pa = aux; 316 struct ahc_data *ahc = (void *)self; 317 bus_addr_t iobase; 318 bus_size_t iosize; 319 bus_space_handle_t ioh; 320 pci_intr_handle_t ih; 321 const char *intrstr; 322 #endif 323 u_long id; 324 unsigned opri = 0; 325 ahc_type ahc_t = AHC_NONE; 326 ahc_flag ahc_f = AHC_FNONE; 327 #if defined(__FreeBSD__) 328 struct ahc_data *ahc; 329 #endif 330 u_char ultra_enb = 0; 331 u_char our_id = 0; 332 333 #if defined(__FreeBSD__) 334 if(!(io_port = pci_conf_read(config_id, PCI_BASEADR0))) 335 return; 336 /* 337 * The first bit of PCI_BASEADR0 is always 338 * set hence we mask it off. 339 */ 340 io_port &= 0xfffffffe; 341 #elif defined(__NetBSD__) 342 if (pci_io_find(pa->pa_pc, pa->pa_tag, PCI_BASEADR0, &iobase, &iosize)) 343 return; 344 if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &ioh)) 345 return; 346 #endif 347 348 #if defined(__FreeBSD__) 349 switch ((id = pci_conf_read(config_id, PCI_ID_REG))) { 350 #elif defined(__NetBSD__) 351 switch (id = pa->pa_id) { 352 #endif 353 case PCI_DEVICE_ID_ADAPTEC_3940U: 354 case PCI_DEVICE_ID_ADAPTEC_3940: 355 if (id == PCI_DEVICE_ID_ADAPTEC_3940U) 356 ahc_t = AHC_394U; 357 else 358 ahc_t = AHC_394; 359 aic3940_count++; 360 if(!(aic3940_count & 0x01)) 361 /* Even count implies second channel */ 362 ahc_f |= AHC_CHNLB; 363 break; 364 case PCI_DEVICE_ID_ADAPTEC_2944U: 365 case PCI_DEVICE_ID_ADAPTEC_2940U: 366 ahc_t = AHC_294U; 367 break; 368 case PCI_DEVICE_ID_ADAPTEC_2944: 369 case PCI_DEVICE_ID_ADAPTEC_2940: 370 ahc_t = AHC_294; 371 break; 372 case PCI_DEVICE_ID_ADAPTEC_2940AU: 373 ahc_t = AHC_294AU; 374 break; 375 case PCI_DEVICE_ID_ADAPTEC_AIC7880: 376 ahc_t = AHC_AIC7880; 377 break; 378 case PCI_DEVICE_ID_ADAPTEC_AIC7870: 379 ahc_t = AHC_AIC7870; 380 break; 381 case PCI_DEVICE_ID_ADAPTEC_AIC7860: 382 ahc_t = AHC_AIC7860; 383 break; 384 case PCI_DEVICE_ID_ADAPTEC_AIC7855: 385 case PCI_DEVICE_ID_ADAPTEC_AIC7850: 386 ahc_t = AHC_AIC7850; 387 break; 388 default: 389 break; 390 } 391 392 /* On all PCI adapters, we allow SCB paging */ 393 ahc_f |= AHC_PAGESCBS; 394 395 /* Remeber how the card was setup in case there is no SEEPROM */ 396 #if defined(__FreeBSD__) 397 our_id = inb(SCSIID + io_port) & OID; 398 if(ahc_t & AHC_ULTRA) 399 ultra_enb = inb(SXFRCTL0 + io_port) & ULTRAEN; 400 #else 401 our_id = bus_space_read_1(pa->pa_iot, ioh, SCSIID) & OID; 402 if(ahc_t & AHC_ULTRA) 403 ultra_enb = bus_space_read_1(pa->pa_iot, ioh, 404 SXFRCTL0) & ULTRAEN; 405 #endif 406 407 #if defined(__FreeBSD__) 408 ahc_reset(io_port); 409 #elif defined(__NetBSD__) 410 printf("\n"); 411 ahc_reset(ahc->sc_dev.dv_xname, pa->pa_iot, ioh); 412 #endif 413 414 if(ahc_t & AHC_AIC7870){ 415 #if defined(__FreeBSD__) 416 u_long devconfig = pci_conf_read(config_id, DEVCONFIG); 417 #elif defined(__NetBSD__) 418 u_long devconfig = 419 pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 420 #endif 421 422 if(devconfig & (RAMPSM)) { 423 /* 424 * External SRAM present. Have the probe walk 425 * the SCBs to see how much SRAM we have and set 426 * the number of SCBs accordingly. We have to 427 * turn off SCBRAMSEL to access the external 428 * SCB SRAM. 429 * 430 * It seems that early versions of the aic7870 431 * didn't use these bits, hence the hack for the 432 * 3940 above. I would guess that recent 3940s 433 * using later aic7870 or aic7880 chips do 434 * actually set RAMPSM. 435 * 436 * The documentation isn't clear, but it sounds 437 * like the value written to devconfig must not 438 * have RAMPSM set. The second sixteen bits of 439 * the register are R/O anyway, so it shouldn't 440 * affect RAMPSM either way. 441 */ 442 devconfig &= ~(RAMPSM|SCBRAMSEL); 443 #if defined(__FreeBSD__) 444 pci_conf_write(config_id, DEVCONFIG, devconfig); 445 #elif defined(__NetBSD__) 446 pci_conf_write(pa->pa_pc, pa->pa_tag, 447 DEVCONFIG, devconfig); 448 #endif 449 } 450 } 451 452 #if defined(__FreeBSD__) 453 if(!(ahc = ahc_alloc(unit, io_port, ahc_t, ahc_f))) 454 return; /* XXX PCI code should take return status */ 455 456 if(!(pci_map_int(config_id, ahc_intr, (void *)ahc, &bio_imask))) { 457 ahc_free(ahc); 458 return; 459 } 460 #elif defined(__NetBSD__) 461 ahc_construct(ahc, pa->pa_iot, ioh, ahc_t, ahc_f); 462 463 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 464 pa->pa_intrline, &ih)) { 465 printf("%s: couldn't map interrupt\n", ahc->sc_dev.dv_xname); 466 ahc_free(ahc); 467 return; 468 } 469 intrstr = pci_intr_string(pa->pa_pc, ih); 470 #if defined(__OpenBSD__) 471 ahc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahc_intr, ahc, 472 ahc->sc_dev.dv_xname); 473 #else 474 ahc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahc_intr, ahc); 475 #endif 476 if (ahc->sc_ih == NULL) { 477 printf("%s: couldn't establish interrupt", 478 ahc->sc_dev.dv_xname); 479 if (intrstr != NULL) 480 printf(" at %s", intrstr); 481 printf("\n"); 482 ahc_free(ahc); 483 return; 484 } 485 if (intrstr != NULL) 486 printf("%s: interrupting at %s\n", ahc->sc_dev.dv_xname, 487 intrstr); 488 #endif 489 /* 490 * Protect ourself from spurrious interrupts during 491 * intialization. 492 */ 493 opri = splbio(); 494 495 /* 496 * Do aic7870/aic7880/aic7850 specific initialization 497 */ 498 { 499 u_char sblkctl; 500 char *id_string; 501 502 switch(ahc->type) { 503 case AHC_394U: 504 case AHC_294U: 505 case AHC_AIC7880: 506 { 507 id_string = "aic7880 "; 508 load_seeprom(ahc); 509 break; 510 } 511 case AHC_394: 512 case AHC_294: 513 case AHC_AIC7870: 514 { 515 id_string = "aic7870 "; 516 load_seeprom(ahc); 517 break; 518 } 519 case AHC_294AU: 520 case AHC_AIC7860: 521 { 522 id_string = "aic7860 "; 523 load_seeprom(ahc); 524 break; 525 } 526 case AHC_AIC7850: 527 { 528 id_string = "aic7850 "; 529 /* 530 * Use defaults, if the chip wasn't initialized by 531 * a BIOS. 532 */ 533 ahc->flags |= AHC_USEDEFAULTS; 534 break; 535 } 536 default: 537 { 538 printf("ahc: Unknown controller type. Ignoring.\n"); 539 ahc_free(ahc); 540 splx(opri); 541 return; 542 } 543 } 544 545 /* 546 * Take the LED out of diagnostic mode 547 */ 548 sblkctl = AHC_INB(ahc, SBLKCTL); 549 AHC_OUTB(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 550 551 /* 552 * I don't know where this is set in the SEEPROM or by the 553 * BIOS, so we default to 100%. 554 */ 555 AHC_OUTB(ahc, DSPCISTATUS, DFTHRSH_100); 556 557 if(ahc->flags & AHC_USEDEFAULTS) { 558 /* 559 * PCI Adapter default setup 560 * Should only be used if the adapter does not have 561 * an SEEPROM. 562 */ 563 /* See if someone else set us up already */ 564 u_long i; 565 for(i = TARG_SCRATCH; i < 0x60; i++) { 566 if(AHC_INB(ahc, i) != 0x00) 567 break; 568 } 569 if(i == TARG_SCRATCH) { 570 /* 571 * Try looking for all ones. You can get 572 * either. 573 */ 574 for (i = TARG_SCRATCH; i < 0x60; i++) { 575 if(AHC_INB(ahc, i) != 0xff) 576 break; 577 } 578 } 579 if((i != 0x60) && (our_id != 0)) { 580 printf("%s: Using left over BIOS settings\n", 581 ahc_name(ahc)); 582 ahc->flags &= ~AHC_USEDEFAULTS; 583 } 584 else 585 our_id = 0x07; 586 AHC_OUTB(ahc, SCSICONF, 587 (our_id & 0x07)|ENSPCHK|RESET_SCSI); 588 /* In case we are a wide card */ 589 AHC_OUTB(ahc, SCSICONF + 1, our_id); 590 591 if(!ultra_enb || (ahc->flags & AHC_USEDEFAULTS)) { 592 /* 593 * If there wasn't a BIOS or the board 594 * wasn't in this mode to begin with, 595 * turn off ultra. 596 */ 597 ahc->type &= ~AHC_ULTRA; 598 } 599 } 600 601 printf("%s: %s", ahc_name(ahc), id_string); 602 } 603 604 if(ahc_init(ahc)){ 605 ahc_free(ahc); 606 splx(opri); 607 return; /* XXX PCI code should take return status */ 608 } 609 splx(opri); 610 611 ahc_attach(ahc); 612 } 613 614 /* 615 * Read the SEEPROM. Return 0 on failure 616 */ 617 void 618 load_seeprom(ahc) 619 struct ahc_data *ahc; 620 { 621 struct seeprom_descriptor sd; 622 struct seeprom_config sc; 623 u_short *scarray = (u_short *)≻ 624 u_short checksum = 0; 625 u_char scsi_conf; 626 u_char host_id; 627 int have_seeprom; 628 629 #if defined(__FreeBSD__) 630 sd.sd_iobase = ahc->baseport + SEECTL; 631 #elif defined(__NetBSD__) 632 sd.sd_iot = ahc->sc_iot; 633 sd.sd_ioh = ahc->sc_ioh; 634 sd.sd_offset = SEECTL; 635 #endif 636 sd.sd_MS = SEEMS; 637 sd.sd_RDY = SEERDY; 638 sd.sd_CS = SEECS; 639 sd.sd_CK = SEECK; 640 sd.sd_DO = SEEDO; 641 sd.sd_DI = SEEDI; 642 643 if(bootverbose) 644 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 645 have_seeprom = acquire_seeprom(&sd); 646 if (have_seeprom) { 647 have_seeprom = read_seeprom(&sd, 648 (u_int16_t *)&sc, 649 ahc->flags & AHC_CHNLB, 650 sizeof(sc)/2); 651 release_seeprom(&sd); 652 if (have_seeprom) { 653 /* Check checksum */ 654 int i; 655 656 for (i = 0;i < (sizeof(sc)/2 - 1);i = i + 1) 657 checksum = checksum + scarray[i]; 658 if (checksum != sc.checksum) { 659 if(bootverbose) 660 printf ("checksum error"); 661 have_seeprom = 0; 662 } 663 else if(bootverbose) 664 printf("done.\n"); 665 } 666 } 667 if (!have_seeprom) { 668 if(bootverbose) 669 printf("\n%s: No SEEPROM availible\n", ahc_name(ahc)); 670 ahc->flags |= AHC_USEDEFAULTS; 671 } 672 else { 673 /* 674 * Put the data we've collected down into SRAM 675 * where ahc_init will find it. 676 */ 677 int i; 678 int max_targ = sc.max_targets & CFMAXTARG; 679 680 for(i = 0; i < max_targ; i++){ 681 u_char target_settings; 682 target_settings = (sc.device_flags[i] & CFXFER) << 4; 683 if (sc.device_flags[i] & CFSYNCH) 684 target_settings |= SOFS; 685 if (sc.device_flags[i] & CFWIDEB) 686 target_settings |= WIDEXFER; 687 if (sc.device_flags[i] & CFDISC) 688 ahc->discenable |= (0x01 << i); 689 AHC_OUTB(ahc, TARG_SCRATCH+i, target_settings); 690 } 691 AHC_OUTB(ahc, DISC_DSB, ~(ahc->discenable & 0xff)); 692 AHC_OUTB(ahc, DISC_DSB + 1, ~((ahc->discenable >> 8) & 0xff)); 693 694 host_id = sc.brtime_id & CFSCSIID; 695 696 scsi_conf = (host_id & 0x7); 697 if(sc.adapter_control & CFSPARITY) 698 scsi_conf |= ENSPCHK; 699 if(sc.adapter_control & CFRESETB) 700 scsi_conf |= RESET_SCSI; 701 702 if(ahc->type & AHC_ULTRA) { 703 /* Should we enable Ultra mode? */ 704 if(!(sc.adapter_control & CFULTRAEN)) 705 /* Treat us as a non-ultra card */ 706 ahc->type &= ~AHC_ULTRA; 707 } 708 /* Set the host ID */ 709 AHC_OUTB(ahc, SCSICONF, scsi_conf); 710 /* In case we are a wide card */ 711 AHC_OUTB(ahc, SCSICONF + 1, host_id); 712 } 713 } 714 715 static int 716 acquire_seeprom(sd) 717 struct seeprom_descriptor *sd; 718 { 719 int wait; 720 721 /* 722 * Request access of the memory port. When access is 723 * granted, SEERDY will go high. We use a 1 second 724 * timeout which should be near 1 second more than 725 * is needed. Reason: after the chip reset, there 726 * should be no contention. 727 */ 728 SEEPROM_OUTB(sd, sd->sd_MS); 729 wait = 1000; /* 1 second timeout in msec */ 730 while (--wait && ((SEEPROM_INB(sd) & sd->sd_RDY) == 0)) { 731 DELAY (1000); /* delay 1 msec */ 732 } 733 if ((SEEPROM_INB(sd) & sd->sd_RDY) == 0) { 734 SEEPROM_OUTB(sd, 0); 735 return (0); 736 } 737 return(1); 738 } 739 740 static void 741 release_seeprom(sd) 742 struct seeprom_descriptor *sd; 743 { 744 /* Release access to the memory port and the serial EEPROM. */ 745 SEEPROM_OUTB(sd, 0); 746 } 747 748 #endif /* NPCI > 0 */ 749
Indexes created Wed Oct 01 19:09:53 GMT 2025