ahc_pci.c revision 1.11
1 /* $NetBSD: ahc_pci.c,v 1.11 1997/03/13 01:04:02 cgd Exp $ */ 2 3 /* 4 * Product specific probe and attach routines for: 5 * 3940, 2940, aic7880, aic7870, aic7860 and aic7850 SCSI controllers 6 * 7 * Copyright (c) 1995, 1996 Justin T. Gibbs. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice immediately at the beginning of the file, without modification, 15 * this list of conditions, and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from Id: aic7870.c,v 1.37 1996/06/08 06:55:55 gibbs Exp 35 */ 36 37 #if defined(__FreeBSD__) 38 #include <pci.h> 39 #endif 40 #if NPCI > 0 || defined(__NetBSD__) 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/queue.h> 46 #if defined(__NetBSD__) 47 #include <sys/device.h> 48 #include <machine/bus.h> 49 #include <machine/intr.h> 50 #endif /* defined(__NetBSD__) */ 51 52 #include <scsi/scsi_all.h> 53 #include <scsi/scsiconf.h> 54 55 #if defined(__FreeBSD__) 56 57 #include <pci/pcireg.h> 58 #include <pci/pcivar.h> 59 60 #include <machine/clock.h> 61 62 #include <i386/scsi/aic7xxx.h> 63 #include <i386/scsi/93cx6.h> 64 65 #include <dev/aic7xxx/aic7xxx_reg.h> 66 67 #define PCI_BASEADR0 PCI_MAP_REG_START 68 69 #elif defined(__NetBSD__) 70 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 74 #include <dev/ic/aic7xxxreg.h> 75 #include <dev/ic/aic7xxxvar.h> 76 #include <dev/ic/smc93cx6var.h> 77 78 /* 79 * Under normal circumstances, these messages are unnecessary 80 * and not terribly cosmetic. 81 */ 82 #ifdef DEBUG 83 #define bootverbose 1 84 #else 85 #define bootverbose 0 86 #endif 87 88 #define PCI_BASEADR0 PCI_MAPREG_START 89 90 #endif /* defined(__NetBSD__) */ 91 92 #define PCI_DEVICE_ID_ADAPTEC_3940U 0x82789004ul 93 #define PCI_DEVICE_ID_ADAPTEC_2944U 0x84789004ul 94 #define PCI_DEVICE_ID_ADAPTEC_2940U 0x81789004ul 95 #define PCI_DEVICE_ID_ADAPTEC_2940AU 0x61789004ul 96 #define PCI_DEVICE_ID_ADAPTEC_3940 0x72789004ul 97 #define PCI_DEVICE_ID_ADAPTEC_2944 0x74789004ul 98 #define PCI_DEVICE_ID_ADAPTEC_2940 0x71789004ul 99 #define PCI_DEVICE_ID_ADAPTEC_AIC7880 0x80789004ul 100 #define PCI_DEVICE_ID_ADAPTEC_AIC7870 0x70789004ul 101 #define PCI_DEVICE_ID_ADAPTEC_AIC7860 0x60789004ul 102 #define PCI_DEVICE_ID_ADAPTEC_AIC7855 0x55789004ul 103 #define PCI_DEVICE_ID_ADAPTEC_AIC7850 0x50789004ul 104 105 #define DEVCONFIG 0x40 106 #define MPORTMODE 0x00000400ul /* aic7870 only */ 107 #define RAMPSM 0x00000200ul /* aic7870 only */ 108 #define VOLSENSE 0x00000100ul 109 #define SCBRAMSEL 0x00000080ul 110 #define MRDCEN 0x00000040ul 111 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 112 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 113 #define BERREN 0x00000008ul 114 #define DACEN 0x00000004ul 115 #define STPWLEVEL 0x00000002ul 116 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 117 118 #define CSIZE_LATTIME 0x0c 119 #define CACHESIZE 0x0000003ful /* only 5 bits */ 120 #define LATTIME 0x0000ff00ul 121 122 /* 123 * Define the format of the aic78X0 SEEPROM registers (16 bits). 124 * 125 */ 126 127 struct seeprom_config { 128 129 /* 130 * SCSI ID Configuration Flags 131 */ 132 #define CFXFER 0x0007 /* synchronous transfer rate */ 133 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 134 #define CFDISC 0x0010 /* enable disconnection */ 135 #define CFWIDEB 0x0020 /* wide bus device */ 136 /* UNUSED 0x00C0 */ 137 #define CFSTART 0x0100 /* send start unit SCSI command */ 138 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 139 #define CFRNFOUND 0x0400 /* report even if not found */ 140 /* UNUSED 0xf800 */ 141 u_int16_t device_flags[16]; /* words 0-15 */ 142 143 /* 144 * BIOS Control Bits 145 */ 146 #define CFSUPREM 0x0001 /* support all removeable drives */ 147 #define CFSUPREMB 0x0002 /* support removeable drives for boot only */ 148 #define CFBIOSEN 0x0004 /* BIOS enabled */ 149 /* UNUSED 0x0008 */ 150 #define CFSM2DRV 0x0010 /* support more than two drives */ 151 /* UNUSED 0x0060 */ 152 #define CFEXTEND 0x0080 /* extended translation enabled */ 153 /* UNUSED 0xff00 */ 154 u_int16_t bios_control; /* word 16 */ 155 156 /* 157 * Host Adapter Control Bits 158 */ 159 /* UNUSED 0x0001 */ 160 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable (Ultra cards) */ 161 #define CFSTERM 0x0004 /* SCSI low byte termination (non-wide cards) */ 162 #define CFWSTERM 0x0008 /* SCSI high byte termination (wide card) */ 163 #define CFSPARITY 0x0010 /* SCSI parity */ 164 /* UNUSED 0x0020 */ 165 #define CFRESETB 0x0040 /* reset SCSI bus at IC initialization */ 166 /* UNUSED 0xff80 */ 167 u_int16_t adapter_control; /* word 17 */ 168 169 /* 170 * Bus Release, Host Adapter ID 171 */ 172 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 173 /* UNUSED 0x00f0 */ 174 #define CFBRTIME 0xff00 /* bus release time */ 175 u_int16_t brtime_id; /* word 18 */ 176 177 /* 178 * Maximum targets 179 */ 180 #define CFMAXTARG 0x00ff /* maximum targets */ 181 /* UNUSED 0xff00 */ 182 u_int16_t max_targets; /* word 19 */ 183 184 u_int16_t res_1[11]; /* words 20-30 */ 185 u_int16_t checksum; /* word 31 */ 186 }; 187 188 static void load_seeprom __P((struct ahc_data *ahc)); 189 static int acquire_seeprom __P((struct seeprom_descriptor *sd)); 190 static void release_seeprom __P((struct seeprom_descriptor *sd)); 191 192 static u_char aic3940_count; 193 194 #if defined(__FreeBSD__) 195 196 static char* aic7870_probe __P((pcici_t tag, pcidi_t type)); 197 static void aic7870_attach __P((pcici_t config_id, int unit)); 198 199 static struct pci_device ahc_pci_driver = { 200 "ahc", 201 aic7870_probe, 202 aic7870_attach, 203 &ahc_unit, 204 NULL 205 }; 206 207 DATA_SET (pcidevice_set, ahc_pci_driver); 208 209 static char* 210 aic7870_probe (pcici_t tag, pcidi_t type) 211 { 212 switch(type) { 213 case PCI_DEVICE_ID_ADAPTEC_3940U: 214 return ("Adaptec 3940 Ultra SCSI host adapter"); 215 break; 216 case PCI_DEVICE_ID_ADAPTEC_3940: 217 return ("Adaptec 3940 SCSI host adapter"); 218 break; 219 case PCI_DEVICE_ID_ADAPTEC_2944U: 220 return ("Adaptec 2944 Ultra SCSI host adapter"); 221 break; 222 case PCI_DEVICE_ID_ADAPTEC_2940U: 223 return ("Adaptec 2940 Ultra SCSI host adapter"); 224 break; 225 case PCI_DEVICE_ID_ADAPTEC_2944: 226 return ("Adaptec 2944 SCSI host adapter"); 227 break; 228 case PCI_DEVICE_ID_ADAPTEC_2940: 229 return ("Adaptec 2940 SCSI host adapter"); 230 break; 231 case PCI_DEVICE_ID_ADAPTEC_2940AU: 232 return ("Adaptec 2940A Ultra SCSI host adapter"); 233 break; 234 case PCI_DEVICE_ID_ADAPTEC_AIC7880: 235 return ("Adaptec aic7880 Ultra SCSI host adapter"); 236 break; 237 case PCI_DEVICE_ID_ADAPTEC_AIC7870: 238 return ("Adaptec aic7870 SCSI host adapter"); 239 break; 240 case PCI_DEVICE_ID_ADAPTEC_AIC7860: 241 return ("Adaptec aic7860 SCSI host adapter"); 242 break; 243 case PCI_DEVICE_ID_ADAPTEC_AIC7855: 244 return ("Adaptec aic7855 SCSI host adapter"); 245 break; 246 case PCI_DEVICE_ID_ADAPTEC_AIC7850: 247 return ("Adaptec aic7850 SCSI host adapter"); 248 break; 249 default: 250 break; 251 } 252 return (0); 253 254 } 255 256 #elif defined(__NetBSD__) 257 258 #ifdef __BROKEN_INDIRECT_CONFIG 259 int ahc_pci_probe __P((struct device *, void *, void *)); 260 #else 261 int ahc_pci_probe __P((struct device *, struct cfdata *, void *)); 262 #endif 263 void ahc_pci_attach __P((struct device *, struct device *, void *)); 264 265 struct cfattach ahc_pci_ca = { 266 sizeof(struct ahc_data), ahc_pci_probe, ahc_pci_attach 267 }; 268 269 int 270 ahc_pci_probe(parent, match, aux) 271 struct device *parent; 272 #ifdef __BROKEN_INDIRECT_CONFIG 273 void *match; 274 #else 275 struct cfdata *match; 276 #endif 277 void *aux; 278 { 279 struct pci_attach_args *pa = aux; 280 281 switch (pa->pa_id) { 282 case PCI_DEVICE_ID_ADAPTEC_3940U: 283 case PCI_DEVICE_ID_ADAPTEC_2944U: 284 case PCI_DEVICE_ID_ADAPTEC_2940U: 285 case PCI_DEVICE_ID_ADAPTEC_2940AU: 286 case PCI_DEVICE_ID_ADAPTEC_3940: 287 case PCI_DEVICE_ID_ADAPTEC_2944: 288 case PCI_DEVICE_ID_ADAPTEC_2940: 289 case PCI_DEVICE_ID_ADAPTEC_AIC7880: 290 case PCI_DEVICE_ID_ADAPTEC_AIC7870: 291 case PCI_DEVICE_ID_ADAPTEC_AIC7860: 292 case PCI_DEVICE_ID_ADAPTEC_AIC7855: 293 case PCI_DEVICE_ID_ADAPTEC_AIC7850: 294 return 1; 295 } 296 return 0; 297 } 298 #endif /* defined(__NetBSD__) */ 299 300 #if defined(__FreeBSD__) 301 static void 302 aic7870_attach(config_id, unit) 303 pcici_t config_id; 304 int unit; 305 #elif defined(__NetBSD__) 306 void 307 ahc_pci_attach(parent, self, aux) 308 struct device *parent, *self; 309 void *aux; 310 #endif 311 { 312 #if defined(__FreeBSD__) 313 u_long io_port; 314 int unit = ahc->sc_dev.dv_unit; 315 #elif defined(__NetBSD__) 316 struct pci_attach_args *pa = aux; 317 struct ahc_data *ahc = (void *)self; 318 bus_addr_t iobase; 319 bus_size_t iosize; 320 bus_space_handle_t ioh; 321 pci_intr_handle_t ih; 322 const char *intrstr; 323 #endif 324 u_long id; 325 unsigned opri = 0; 326 ahc_type ahc_t = AHC_NONE; 327 ahc_flag ahc_f = AHC_FNONE; 328 #if defined(__FreeBSD__) 329 struct ahc_data *ahc; 330 #endif 331 u_char ultra_enb = 0; 332 u_char our_id = 0; 333 334 #if defined(__FreeBSD__) 335 if(!(io_port = pci_conf_read(config_id, PCI_BASEADR0))) 336 return; 337 /* 338 * The first bit of PCI_BASEADR0 is always 339 * set hence we mask it off. 340 */ 341 io_port &= 0xfffffffe; 342 #elif defined(__NetBSD__) 343 if (pci_io_find(pa->pa_pc, pa->pa_tag, PCI_BASEADR0, &iobase, &iosize)) 344 return; 345 if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &ioh)) 346 return; 347 #endif 348 349 #if defined(__FreeBSD__) 350 switch ((id = pci_conf_read(config_id, PCI_ID_REG))) { 351 #elif defined(__NetBSD__) 352 switch (id = pa->pa_id) { 353 #endif 354 case PCI_DEVICE_ID_ADAPTEC_3940U: 355 case PCI_DEVICE_ID_ADAPTEC_3940: 356 if (id == PCI_DEVICE_ID_ADAPTEC_3940U) 357 ahc_t = AHC_394U; 358 else 359 ahc_t = AHC_394; 360 aic3940_count++; 361 if(!(aic3940_count & 0x01)) 362 /* Even count implies second channel */ 363 ahc_f |= AHC_CHNLB; 364 break; 365 case PCI_DEVICE_ID_ADAPTEC_2944U: 366 case PCI_DEVICE_ID_ADAPTEC_2940U: 367 ahc_t = AHC_294U; 368 break; 369 case PCI_DEVICE_ID_ADAPTEC_2944: 370 case PCI_DEVICE_ID_ADAPTEC_2940: 371 ahc_t = AHC_294; 372 break; 373 case PCI_DEVICE_ID_ADAPTEC_2940AU: 374 ahc_t = AHC_294AU; 375 break; 376 case PCI_DEVICE_ID_ADAPTEC_AIC7880: 377 ahc_t = AHC_AIC7880; 378 break; 379 case PCI_DEVICE_ID_ADAPTEC_AIC7870: 380 ahc_t = AHC_AIC7870; 381 break; 382 case PCI_DEVICE_ID_ADAPTEC_AIC7860: 383 ahc_t = AHC_AIC7860; 384 break; 385 case PCI_DEVICE_ID_ADAPTEC_AIC7855: 386 case PCI_DEVICE_ID_ADAPTEC_AIC7850: 387 ahc_t = AHC_AIC7850; 388 break; 389 default: 390 break; 391 } 392 393 /* On all PCI adapters, we allow SCB paging */ 394 ahc_f |= AHC_PAGESCBS; 395 396 /* Remeber how the card was setup in case there is no SEEPROM */ 397 #if defined(__FreeBSD__) 398 our_id = inb(SCSIID + io_port) & OID; 399 if(ahc_t & AHC_ULTRA) 400 ultra_enb = inb(SXFRCTL0 + io_port) & ULTRAEN; 401 #else 402 our_id = bus_space_read_1(pa->pa_iot, ioh, SCSIID) & OID; 403 if(ahc_t & AHC_ULTRA) 404 ultra_enb = bus_space_read_1(pa->pa_iot, ioh, 405 SXFRCTL0) & ULTRAEN; 406 #endif 407 408 #if defined(__FreeBSD__) 409 ahc_reset(io_port); 410 #elif defined(__NetBSD__) 411 printf("\n"); 412 ahc_reset(ahc->sc_dev.dv_xname, pa->pa_iot, ioh); 413 #endif 414 415 if(ahc_t & AHC_AIC7870){ 416 #if defined(__FreeBSD__) 417 u_long devconfig = pci_conf_read(config_id, DEVCONFIG); 418 #elif defined(__NetBSD__) 419 u_long devconfig = 420 pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 421 #endif 422 423 if(devconfig & (RAMPSM)) { 424 /* 425 * External SRAM present. Have the probe walk 426 * the SCBs to see how much SRAM we have and set 427 * the number of SCBs accordingly. We have to 428 * turn off SCBRAMSEL to access the external 429 * SCB SRAM. 430 * 431 * It seems that early versions of the aic7870 432 * didn't use these bits, hence the hack for the 433 * 3940 above. I would guess that recent 3940s 434 * using later aic7870 or aic7880 chips do 435 * actually set RAMPSM. 436 * 437 * The documentation isn't clear, but it sounds 438 * like the value written to devconfig must not 439 * have RAMPSM set. The second sixteen bits of 440 * the register are R/O anyway, so it shouldn't 441 * affect RAMPSM either way. 442 */ 443 devconfig &= ~(RAMPSM|SCBRAMSEL); 444 #if defined(__FreeBSD__) 445 pci_conf_write(config_id, DEVCONFIG, devconfig); 446 #elif defined(__NetBSD__) 447 pci_conf_write(pa->pa_pc, pa->pa_tag, 448 DEVCONFIG, devconfig); 449 #endif 450 } 451 } 452 453 #if defined(__FreeBSD__) 454 if(!(ahc = ahc_alloc(unit, io_port, ahc_t, ahc_f))) 455 return; /* XXX PCI code should take return status */ 456 457 if(!(pci_map_int(config_id, ahc_intr, (void *)ahc, &bio_imask))) { 458 ahc_free(ahc); 459 return; 460 } 461 #elif defined(__NetBSD__) 462 ahc_construct(ahc, pa->pa_iot, ioh, ahc_t, ahc_f); 463 464 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 465 pa->pa_intrline, &ih)) { 466 printf("%s: couldn't map interrupt\n", ahc->sc_dev.dv_xname); 467 ahc_free(ahc); 468 return; 469 } 470 intrstr = pci_intr_string(pa->pa_pc, ih); 471 #if defined(__OpenBSD__) 472 ahc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahc_intr, ahc, 473 ahc->sc_dev.dv_xname); 474 #else 475 ahc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahc_intr, ahc); 476 #endif 477 if (ahc->sc_ih == NULL) { 478 printf("%s: couldn't establish interrupt", 479 ahc->sc_dev.dv_xname); 480 if (intrstr != NULL) 481 printf(" at %s", intrstr); 482 printf("\n"); 483 ahc_free(ahc); 484 return; 485 } 486 if (intrstr != NULL) 487 printf("%s: interrupting at %s\n", ahc->sc_dev.dv_xname, 488 intrstr); 489 #endif 490 /* 491 * Protect ourself from spurrious interrupts during 492 * intialization. 493 */ 494 opri = splbio(); 495 496 /* 497 * Do aic7870/aic7880/aic7850 specific initialization 498 */ 499 { 500 u_char sblkctl; 501 char *id_string; 502 503 switch(ahc->type) { 504 case AHC_394U: 505 case AHC_294U: 506 case AHC_AIC7880: 507 { 508 id_string = "aic7880 "; 509 load_seeprom(ahc); 510 break; 511 } 512 case AHC_394: 513 case AHC_294: 514 case AHC_AIC7870: 515 { 516 id_string = "aic7870 "; 517 load_seeprom(ahc); 518 break; 519 } 520 case AHC_294AU: 521 case AHC_AIC7860: 522 { 523 id_string = "aic7860 "; 524 load_seeprom(ahc); 525 break; 526 } 527 case AHC_AIC7850: 528 { 529 id_string = "aic7850 "; 530 /* 531 * Use defaults, if the chip wasn't initialized by 532 * a BIOS. 533 */ 534 ahc->flags |= AHC_USEDEFAULTS; 535 break; 536 } 537 default: 538 { 539 printf("ahc: Unknown controller type. Ignoring.\n"); 540 ahc_free(ahc); 541 splx(opri); 542 return; 543 } 544 } 545 546 /* 547 * Take the LED out of diagnostic mode 548 */ 549 sblkctl = AHC_INB(ahc, SBLKCTL); 550 AHC_OUTB(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 551 552 /* 553 * I don't know where this is set in the SEEPROM or by the 554 * BIOS, so we default to 100%. 555 */ 556 AHC_OUTB(ahc, DSPCISTATUS, DFTHRSH_100); 557 558 if(ahc->flags & AHC_USEDEFAULTS) { 559 /* 560 * PCI Adapter default setup 561 * Should only be used if the adapter does not have 562 * an SEEPROM. 563 */ 564 /* See if someone else set us up already */ 565 u_long i; 566 for(i = TARG_SCRATCH; i < 0x60; i++) { 567 if(AHC_INB(ahc, i) != 0x00) 568 break; 569 } 570 if(i == TARG_SCRATCH) { 571 /* 572 * Try looking for all ones. You can get 573 * either. 574 */ 575 for (i = TARG_SCRATCH; i < 0x60; i++) { 576 if(AHC_INB(ahc, i) != 0xff) 577 break; 578 } 579 } 580 if((i != 0x60) && (our_id != 0)) { 581 printf("%s: Using left over BIOS settings\n", 582 ahc_name(ahc)); 583 ahc->flags &= ~AHC_USEDEFAULTS; 584 } 585 else 586 our_id = 0x07; 587 AHC_OUTB(ahc, SCSICONF, 588 (our_id & 0x07)|ENSPCHK|RESET_SCSI); 589 /* In case we are a wide card */ 590 AHC_OUTB(ahc, SCSICONF + 1, our_id); 591 592 if(!ultra_enb || (ahc->flags & AHC_USEDEFAULTS)) { 593 /* 594 * If there wasn't a BIOS or the board 595 * wasn't in this mode to begin with, 596 * turn off ultra. 597 */ 598 ahc->type &= ~AHC_ULTRA; 599 } 600 } 601 602 printf("%s: %s", ahc_name(ahc), id_string); 603 } 604 605 if(ahc_init(ahc)){ 606 ahc_free(ahc); 607 splx(opri); 608 return; /* XXX PCI code should take return status */ 609 } 610 splx(opri); 611 612 ahc_attach(ahc); 613 } 614 615 /* 616 * Read the SEEPROM. Return 0 on failure 617 */ 618 void 619 load_seeprom(ahc) 620 struct ahc_data *ahc; 621 { 622 struct seeprom_descriptor sd; 623 struct seeprom_config sc; 624 u_short *scarray = (u_short *)≻ 625 u_short checksum = 0; 626 u_char scsi_conf; 627 u_char host_id; 628 int have_seeprom; 629 630 #if defined(__FreeBSD__) 631 sd.sd_iobase = ahc->baseport + SEECTL; 632 #elif defined(__NetBSD__) 633 sd.sd_iot = ahc->sc_iot; 634 sd.sd_ioh = ahc->sc_ioh; 635 sd.sd_offset = SEECTL; 636 #endif 637 sd.sd_MS = SEEMS; 638 sd.sd_RDY = SEERDY; 639 sd.sd_CS = SEECS; 640 sd.sd_CK = SEECK; 641 sd.sd_DO = SEEDO; 642 sd.sd_DI = SEEDI; 643 644 if(bootverbose) 645 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 646 have_seeprom = acquire_seeprom(&sd); 647 if (have_seeprom) { 648 have_seeprom = read_seeprom(&sd, 649 (u_int16_t *)&sc, 650 ahc->flags & AHC_CHNLB, 651 sizeof(sc)/2); 652 release_seeprom(&sd); 653 if (have_seeprom) { 654 /* Check checksum */ 655 int i; 656 657 for (i = 0;i < (sizeof(sc)/2 - 1);i = i + 1) 658 checksum = checksum + scarray[i]; 659 if (checksum != sc.checksum) { 660 if(bootverbose) 661 printf ("checksum error"); 662 have_seeprom = 0; 663 } 664 else if(bootverbose) 665 printf("done.\n"); 666 } 667 } 668 if (!have_seeprom) { 669 if(bootverbose) 670 printf("\n%s: No SEEPROM availible\n", ahc_name(ahc)); 671 ahc->flags |= AHC_USEDEFAULTS; 672 } 673 else { 674 /* 675 * Put the data we've collected down into SRAM 676 * where ahc_init will find it. 677 */ 678 int i; 679 int max_targ = sc.max_targets & CFMAXTARG; 680 681 for(i = 0; i < max_targ; i++){ 682 u_char target_settings; 683 target_settings = (sc.device_flags[i] & CFXFER) << 4; 684 if (sc.device_flags[i] & CFSYNCH) 685 target_settings |= SOFS; 686 if (sc.device_flags[i] & CFWIDEB) 687 target_settings |= WIDEXFER; 688 if (sc.device_flags[i] & CFDISC) 689 ahc->discenable |= (0x01 << i); 690 AHC_OUTB(ahc, TARG_SCRATCH+i, target_settings); 691 } 692 AHC_OUTB(ahc, DISC_DSB, ~(ahc->discenable & 0xff)); 693 AHC_OUTB(ahc, DISC_DSB + 1, ~((ahc->discenable >> 8) & 0xff)); 694 695 host_id = sc.brtime_id & CFSCSIID; 696 697 scsi_conf = (host_id & 0x7); 698 if(sc.adapter_control & CFSPARITY) 699 scsi_conf |= ENSPCHK; 700 if(sc.adapter_control & CFRESETB) 701 scsi_conf |= RESET_SCSI; 702 703 if(ahc->type & AHC_ULTRA) { 704 /* Should we enable Ultra mode? */ 705 if(!(sc.adapter_control & CFULTRAEN)) 706 /* Treat us as a non-ultra card */ 707 ahc->type &= ~AHC_ULTRA; 708 } 709 /* Set the host ID */ 710 AHC_OUTB(ahc, SCSICONF, scsi_conf); 711 /* In case we are a wide card */ 712 AHC_OUTB(ahc, SCSICONF + 1, host_id); 713 } 714 } 715 716 static int 717 acquire_seeprom(sd) 718 struct seeprom_descriptor *sd; 719 { 720 int wait; 721 722 /* 723 * Request access of the memory port. When access is 724 * granted, SEERDY will go high. We use a 1 second 725 * timeout which should be near 1 second more than 726 * is needed. Reason: after the chip reset, there 727 * should be no contention. 728 */ 729 SEEPROM_OUTB(sd, sd->sd_MS); 730 wait = 1000; /* 1 second timeout in msec */ 731 while (--wait && ((SEEPROM_INB(sd) & sd->sd_RDY) == 0)) { 732 DELAY (1000); /* delay 1 msec */ 733 } 734 if ((SEEPROM_INB(sd) & sd->sd_RDY) == 0) { 735 SEEPROM_OUTB(sd, 0); 736 return (0); 737 } 738 return(1); 739 } 740 741 static void 742 release_seeprom(sd) 743 struct seeprom_descriptor *sd; 744 { 745 /* Release access to the memory port and the serial EEPROM. */ 746 SEEPROM_OUTB(sd, 0); 747 } 748 749 #endif /* NPCI > 0 */ 750
Indexes created Wed Oct 01 19:09:53 GMT 2025