ahc_pci.c revision 1.2
1 /* $NetBSD: ahc_pci.c,v 1.2 1996/05/20 00:56:39 thorpej Exp $ */ 2 3 /* 4 * Product specific probe and attach routines for: 5 * 3940, 2940, aic7880, aic7870, aic7860 and aic7850 SCSI controllers 6 * 7 * Copyright (c) 1995, 1996 Justin T. Gibbs. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice immediately at the beginning of the file, without modification, 15 * this list of conditions, and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 #if defined(__FreeBSD__) 36 #include <pci.h> 37 #endif 38 #if NPCI > 0 || defined(__NetBSD__) 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/malloc.h> 42 #include <sys/kernel.h> 43 #include <sys/queue.h> 44 #if defined(__NetBSD__) 45 #include <sys/device.h> 46 #include <machine/bus.h> 47 #ifdef __alpha__ 48 #include <machine/intr.h> 49 #endif 50 #endif /* defined(__NetBSD__) */ 51 52 #include <scsi/scsi_all.h> 53 #include <scsi/scsiconf.h> 54 55 #if defined(__FreeBSD__) 56 57 #include <pci/pcireg.h> 58 #include <pci/pcivar.h> 59 60 #include <machine/clock.h> 61 62 #include <i386/scsi/aic7xxx.h> 63 #include <i386/scsi/93cx6.h> 64 65 #include <dev/aic7xxx/aic7xxx_reg.h> 66 67 #define PCI_BASEADR0 PCI_MAP_REG_START 68 69 #elif defined(__NetBSD__) 70 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 74 #include <dev/ic/aic7xxxreg.h> 75 #include <dev/ic/aic7xxxvar.h> 76 #include <dev/ic/smc93cx6var.h> 77 78 #define bootverbose 1 79 #define PCI_BASEADR0 PCI_MAPREG_START 80 81 #endif /* defined(__NetBSD__) */ 82 83 #define PCI_DEVICE_ID_ADAPTEC_3940U 0x82789004ul 84 #define PCI_DEVICE_ID_ADAPTEC_2944U 0x84789004ul 85 #define PCI_DEVICE_ID_ADAPTEC_2940U 0x81789004ul 86 #define PCI_DEVICE_ID_ADAPTEC_3940 0x72789004ul 87 #define PCI_DEVICE_ID_ADAPTEC_2944 0x74789004ul 88 #define PCI_DEVICE_ID_ADAPTEC_2940 0x71789004ul 89 #define PCI_DEVICE_ID_ADAPTEC_AIC7880 0x80789004ul 90 #define PCI_DEVICE_ID_ADAPTEC_AIC7870 0x70789004ul 91 #define PCI_DEVICE_ID_ADAPTEC_AIC7860 0x60789004ul 92 #define PCI_DEVICE_ID_ADAPTEC_AIC7855 0x55789004ul 93 #define PCI_DEVICE_ID_ADAPTEC_AIC7850 0x50789004ul 94 95 #define DEVCONFIG 0x40 96 #define MPORTMODE 0x00000400ul /* aic7870 only */ 97 #define RAMPSM 0x00000200ul /* aic7870 only */ 98 #define VOLSENSE 0x00000100ul 99 #define SCBRAMSEL 0x00000080ul 100 #define MRDCEN 0x00000040ul 101 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 102 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 103 #define BERREN 0x00000008ul 104 #define DACEN 0x00000004ul 105 #define STPWLEVEL 0x00000002ul 106 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 107 108 #define CSIZE_LATTIME 0x0c 109 #define CACHESIZE 0x0000003ful /* only 5 bits */ 110 #define LATTIME 0x0000ff00ul 111 112 /* 113 * Define the format of the aic78X0 SEEPROM registers (16 bits). 114 * 115 */ 116 117 struct seeprom_config { 118 119 /* 120 * SCSI ID Configuration Flags 121 */ 122 #define CFXFER 0x0007 /* synchronous transfer rate */ 123 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 124 #define CFDISC 0x0010 /* enable disconnection */ 125 #define CFWIDEB 0x0020 /* wide bus device */ 126 /* UNUSED 0x00C0 */ 127 #define CFSTART 0x0100 /* send start unit SCSI command */ 128 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 129 #define CFRNFOUND 0x0400 /* report even if not found */ 130 /* UNUSED 0xf800 */ 131 u_int16_t device_flags[16]; /* words 0-15 */ 132 133 /* 134 * BIOS Control Bits 135 */ 136 #define CFSUPREM 0x0001 /* support all removeable drives */ 137 #define CFSUPREMB 0x0002 /* support removeable drives for boot only */ 138 #define CFBIOSEN 0x0004 /* BIOS enabled */ 139 /* UNUSED 0x0008 */ 140 #define CFSM2DRV 0x0010 /* support more than two drives */ 141 /* UNUSED 0x0060 */ 142 #define CFEXTEND 0x0080 /* extended translation enabled */ 143 /* UNUSED 0xff00 */ 144 u_int16_t bios_control; /* word 16 */ 145 146 /* 147 * Host Adapter Control Bits 148 */ 149 /* UNUSED 0x0001 */ 150 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable (Ultra cards) */ 151 #define CFSTERM 0x0004 /* SCSI low byte termination (non-wide cards) */ 152 #define CFWSTERM 0x0008 /* SCSI high byte termination (wide card) */ 153 #define CFSPARITY 0x0010 /* SCSI parity */ 154 /* UNUSED 0x0020 */ 155 #define CFRESETB 0x0040 /* reset SCSI bus at IC initialization */ 156 /* UNUSED 0xff80 */ 157 u_int16_t adapter_control; /* word 17 */ 158 159 /* 160 * Bus Release, Host Adapter ID 161 */ 162 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 163 /* UNUSED 0x00f0 */ 164 #define CFBRTIME 0xff00 /* bus release time */ 165 u_int16_t brtime_id; /* word 18 */ 166 167 /* 168 * Maximum targets 169 */ 170 #define CFMAXTARG 0x00ff /* maximum targets */ 171 /* UNUSED 0xff00 */ 172 u_int16_t max_targets; /* word 19 */ 173 174 u_int16_t res_1[11]; /* words 20-30 */ 175 u_int16_t checksum; /* word 31 */ 176 }; 177 178 static void load_seeprom __P((struct ahc_data *ahc)); 179 180 static u_char aic3940_count; 181 182 #if defined(__FreeBSD__) 183 184 static char* aic7870_probe __P((pcici_t tag, pcidi_t type)); 185 static void aic7870_attach __P((pcici_t config_id, int unit)); 186 187 static struct pci_device ahc_pci_driver = { 188 "ahc", 189 aic7870_probe, 190 aic7870_attach, 191 &ahc_unit, 192 NULL 193 }; 194 195 DATA_SET (pcidevice_set, ahc_pci_driver); 196 197 static char* 198 aic7870_probe (pcici_t tag, pcidi_t type) 199 { 200 switch(type) { 201 case PCI_DEVICE_ID_ADAPTEC_3940U: 202 return ("Adaptec 3940 Ultra SCSI host adapter"); 203 break; 204 case PCI_DEVICE_ID_ADAPTEC_3940: 205 return ("Adaptec 3940 SCSI host adapter"); 206 break; 207 case PCI_DEVICE_ID_ADAPTEC_2944U: 208 return ("Adaptec 2944 Ultra SCSI host adapter"); 209 break; 210 case PCI_DEVICE_ID_ADAPTEC_2940U: 211 return ("Adaptec 2940 Ultra SCSI host adapter"); 212 break; 213 case PCI_DEVICE_ID_ADAPTEC_2944: 214 return ("Adaptec 2944 SCSI host adapter"); 215 break; 216 case PCI_DEVICE_ID_ADAPTEC_2940: 217 return ("Adaptec 2940 SCSI host adapter"); 218 break; 219 case PCI_DEVICE_ID_ADAPTEC_AIC7880: 220 return ("Adaptec aic7880 Ultra SCSI host adapter"); 221 break; 222 case PCI_DEVICE_ID_ADAPTEC_AIC7870: 223 return ("Adaptec aic7870 SCSI host adapter"); 224 break; 225 case PCI_DEVICE_ID_ADAPTEC_AIC7860: 226 return ("Adaptec aic7860 SCSI host adapter"); 227 break; 228 case PCI_DEVICE_ID_ADAPTEC_AIC7855: 229 return ("Adaptec aic7855 SCSI host adapter"); 230 break; 231 case PCI_DEVICE_ID_ADAPTEC_AIC7850: 232 return ("Adaptec aic7850 SCSI host adapter"); 233 break; 234 default: 235 break; 236 } 237 return (0); 238 239 } 240 241 #elif defined(__NetBSD__) 242 243 int ahc_pci_probe __P((struct device *, void *, void *)); 244 void ahc_pci_attach __P((struct device *, struct device *, void *)); 245 246 struct cfattach ahc_pci_ca = { 247 sizeof(struct ahc_data), ahc_pci_probe, ahc_pci_attach 248 }; 249 250 int 251 ahc_pci_probe(parent, match, aux) 252 struct device *parent; 253 void *match, *aux; 254 { 255 struct pci_attach_args *pa = aux; 256 257 switch (pa->pa_id) { 258 case PCI_DEVICE_ID_ADAPTEC_3940U: 259 case PCI_DEVICE_ID_ADAPTEC_2944U: 260 case PCI_DEVICE_ID_ADAPTEC_2940U: 261 case PCI_DEVICE_ID_ADAPTEC_3940: 262 case PCI_DEVICE_ID_ADAPTEC_2944: 263 case PCI_DEVICE_ID_ADAPTEC_2940: 264 case PCI_DEVICE_ID_ADAPTEC_AIC7880: 265 case PCI_DEVICE_ID_ADAPTEC_AIC7870: 266 case PCI_DEVICE_ID_ADAPTEC_AIC7860: 267 case PCI_DEVICE_ID_ADAPTEC_AIC7855: 268 case PCI_DEVICE_ID_ADAPTEC_AIC7850: 269 return 1; 270 } 271 return 0; 272 } 273 #endif /* defined(__NetBSD__) */ 274 275 #if defined(__FreeBSD__) 276 static void 277 aic7870_attach(config_id, unit) 278 pcici_t config_id; 279 int unit; 280 #elif defined(__NetBSD__) 281 void 282 ahc_pci_attach(parent, self, aux) 283 struct device *parent, *self; 284 void *aux; 285 #endif 286 { 287 #if defined(__FreeBSD__) 288 u_long io_port; 289 #elif defined(__NetBSD__) 290 struct pci_attach_args *pa = aux; 291 struct ahc_data *ahc = (void *)self; 292 int unit = ahc->sc_dev.dv_unit; 293 bus_io_addr_t iobase; 294 bus_io_size_t iosize; 295 bus_io_handle_t ioh; 296 pci_intr_handle_t ih; 297 const char *intrstr; 298 #endif 299 u_long id; 300 unsigned opri = 0; 301 ahc_type ahc_t = AHC_NONE; 302 ahc_flag ahc_f = AHC_FNONE; 303 #if defined(__FreeBSD__) 304 struct ahc_data *ahc; 305 #endif 306 u_char ultra_enb = 0; 307 u_char our_id = 0; 308 309 #if defined(__FreeBSD__) 310 if(!(io_port = pci_conf_read(config_id, PCI_BASEADR0))) 311 return; 312 /* 313 * The first bit of PCI_BASEADR0 is always 314 * set hence we mask it off. 315 */ 316 io_port &= 0xfffffffe; 317 #elif defined(__NetBSD__) 318 if (pci_io_find(pa->pa_pc, pa->pa_tag, PCI_BASEADR0, &iobase, &iosize)) 319 return; 320 if (bus_io_map(pa->pa_bc, iobase, iosize, &ioh)) 321 return; 322 #endif 323 324 #if defined(__FreeBSD__) 325 switch ((id = pci_conf_read(config_id, PCI_ID_REG))) { 326 #elif defined(__NetBSD__) 327 switch (id = pa->pa_id) { 328 #endif 329 case PCI_DEVICE_ID_ADAPTEC_3940U: 330 case PCI_DEVICE_ID_ADAPTEC_3940: 331 if (id == PCI_DEVICE_ID_ADAPTEC_3940U) 332 ahc_t = AHC_394U; 333 else 334 ahc_t = AHC_394; 335 aic3940_count++; 336 if(!(aic3940_count & 0x01)) 337 /* Even count implies second channel */ 338 ahc_f |= AHC_CHNLB; 339 break; 340 case PCI_DEVICE_ID_ADAPTEC_2944U: 341 case PCI_DEVICE_ID_ADAPTEC_2940U: 342 ahc_t = AHC_294U; 343 break; 344 case PCI_DEVICE_ID_ADAPTEC_2944: 345 case PCI_DEVICE_ID_ADAPTEC_2940: 346 ahc_t = AHC_294; 347 break; 348 case PCI_DEVICE_ID_ADAPTEC_AIC7880: 349 ahc_t = AHC_AIC7880; 350 break; 351 case PCI_DEVICE_ID_ADAPTEC_AIC7870: 352 ahc_t = AHC_AIC7870; 353 break; 354 case PCI_DEVICE_ID_ADAPTEC_AIC7860: 355 ahc_t = AHC_AIC7860; 356 break; 357 case PCI_DEVICE_ID_ADAPTEC_AIC7855: 358 case PCI_DEVICE_ID_ADAPTEC_AIC7850: 359 ahc_t = AHC_AIC7850; 360 break; 361 default: 362 break; 363 } 364 365 /* On all PCI adapters, we allow SCB paging */ 366 ahc_f |= AHC_PAGESCBS; 367 368 /* Remeber how the card was setup in case there is no SEEPROM */ 369 #if defined(__FreeBSD__) 370 our_id = inb(SCSIID + io_port) & OID; 371 if(ahc_t & AHC_ULTRA) 372 ultra_enb = inb(SXFRCTL0 + io_port) & ULTRAEN; 373 #else 374 our_id = bus_io_read_1(pa->pa_bc, ioh, SCSIID) & OID; 375 if(ahc_t & AHC_ULTRA) 376 ultra_enb = bus_io_read_1(pa->pa_bc, ioh, SXFRCTL0) & ULTRAEN; 377 #endif 378 379 #if defined(__FreeBSD__) 380 ahc_reset(io_port); 381 #elif defined(__NetBSD__) 382 printf("\n"); 383 ahc_reset(ahc->sc_dev.dv_xname, pa->pa_bc, ioh); 384 #endif 385 386 if(ahc_t & AHC_AIC7870){ 387 #if defined(__FreeBSD__) 388 u_long devconfig = pci_conf_read(config_id, DEVCONFIG); 389 #elif defined(__NetBSD__) 390 u_long devconfig = 391 pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 392 #endif 393 394 if(devconfig & (RAMPSM)) { 395 /* 396 * External SRAM present. Have the probe walk 397 * the SCBs to see how much SRAM we have and set 398 * the number of SCBs accordingly. We have to 399 * turn off SCBRAMSEL to access the external 400 * SCB SRAM. 401 * 402 * It seems that early versions of the aic7870 403 * didn't use these bits, hence the hack for the 404 * 3940 above. I would guess that recent 3940s 405 * using later aic7870 or aic7880 chips do 406 * actually set RAMPSM. 407 * 408 * The documentation isn't clear, but it sounds 409 * like the value written to devconfig must not 410 * have RAMPSM set. The second sixteen bits of 411 * the register are R/O anyway, so it shouldn't 412 * affect RAMPSM either way. 413 */ 414 devconfig &= ~(RAMPSM|SCBRAMSEL); 415 #if defined(__FreeBSD__) 416 pci_conf_write(config_id, DEVCONFIG, devconfig); 417 #elif defined(__NetBSD__) 418 pci_conf_write(pa->pa_pc, pa->pa_tag, 419 DEVCONFIG, devconfig); 420 #endif 421 } 422 } 423 424 /* 425 * Ensure that we are using good values for the PCI burst size 426 * and latency timer. 427 */ 428 { 429 #if defined(__FreeBSD__) 430 u_long csize_lattime = pci_conf_read(config_id, CSIZE_LATTIME); 431 #elif defined(__NetBSD__) 432 u_long csize_lattime = 433 pci_conf_read(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME); 434 #endif 435 436 if((csize_lattime & CACHESIZE) == 0) { 437 /* default to 8DWDs. What's the PCI define for this? */ 438 csize_lattime |= 8; 439 } 440 if((csize_lattime & LATTIME) == 0) { 441 /* Default to 64 PCLKS (is this a good value?) */ 442 /* This may also be availble in the SEEPROM?? */ 443 csize_lattime |= (64 << 8); 444 } 445 if(bootverbose) 446 printf("ahc%d: BurstLen = %ldDWDs, " 447 "Latency Timer = %ldPCLKS\n", 448 unit, 449 csize_lattime & CACHESIZE, 450 (csize_lattime >> 8) & 0xff); 451 #if defined(__FreeBSD__) 452 pci_conf_write(config_id, CSIZE_LATTIME, csize_lattime); 453 #elif defined(__NetBSD__) 454 pci_conf_write(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME, 455 csize_lattime); 456 #endif 457 } 458 459 #if defined(__FreeBSD__) 460 if(!(ahc = ahc_alloc(unit, io_port, ahc_t, ahc_f))) 461 return; /* XXX PCI code should take return status */ 462 463 if(!(pci_map_int(config_id, ahc_intr, (void *)ahc, &bio_imask))) { 464 ahc_free(ahc); 465 return; 466 } 467 #elif defined(__NetBSD__) 468 ahc_construct(ahc, pa->pa_bc, ioh, ahc_t, ahc_f); 469 470 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 471 pa->pa_intrline, &ih)) { 472 printf("%s: couldn't map interrupt\n", ahc->sc_dev.dv_xname); 473 ahc_free(ahc); 474 return; 475 } 476 intrstr = pci_intr_string(pa->pa_pc, ih); 477 ahc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahc_intr, ahc 478 #ifdef __OpenBSD__ 479 , ahc->sc_dev.dv_xname 480 #endif 481 ); 482 if (ahc->sc_ih == NULL) { 483 printf("%s: couldn't establish interrupt", 484 ahc->sc_dev.dv_xname); 485 if (intrstr != NULL) 486 printf(" at %s", intrstr); 487 printf("\n"); 488 ahc_free(ahc); 489 return; 490 } 491 if (intrstr != NULL) 492 printf("%s: interrupting at %s\n", ahc->sc_dev.dv_xname, 493 intrstr); 494 #endif 495 /* 496 * Protect ourself from spurrious interrupts during 497 * intialization. 498 */ 499 opri = splbio(); 500 501 /* 502 * Do aic7870/aic7880/aic7850 specific initialization 503 */ 504 { 505 u_char sblkctl; 506 char *id_string; 507 508 switch(ahc->type) { 509 case AHC_394U: 510 case AHC_294U: 511 case AHC_AIC7880: 512 { 513 id_string = "aic7880 "; 514 load_seeprom(ahc); 515 break; 516 } 517 case AHC_394: 518 case AHC_294: 519 case AHC_AIC7870: 520 { 521 id_string = "aic7870 "; 522 load_seeprom(ahc); 523 break; 524 } 525 case AHC_AIC7860: 526 { 527 id_string = "aic7860 "; 528 /* 529 * Use defaults, if the chip wasn't initialized by 530 * a BIOS. 531 */ 532 ahc->flags |= AHC_USEDEFAULTS; 533 break; 534 } 535 case AHC_AIC7850: 536 { 537 id_string = "aic7850 "; 538 /* 539 * Use defaults, if the chip wasn't initialized by 540 * a BIOS. 541 */ 542 ahc->flags |= AHC_USEDEFAULTS; 543 break; 544 } 545 default: 546 { 547 printf("ahc: Unknown controller type. Ignoring.\n"); 548 ahc_free(ahc); 549 splx(opri); 550 return; 551 } 552 } 553 554 /* 555 * Take the LED out of diagnostic mode 556 */ 557 sblkctl = AHC_INB(ahc, SBLKCTL); 558 AHC_OUTB(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 559 560 /* 561 * I don't know where this is set in the SEEPROM or by the 562 * BIOS, so we default to 100%. 563 */ 564 AHC_OUTB(ahc, DSPCISTATUS, DFTHRSH_100); 565 566 if(ahc->flags & AHC_USEDEFAULTS) { 567 /* 568 * PCI Adapter default setup 569 * Should only be used if the adapter does not have 570 * an SEEPROM. 571 */ 572 /* See if someone else set us up already */ 573 u_long i; 574 for(i = TARG_SCRATCH; i < 0x60; i++) { 575 if(AHC_INB(ahc, i) != 0xff) 576 break; 577 } 578 if(i != 0x60) { 579 printf("%s: Using left over BIOS settings\n", 580 ahc_name(ahc)); 581 ahc->flags &= ~AHC_USEDEFAULTS; 582 } 583 else 584 our_id = 0x07; 585 AHC_OUTB(ahc, SCSICONF, 586 (our_id & 0x07)|ENSPCHK|RESET_SCSI); 587 /* In case we are a wide card */ 588 AHC_OUTB(ahc, SCSICONF + 1, our_id); 589 590 if(!ultra_enb || (ahc->flags & AHC_USEDEFAULTS)) { 591 /* 592 * If there wasn't a BIOS or the board 593 * wasn't in this mode to begin with, 594 * turn off ultra. 595 */ 596 ahc->type &= ~AHC_ULTRA; 597 } 598 } 599 600 printf("%s: %s", ahc_name(ahc), id_string); 601 } 602 603 if(ahc_init(ahc)){ 604 ahc_free(ahc); 605 splx(opri); 606 return; /* XXX PCI code should take return status */ 607 } 608 splx(opri); 609 610 ahc_attach(ahc); 611 return; 612 } 613 614 /* 615 * Read the SEEPROM. Return 0 on failure 616 */ 617 void 618 load_seeprom(ahc) 619 struct ahc_data *ahc; 620 { 621 struct seeprom_descriptor sd; 622 struct seeprom_config sc; 623 u_short *scarray = (u_short *)≻ 624 u_short checksum = 0; 625 u_char scsi_conf; 626 u_char host_id; 627 int have_seeprom; 628 629 #if defined(__FreeBSD__) 630 sd.sd_iobase = ahc->baseport + SEECTL; 631 #elif defined(__NetBSD__) 632 sd.sd_bc = ahc->sc_bc; 633 sd.sd_ioh = ahc->sc_ioh; 634 sd.sd_offset = SEECTL; 635 #endif 636 sd.sd_MS = SEEMS; 637 sd.sd_RDY = SEERDY; 638 sd.sd_CS = SEECS; 639 sd.sd_CK = SEECK; 640 sd.sd_DO = SEEDO; 641 sd.sd_DI = SEEDI; 642 643 if(bootverbose) 644 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 645 have_seeprom = acquire_seeprom(&sd); 646 if (have_seeprom) { 647 have_seeprom = read_seeprom(&sd, 648 (u_int16_t *)&sc, 649 ahc->flags & AHC_CHNLB, 650 sizeof(sc)/2); 651 release_seeprom(&sd); 652 if (have_seeprom) { 653 /* Check checksum */ 654 int i; 655 656 for (i = 0;i < (sizeof(sc)/2 - 1);i = i + 1) 657 checksum = checksum + scarray[i]; 658 if (checksum != sc.checksum) { 659 if(bootverbose) 660 printf ("checksum error"); 661 have_seeprom = 0; 662 } 663 else if(bootverbose) 664 printf("done.\n"); 665 } 666 } 667 if (!have_seeprom) { 668 if(bootverbose) 669 printf("\n%s: No SEEPROM availible\n", ahc_name(ahc)); 670 ahc->flags |= AHC_USEDEFAULTS; 671 } 672 else { 673 /* 674 * Put the data we've collected down into SRAM 675 * where ahc_init will find it. 676 */ 677 int i; 678 int max_targ = sc.max_targets & CFMAXTARG; 679 680 for(i = 0; i <= max_targ; i++){ 681 u_char target_settings; 682 target_settings = (sc.device_flags[i] & CFXFER) << 4; 683 if (sc.device_flags[i] & CFSYNCH) 684 target_settings |= SOFS; 685 if (sc.device_flags[i] & CFWIDEB) 686 target_settings |= WIDEXFER; 687 if (sc.device_flags[i] & CFDISC) 688 ahc->discenable |= (0x01 << i); 689 AHC_OUTB(ahc, TARG_SCRATCH+i, target_settings); 690 } 691 AHC_OUTB(ahc, DISC_DSB, ~(ahc->discenable & 0xff)); 692 AHC_OUTB(ahc, DISC_DSB + 1, ~((ahc->discenable >> 8) & 0xff)); 693 694 host_id = sc.brtime_id & CFSCSIID; 695 696 scsi_conf = (host_id & 0x7); 697 if(sc.adapter_control & CFSPARITY) 698 scsi_conf |= ENSPCHK; 699 if(sc.adapter_control & CFRESETB) 700 scsi_conf |= RESET_SCSI; 701 702 if(ahc->type & AHC_ULTRA) { 703 /* Should we enable Ultra mode? */ 704 if(!(sc.adapter_control & CFULTRAEN)) 705 /* Treat us as a non-ultra card */ 706 ahc->type &= ~AHC_ULTRA; 707 } 708 /* Set the host ID */ 709 AHC_OUTB(ahc, SCSICONF, scsi_conf); 710 /* In case we are a wide card */ 711 AHC_OUTB(ahc, SCSICONF + 1, host_id); 712 } 713 } 714 715 #endif /* NPCI > 0 */ 716
Indexes created Wed Oct 01 19:09:53 GMT 2025