ahc_pci.c revision 1.24
1 /* $NetBSD: ahc_pci.c,v 1.24 2000/05/10 17:07:52 thorpej Exp $ */ 2 3 /* 4 * Product specific probe and attach routines for: 5 * 3940, 2940, aic7895, aic7890, aic7880, 6 * aic7870, aic7860 and aic7850 SCSI controllers 7 * 8 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * Alternatively, this software may be distributed under the terms of the 21 * the GNU Public License ("GPL"). 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/aic7xxx/ahc_pci.c,v 1.28 2000/02/09 21:00:22 gibbs Exp $ 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/device.h> 44 45 #include <machine/bus.h> 46 #include <machine/intr.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 51 /* XXXX some i386 on-board chips act weird when memory-mapped */ 52 #ifndef __i386__ 53 #define AHC_ALLOW_MEMIO 54 #endif 55 56 #define AHC_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 57 #define AHC_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 58 59 #include <dev/scsipi/scsi_all.h> 60 #include <dev/scsipi/scsipi_all.h> 61 #include <dev/scsipi/scsiconf.h> 62 63 #include <dev/ic/aic7xxxvar.h> 64 #include <dev/ic/smc93cx6var.h> 65 66 #include <dev/microcode/aic7xxx/aic7xxx_reg.h> 67 68 #ifdef DEBUG 69 #define bootverbose 1 70 #else 71 #define bootverbose 1 72 #endif 73 74 struct ahc_pci_busdata { 75 pci_chipset_tag_t pc; 76 pcitag_t tag; 77 u_int dev; 78 u_int func; 79 }; 80 81 static __inline u_int64_t 82 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 83 { 84 u_int64_t id; 85 86 id = subvendor 87 | (subdevice << 16) 88 | ((u_int64_t)vendor << 32) 89 | ((u_int64_t)device << 48); 90 91 return (id); 92 } 93 94 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 95 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 96 #define ID_AIC7850 0x5078900400000000ull 97 #define ID_AHA_2910_15_20_30C 0x5078900478509004ull 98 #define ID_AIC7855 0x5578900400000000ull 99 #define ID_AIC7859 0x3860900400000000ull 100 #define ID_AHA_2930CU 0x3860900438699004ull 101 #define ID_AIC7860 0x6078900400000000ull 102 #define ID_AIC7860C 0x6078900478609004ull 103 #define ID_AHA_2940AU_0 0x6178900400000000ull 104 #define ID_AHA_2940AU_1 0x6178900478619004ull 105 #define ID_AHA_2940AU_CN 0x2178900478219004ull 106 #define ID_AHA_2930C_VAR 0x6038900438689004ull 107 108 #define ID_AIC7870 0x7078900400000000ull 109 #define ID_AHA_2940 0x7178900400000000ull 110 #define ID_AHA_3940 0x7278900400000000ull 111 #define ID_AHA_398X 0x7378900400000000ull 112 #define ID_AHA_2944 0x7478900400000000ull 113 #define ID_AHA_3944 0x7578900400000000ull 114 115 #define ID_AIC7880 0x8078900400000000ull 116 #define ID_AIC7880_B 0x8078900478809004ull 117 #define ID_AHA_2940U 0x8178900400000000ull 118 #define ID_AHA_3940U 0x8278900400000000ull 119 #define ID_AHA_2944U 0x8478900400000000ull 120 #define ID_AHA_3944U 0x8578900400000000ull 121 #define ID_AHA_398XU 0x8378900400000000ull 122 #define ID_AHA_4944U 0x8678900400000000ull 123 #define ID_AHA_2940UB 0x8178900478819004ull 124 #define ID_AHA_2930U 0x8878900478889004ull 125 #define ID_AHA_2940U_PRO 0x8778900478879004ull 126 #define ID_AHA_2940U_CN 0x0078900478009004ull 127 128 #define ID_AIC7895 0x7895900478959004ull 129 #define ID_AIC7895_RAID_PORT 0x7893900478939004ull 130 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 131 #define ID_AHA_3940AU 0x7895900478929004ull 132 #define ID_AHA_3944AU 0x7895900478949004ull 133 134 #define ID_AIC7890 0x001F9005000F9005ull 135 #define ID_AHA_2930U2 0x0011900501819005ull 136 #define ID_AHA_2940U2B 0x00109005A1009005ull 137 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 138 #define ID_AHA_2940U2 0x00109005A1809005ull 139 #define ID_AHA_2950U2B 0x00109005E1009005ull 140 141 #define ID_AIC7892 0x008F9005FFFF9005ull 142 #define ID_AHA_29160 0x00809005E2A09005ull 143 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 144 #define ID_AHA_29160N 0x0080900562A09005ull 145 #define ID_AHA_29160B 0x00809005E2209005ull 146 #define ID_AHA_19160B 0x0081900562A19005ull 147 148 #define ID_AIC7896 0x005F9005FFFF9005ull 149 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 150 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 151 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 152 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 153 154 #define ID_AIC7899 0x00CF9005FFFF9005ull 155 #define ID_AHA_3960D 0x00C09005F6209005ull /* AKA AHA-39160 */ 156 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 157 158 #define ID_AIC7810 0x1078900400000000ull 159 #define ID_AIC7815 0x1578900400000000ull 160 161 typedef int (ahc_device_setup_t)(struct pci_attach_args *, char *, 162 ahc_chip *, ahc_feature *, ahc_flag *); 163 164 static ahc_device_setup_t ahc_aic7850_setup; 165 static ahc_device_setup_t ahc_aic7855_setup; 166 static ahc_device_setup_t ahc_aic7859_setup; 167 static ahc_device_setup_t ahc_aic7860_setup; 168 static ahc_device_setup_t ahc_aic7870_setup; 169 static ahc_device_setup_t ahc_aha394X_setup; 170 static ahc_device_setup_t ahc_aha398X_setup; 171 static ahc_device_setup_t ahc_aic7880_setup; 172 static ahc_device_setup_t ahc_2940Pro_setup; 173 static ahc_device_setup_t ahc_aha394XU_setup; 174 static ahc_device_setup_t ahc_aha398XU_setup; 175 static ahc_device_setup_t ahc_aic7890_setup; 176 static ahc_device_setup_t ahc_aic7892_setup; 177 static ahc_device_setup_t ahc_aic7895_setup; 178 static ahc_device_setup_t ahc_aic7896_setup; 179 static ahc_device_setup_t ahc_aic7899_setup; 180 static ahc_device_setup_t ahc_raid_setup; 181 static ahc_device_setup_t ahc_aha394XX_setup; 182 static ahc_device_setup_t ahc_aha398XX_setup; 183 184 struct ahc_pci_identity { 185 u_int64_t full_id; 186 u_int64_t id_mask; 187 char *name; 188 ahc_device_setup_t *setup; 189 }; 190 191 struct ahc_pci_identity ahc_pci_ident_table [] = 192 { 193 /* aic7850 based controllers */ 194 { 195 ID_AHA_2910_15_20_30C, 196 ID_ALL_MASK, 197 "Adaptec 2910/15/20/30C SCSI adapter", 198 ahc_aic7850_setup 199 }, 200 /* aic7859 based controllers */ 201 { 202 ID_AHA_2930CU, 203 ID_ALL_MASK, 204 "Adaptec 2930CU SCSI adapter", 205 ahc_aic7859_setup 206 }, 207 /* aic7860 based controllers */ 208 { 209 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 210 ID_DEV_VENDOR_MASK, 211 "Adaptec 2940A Ultra SCSI adapter", 212 ahc_aic7860_setup 213 }, 214 { 215 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 216 ID_DEV_VENDOR_MASK, 217 "Adaptec 2940A/CN Ultra SCSI adapter", 218 ahc_aic7860_setup 219 }, 220 { 221 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 222 ID_DEV_VENDOR_MASK, 223 "Adaptec 2930C SCSI adapter (VAR)", 224 ahc_aic7860_setup 225 }, 226 /* aic7870 based controllers */ 227 { 228 ID_AHA_2940, 229 ID_ALL_MASK, 230 "Adaptec 2940 SCSI adapter", 231 ahc_aic7870_setup 232 }, 233 { 234 ID_AHA_3940, 235 ID_ALL_MASK, 236 "Adaptec 3940 SCSI adapter", 237 ahc_aha394X_setup 238 }, 239 { 240 ID_AHA_398X, 241 ID_ALL_MASK, 242 "Adaptec 398X SCSI RAID adapter", 243 ahc_aha398X_setup 244 }, 245 { 246 ID_AHA_2944, 247 ID_ALL_MASK, 248 "Adaptec 2944 SCSI adapter", 249 ahc_aic7870_setup 250 }, 251 { 252 ID_AHA_3944, 253 ID_ALL_MASK, 254 "Adaptec 3944 SCSI adapter", 255 ahc_aha394X_setup 256 }, 257 /* aic7880 based controllers */ 258 { 259 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 260 ID_DEV_VENDOR_MASK, 261 "Adaptec 2940 Ultra SCSI adapter", 262 ahc_aic7880_setup 263 }, 264 { 265 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 266 ID_DEV_VENDOR_MASK, 267 "Adaptec 3940 Ultra SCSI adapter", 268 ahc_aha394XU_setup 269 }, 270 { 271 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 272 ID_DEV_VENDOR_MASK, 273 "Adaptec 2944 Ultra SCSI adapter", 274 ahc_aic7880_setup 275 }, 276 { 277 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 278 ID_DEV_VENDOR_MASK, 279 "Adaptec 3944 Ultra SCSI adapter", 280 ahc_aha394XU_setup 281 }, 282 { 283 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 284 ID_DEV_VENDOR_MASK, 285 "Adaptec 398X Ultra SCSI RAID adapter", 286 ahc_aha398XU_setup 287 }, 288 { 289 /* 290 * XXX Don't know the slot numbers 291 * so we can't identify channels 292 */ 293 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 294 ID_DEV_VENDOR_MASK, 295 "Adaptec 4944 Ultra SCSI adapter", 296 ahc_aic7880_setup 297 }, 298 { 299 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 300 ID_DEV_VENDOR_MASK, 301 "Adaptec 2930 Ultra SCSI adapter", 302 ahc_aic7880_setup 303 }, 304 { 305 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 306 ID_DEV_VENDOR_MASK, 307 "Adaptec 2940 Pro Ultra SCSI adapter", 308 ahc_2940Pro_setup 309 }, 310 { 311 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 312 ID_DEV_VENDOR_MASK, 313 "Adaptec 2940/CN Ultra SCSI adapter", 314 ahc_aic7880_setup 315 }, 316 /* aic7890 based controllers */ 317 { 318 ID_AHA_2930U2, 319 ID_ALL_MASK, 320 "Adaptec 2930 Ultra2 SCSI adapter", 321 ahc_aic7890_setup 322 }, 323 { 324 ID_AHA_2940U2B, 325 ID_ALL_MASK, 326 "Adaptec 2940B Ultra2 SCSI adapter", 327 ahc_aic7890_setup 328 }, 329 { 330 ID_AHA_2940U2_OEM, 331 ID_ALL_MASK, 332 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 333 ahc_aic7890_setup 334 }, 335 { 336 ID_AHA_2940U2, 337 ID_ALL_MASK, 338 "Adaptec 2940 Ultra2 SCSI adapter", 339 ahc_aic7890_setup 340 }, 341 { 342 ID_AHA_2950U2B, 343 ID_ALL_MASK, 344 "Adaptec 2950 Ultra2 SCSI adapter", 345 ahc_aic7890_setup 346 }, 347 /* aic7892 based controllers */ 348 { 349 ID_AHA_29160, 350 ID_ALL_MASK, 351 "Adaptec 29160 Ultra160 SCSI adapter", 352 ahc_aic7892_setup 353 }, 354 { 355 ID_AHA_29160_CPQ, 356 ID_ALL_MASK, 357 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 358 ahc_aic7892_setup 359 }, 360 { 361 ID_AHA_29160N, 362 ID_ALL_MASK, 363 "Adaptec 29160N Ultra160 SCSI adapter", 364 ahc_aic7892_setup 365 }, 366 { 367 ID_AHA_29160B, 368 ID_ALL_MASK, 369 "Adaptec 29160B Ultra160 SCSI adapter", 370 ahc_aic7892_setup 371 }, 372 { 373 ID_AHA_19160B, 374 ID_ALL_MASK, 375 "Adaptec 19160B Ultra160 SCSI adapter", 376 ahc_aic7892_setup 377 }, 378 /* aic7895 based controllers */ 379 { 380 ID_AHA_2940U_DUAL, 381 ID_ALL_MASK, 382 "Adaptec 2940/DUAL Ultra SCSI adapter", 383 ahc_aic7895_setup 384 }, 385 { 386 ID_AHA_3940AU, 387 ID_ALL_MASK, 388 "Adaptec 3940A Ultra SCSI adapter", 389 ahc_aic7895_setup 390 }, 391 { 392 ID_AHA_3944AU, 393 ID_ALL_MASK, 394 "Adaptec 3944A Ultra SCSI adapter", 395 ahc_aic7895_setup 396 }, 397 /* aic7896/97 based controllers */ 398 { 399 ID_AHA_3950U2B_0, 400 ID_ALL_MASK, 401 "Adaptec 3950B Ultra2 SCSI adapter", 402 ahc_aic7896_setup 403 }, 404 { 405 ID_AHA_3950U2B_1, 406 ID_ALL_MASK, 407 "Adaptec 3950B Ultra2 SCSI adapter", 408 ahc_aic7896_setup 409 }, 410 { 411 ID_AHA_3950U2D_0, 412 ID_ALL_MASK, 413 "Adaptec 3950D Ultra2 SCSI adapter", 414 ahc_aic7896_setup 415 }, 416 { 417 ID_AHA_3950U2D_1, 418 ID_ALL_MASK, 419 "Adaptec 3950D Ultra2 SCSI adapter", 420 ahc_aic7896_setup 421 }, 422 /* aic7899 based controllers */ 423 { 424 ID_AHA_3960D, 425 ID_ALL_MASK, 426 "Adaptec 3960D Ultra160 SCSI adapter", 427 ahc_aic7899_setup 428 }, 429 { 430 ID_AHA_3960D_CPQ, 431 ID_ALL_MASK, 432 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 433 ahc_aic7899_setup 434 }, 435 /* Generic chip probes for devices we don't know 'exactly' */ 436 { 437 ID_AIC7850 & ID_DEV_VENDOR_MASK, 438 ID_DEV_VENDOR_MASK, 439 "Adaptec aic7850 SCSI adapter", 440 ahc_aic7850_setup 441 }, 442 { 443 ID_AIC7855 & ID_DEV_VENDOR_MASK, 444 ID_DEV_VENDOR_MASK, 445 "Adaptec aic7855 SCSI adapter", 446 ahc_aic7855_setup 447 }, 448 { 449 ID_AIC7859 & ID_DEV_VENDOR_MASK, 450 ID_DEV_VENDOR_MASK, 451 "Adaptec aic7859 SCSI adapter", 452 ahc_aic7859_setup 453 }, 454 { 455 ID_AIC7860 & ID_DEV_VENDOR_MASK, 456 ID_DEV_VENDOR_MASK, 457 "Adaptec aic7860 SCSI adapter", 458 ahc_aic7860_setup 459 }, 460 { 461 ID_AIC7870 & ID_DEV_VENDOR_MASK, 462 ID_DEV_VENDOR_MASK, 463 "Adaptec aic7870 SCSI adapter", 464 ahc_aic7870_setup 465 }, 466 { 467 ID_AIC7880 & ID_DEV_VENDOR_MASK, 468 ID_DEV_VENDOR_MASK, 469 "Adaptec aic7880 Ultra SCSI adapter", 470 ahc_aic7880_setup 471 }, 472 { 473 ID_AIC7890 & ID_DEV_VENDOR_MASK, 474 ID_DEV_VENDOR_MASK, 475 "Adaptec aic7890/91 Ultra2 SCSI adapter", 476 ahc_aic7890_setup 477 }, 478 { 479 ID_AIC7892 & ID_DEV_VENDOR_MASK, 480 ID_DEV_VENDOR_MASK, 481 "Adaptec aic7892 Ultra160 SCSI adapter", 482 ahc_aic7892_setup 483 }, 484 { 485 ID_AIC7895 & ID_DEV_VENDOR_MASK, 486 ID_DEV_VENDOR_MASK, 487 "Adaptec aic7895 Ultra SCSI adapter", 488 ahc_aic7895_setup 489 }, 490 { 491 ID_AIC7895_RAID_PORT & ID_DEV_VENDOR_MASK, 492 ID_DEV_VENDOR_MASK, 493 "Adaptec aic7895 Ultra SCSI adapter (RAID PORT)", 494 ahc_aic7895_setup 495 }, 496 { 497 ID_AIC7896 & ID_DEV_VENDOR_MASK, 498 ID_DEV_VENDOR_MASK, 499 "Adaptec aic7896/97 Ultra2 SCSI adapter", 500 ahc_aic7896_setup 501 }, 502 { 503 ID_AIC7899 & ID_DEV_VENDOR_MASK, 504 ID_DEV_VENDOR_MASK, 505 "Adaptec aic7899 Ultra160 SCSI adapter", 506 ahc_aic7899_setup 507 }, 508 { 509 ID_AIC7810 & ID_DEV_VENDOR_MASK, 510 ID_DEV_VENDOR_MASK, 511 "Adaptec aic7810 RAID memory controller", 512 ahc_raid_setup 513 }, 514 { 515 ID_AIC7815 & ID_DEV_VENDOR_MASK, 516 ID_DEV_VENDOR_MASK, 517 "Adaptec aic7815 RAID memory controller", 518 ahc_raid_setup 519 } 520 }; 521 522 static const int ahc_num_pci_devs = 523 sizeof(ahc_pci_ident_table) / sizeof(*ahc_pci_ident_table); 524 525 #define AHC_394X_SLOT_CHANNEL_A 4 526 #define AHC_394X_SLOT_CHANNEL_B 5 527 528 #define AHC_398X_SLOT_CHANNEL_A 4 529 #define AHC_398X_SLOT_CHANNEL_B 8 530 #define AHC_398X_SLOT_CHANNEL_C 12 531 532 #define DEVCONFIG 0x40 533 #define SCBSIZE32 0x00010000 /* aic789X only */ 534 #define MPORTMODE 0x00000400 /* aic7870 only */ 535 #define RAMPSM 0x00000200 /* aic7870 only */ 536 #define VOLSENSE 0x00000100 537 #define SCBRAMSEL 0x00000080 538 #define MRDCEN 0x00000040 539 #define EXTSCBTIME 0x00000020 /* aic7870 only */ 540 #define EXTSCBPEN 0x00000010 /* aic7870 only */ 541 #define BERREN 0x00000008 542 #define DACEN 0x00000004 543 #define STPWLEVEL 0x00000002 544 #define DIFACTNEGEN 0x00000001 /* aic7870 only */ 545 546 #define CSIZE_LATTIME 0x0c 547 #define CACHESIZE 0x0000003f /* only 5 bits */ 548 #define LATTIME 0x0000ff00 549 550 static struct ahc_pci_identity *ahc_find_pci_device(pcireg_t, pcireg_t); 551 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 552 static void ahc_ext_scbram_config(struct ahc_softc *ahc, int enable, 553 int pcheck, int fast); 554 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 555 556 int ahc_pci_probe __P((struct device *, struct cfdata *, void *)); 557 void ahc_pci_attach __P((struct device *, struct device *, void *)); 558 559 /* Exported for use in the ahc_intr routine */ 560 int ahc_pci_intr(struct ahc_softc *ahc); 561 562 struct cfattach ahc_pci_ca = { 563 sizeof(struct ahc_softc), ahc_pci_probe, ahc_pci_attach 564 }; 565 566 static struct ahc_pci_identity * 567 ahc_find_pci_device(id, subid) 568 pcireg_t id, subid; 569 { 570 u_int64_t full_id; 571 struct ahc_pci_identity *entry; 572 u_int i; 573 574 full_id = ahc_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 575 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 576 577 for (i = 0; i < ahc_num_pci_devs; i++) { 578 entry = &ahc_pci_ident_table[i]; 579 if (entry->full_id == (full_id & entry->id_mask)) 580 return (entry); 581 } 582 return (NULL); 583 } 584 585 int 586 ahc_pci_probe(parent, match, aux) 587 struct device *parent; 588 struct cfdata *match; 589 void *aux; 590 { 591 struct pci_attach_args *pa = aux; 592 struct ahc_pci_identity *entry; 593 pcireg_t subid; 594 595 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 596 entry = ahc_find_pci_device(pa->pa_id, subid); 597 return entry != NULL ? 1 : 0; 598 } 599 600 void 601 ahc_pci_attach(parent, self, aux) 602 struct device *parent, *self; 603 void *aux; 604 { 605 struct pci_attach_args *pa = aux; 606 struct ahc_pci_identity *entry; 607 struct ahc_softc *ahc = (void *)self; 608 pcireg_t command; 609 ahc_chip ahc_t = AHC_NONE; 610 ahc_feature ahc_fe = AHC_FENONE; 611 ahc_flag ahc_f = AHC_FNONE; 612 u_int our_id = 0; 613 u_int sxfrctl1; 614 u_int scsiseq; 615 int error; 616 char channel; 617 pcireg_t subid; 618 int ioh_valid, memh_valid; 619 bus_space_tag_t st, iot; 620 bus_space_handle_t sh, ioh; 621 #ifdef AHC_ALLOW_MEMIO 622 bus_space_tag_t memt; 623 bus_space_handle_t memh; 624 pcireg_t memtype; 625 #endif 626 pci_intr_handle_t ih; 627 const char *intrstr; 628 struct ahc_pci_busdata *bd; 629 630 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 631 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 632 entry = ahc_find_pci_device(pa->pa_id, subid); 633 if (entry == NULL) 634 return; 635 error = entry->setup(pa, &channel, &ahc_t, &ahc_fe, &ahc_f); 636 if (error != 0) 637 return; 638 639 ioh_valid = memh_valid = 0; 640 641 #ifdef AHC_ALLOW_MEMIO 642 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHC_PCI_MEMADDR); 643 switch (memtype) { 644 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 645 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 646 memh_valid = (pci_mapreg_map(pa, AHC_PCI_MEMADDR, 647 memtype, 0, &memt, &memh, NULL, NULL) == 0); 648 break; 649 default: 650 memh_valid = 0; 651 } 652 #endif 653 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_IOADDR, 654 PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, NULL, NULL) == 0); 655 656 if (ioh_valid) { 657 st = iot; 658 sh = ioh; 659 #ifdef AHC_ALLOW_MEMIO 660 } else if (memh_valid) { 661 st = memt; 662 sh = memh; 663 #endif 664 } else { 665 printf(": unable to map registers\n"); 666 return; 667 } 668 669 printf("\n"); 670 671 672 /* Ensure busmastering is enabled */ 673 command |= PCI_COMMAND_MASTER_ENABLE;; 674 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 675 676 /* On all PCI adapters, we allow SCB paging */ 677 ahc_f |= AHC_PAGESCBS; 678 if (ahc_alloc(ahc, sh, st, pa->pa_dmat, 679 ahc_t|AHC_PCI, ahc_fe, ahc_f) < 0) 680 return; 681 682 bd = malloc(sizeof (struct ahc_pci_busdata), M_DEVBUF, M_NOWAIT); 683 if (bd == NULL) { 684 printf(": unable to allocate bus-specific data\n"); 685 return; 686 } 687 688 bd->pc = pa->pa_pc; 689 bd->tag = pa->pa_tag; 690 bd->func = pa->pa_function; 691 bd->dev = pa->pa_device; 692 693 ahc->bus_data = bd; 694 ahc->bus_intr = ahc_pci_intr; 695 ahc->channel = channel; 696 697 /* Remeber how the card was setup in case there is no SEEPROM */ 698 ahc_outb(ahc, HCNTRL, ahc->pause); 699 if ((ahc->features & AHC_ULTRA2) != 0) 700 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 701 else 702 our_id = ahc_inb(ahc, SCSIID) & OID; 703 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 704 scsiseq = ahc_inb(ahc, SCSISEQ); 705 706 if (ahc_reset(ahc) != 0) { 707 /* Failed */ 708 ahc_free(ahc); 709 return; 710 } 711 712 if ((ahc->features & AHC_DT) != 0) { 713 u_int optionmode; 714 u_int sfunct; 715 716 /* Perform ALT-Mode Setup */ 717 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 718 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 719 optionmode = ahc_inb(ahc, OPTIONMODE); 720 printf("OptionMode = %x\n", optionmode); 721 ahc_outb(ahc, OPTIONMODE, OPTIONMODE_DEFAULTS); 722 /* Send CRC info in target mode every 4K */ 723 ahc_outb(ahc, TARGCRCCNT, 0); 724 ahc_outb(ahc, TARGCRCCNT + 1, 0x10); 725 ahc_outb(ahc, SFUNCT, sfunct); 726 727 /* Normal mode setup */ 728 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 729 |TARGCRCENDEN|TARGCRCCNTEN); 730 } 731 732 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 733 pa->pa_intrline, &ih)) { 734 printf("%s: couldn't map interrupt\n", ahc->sc_dev.dv_xname); 735 ahc_free(ahc); 736 return; 737 } 738 intrstr = pci_intr_string(pa->pa_pc, ih); 739 ahc->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahc_intr, ahc); 740 if (ahc->ih == NULL) { 741 printf("%s: couldn't establish interrupt", 742 ahc->sc_dev.dv_xname); 743 if (intrstr != NULL) 744 printf(" at %s", intrstr); 745 printf("\n"); 746 ahc_free(ahc); 747 return; 748 } 749 if (intrstr != NULL) 750 printf("%s: interrupting at %s\n", ahc->sc_dev.dv_xname, 751 intrstr); 752 753 /* 754 * Do aic7880/aic7870/aic7860/aic7850 specific initialization 755 */ 756 { 757 u_int8_t sblkctl; 758 u_int dscommand0; 759 760 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 761 dscommand0 |= MPARCKEN; 762 if ((ahc->features & AHC_ULTRA2) != 0) { 763 764 /* 765 * DPARCKEN doesn't work correctly on 766 * some MBs so don't use it. 767 */ 768 dscommand0 &= ~(USCBSIZE32|DPARCKEN); 769 dscommand0 |= CACHETHEN; 770 } 771 772 ahc_outb(ahc, DSCOMMAND0, dscommand0); 773 774 /* See if we have an SEEPROM and perform auto-term */ 775 check_extport(ahc, &sxfrctl1); 776 777 /* 778 * Take the LED out of diagnostic mode 779 */ 780 sblkctl = ahc_inb(ahc, SBLKCTL); 781 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 782 783 /* 784 * I don't know where this is set in the SEEPROM or by the 785 * BIOS, so we default to 100% on Ultra or slower controllers 786 * and 75% on ULTRA2 controllers. 787 */ 788 if ((ahc->features & AHC_ULTRA2) != 0) { 789 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 790 } else { 791 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 792 } 793 794 if (ahc->flags & AHC_USEDEFAULTS) { 795 /* 796 * PCI Adapter default setup 797 * Should only be used if the adapter does not have 798 * an SEEPROM. 799 */ 800 /* See if someone else set us up already */ 801 if (scsiseq != 0) { 802 printf("%s: Using left over BIOS settings\n", 803 ahc_name(ahc)); 804 ahc->flags &= ~AHC_USEDEFAULTS; 805 } else { 806 /* 807 * Assume only one connector and always turn 808 * on termination. 809 */ 810 our_id = 0x07; 811 sxfrctl1 = STPWEN; 812 } 813 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 814 815 ahc->our_id = our_id; 816 } 817 } 818 819 /* 820 * Take a look to see if we have external SRAM. 821 * We currently do not attempt to use SRAM that is 822 * shared among multiple controllers. 823 */ 824 ahc_probe_ext_scbram(ahc); 825 826 827 printf("%s: %s ", ahc_name(ahc), 828 ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); 829 830 /* 831 * Record our termination setting for the 832 * generic initialization routine. 833 */ 834 if ((sxfrctl1 & STPWEN) != 0) 835 ahc->flags |= AHC_TERM_ENB_A; 836 837 if (ahc_init(ahc)) { 838 ahc_free(ahc); 839 return; 840 } 841 842 ahc_attach(ahc); 843 } 844 845 /* 846 * Test for the presense of external sram in an 847 * "unshared" configuration. 848 */ 849 static int 850 ahc_ext_scbram_present(struct ahc_softc *ahc) 851 { 852 int ramps; 853 int single_user; 854 pcireg_t devconfig; 855 struct ahc_pci_busdata *bd = ahc->bus_data; 856 857 devconfig = pci_conf_read(bd->pc, bd->tag, DEVCONFIG); 858 single_user = (devconfig & MPORTMODE) != 0; 859 860 if ((ahc->features & AHC_ULTRA2) != 0) 861 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 862 else if ((ahc->chip & AHC_CHIPID_MASK) >= AHC_AIC7870) 863 ramps = (devconfig & RAMPSM) != 0; 864 else 865 ramps = 0; 866 867 if (ramps && single_user) 868 return (1); 869 return (0); 870 } 871 872 /* 873 * Enable external scbram. 874 */ 875 static void 876 ahc_ext_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, int fast) 877 { 878 pcireg_t devconfig; 879 struct ahc_pci_busdata *bd = ahc->bus_data; 880 881 if (ahc->features & AHC_MULTI_FUNC) { 882 /* 883 * Set the SCB Base addr (highest address bit) 884 * depending on which channel we are. 885 */ 886 ahc_outb(ahc, SCBBADDR, (u_int8_t)bd->func); 887 } 888 889 devconfig = pci_conf_read(bd->pc, bd->tag, DEVCONFIG); 890 if ((ahc->features & AHC_ULTRA2) != 0) { 891 u_int dscommand0; 892 893 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 894 if (enable) 895 dscommand0 &= ~INTSCBRAMSEL; 896 else 897 dscommand0 |= INTSCBRAMSEL; 898 ahc_outb(ahc, DSCOMMAND0, dscommand0); 899 } else { 900 if (fast) 901 devconfig &= ~EXTSCBTIME; 902 else 903 devconfig |= EXTSCBTIME; 904 if (enable) 905 devconfig &= ~SCBRAMSEL; 906 else 907 devconfig |= SCBRAMSEL; 908 } 909 if (pcheck) 910 devconfig |= EXTSCBPEN; 911 else 912 devconfig &= ~EXTSCBPEN; 913 914 pci_conf_write(bd->pc, bd->tag, DEVCONFIG, devconfig); 915 } 916 917 /* 918 * Take a look to see if we have external SRAM. 919 * We currently do not attempt to use SRAM that is 920 * shared among multiple controllers. 921 */ 922 static void 923 ahc_probe_ext_scbram(struct ahc_softc *ahc) 924 { 925 int num_scbs; 926 int test_num_scbs; 927 int enable; 928 int pcheck; 929 int fast; 930 931 if (ahc_ext_scbram_present(ahc) == 0) 932 return; 933 934 /* 935 * Probe for the best parameters to use. 936 */ 937 enable = FALSE; 938 pcheck = FALSE; 939 fast = FALSE; 940 ahc_ext_scbram_config(ahc, /*enable*/TRUE, pcheck, fast); 941 num_scbs = ahc_probe_scbs(ahc); 942 if (num_scbs == 0) { 943 /* The SRAM wasn't really present. */ 944 goto done; 945 } 946 enable = TRUE; 947 948 /* 949 * Clear any outstanding parity error 950 * and ensure that parity error reporting 951 * is enabled. 952 */ 953 ahc_outb(ahc, SEQCTL, 0); 954 ahc_outb(ahc, CLRINT, CLRPARERR); 955 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 956 957 /* Now see if we can do parity */ 958 ahc_ext_scbram_config(ahc, enable, /*pcheck*/TRUE, fast); 959 num_scbs = ahc_probe_scbs(ahc); 960 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 961 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 962 pcheck = TRUE; 963 964 /* Clear any resulting parity error */ 965 ahc_outb(ahc, CLRINT, CLRPARERR); 966 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 967 968 /* Now see if we can do fast timing */ 969 ahc_ext_scbram_config(ahc, enable, pcheck, /*fast*/TRUE); 970 test_num_scbs = ahc_probe_scbs(ahc); 971 if (test_num_scbs == num_scbs 972 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 973 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 974 fast = TRUE; 975 976 done: 977 /* 978 * Disable parity error reporting until we 979 * can load instruction ram. 980 */ 981 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 982 /* Clear any latched parity error */ 983 ahc_outb(ahc, CLRINT, CLRPARERR); 984 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 985 if (bootverbose && enable) { 986 printf("%s: External SRAM, %s access%s\n", 987 ahc_name(ahc), fast ? "fast" : "slow", 988 pcheck ? ", parity checking enabled" : ""); 989 990 } 991 ahc_ext_scbram_config(ahc, enable, pcheck, fast); 992 } 993 994 #define DPE PCI_STATUS_PARITY_DETECT 995 #define SSE PCI_STATUS_SPECIAL_ERROR 996 #define RMA PCI_STATUS_MASTER_ABORT 997 #define RTA PCI_STATUS_MASTER_TARGET_ABORT 998 #define STA PCI_STATUS_TARGET_TARGET_ABORT 999 #define DPR PCI_STATUS_PARITY_ERROR 1000 1001 int 1002 ahc_pci_intr(struct ahc_softc *ahc) 1003 { 1004 pcireg_t status1; 1005 struct ahc_pci_busdata *bd = ahc->bus_data; 1006 1007 if ((ahc_inb(ahc, ERROR) & PCIERRSTAT) == 0) 1008 return 0; 1009 1010 status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 1011 1012 if (status1 & DPE) { 1013 printf("%s: Data Parity Error Detected during address " 1014 "or write data phase\n", ahc_name(ahc)); 1015 } 1016 if (status1 & SSE) { 1017 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1018 } 1019 if (status1 & RMA) { 1020 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1021 } 1022 if (status1 & RTA) { 1023 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1024 } 1025 if (status1 & STA) { 1026 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1027 } 1028 if (status1 & DPR) { 1029 printf("%s: Data Parity Error has been reported via PERR#\n", 1030 ahc_name(ahc)); 1031 } 1032 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1033 printf("%s: Latched PCIERR interrupt with " 1034 "no status bits set\n", ahc_name(ahc)); 1035 } 1036 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, status1); 1037 1038 if (status1 & (DPR|RMA|RTA)) { 1039 ahc_outb(ahc, CLRINT, CLRPARERR); 1040 } 1041 1042 return 1; 1043 } 1044 1045 static int 1046 ahc_aic7850_setup(struct pci_attach_args *pa, char *channel, 1047 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1048 { 1049 *channel = 'A'; 1050 *chip = AHC_AIC7850; 1051 *features = AHC_AIC7850_FE; 1052 return (0); 1053 } 1054 1055 static int 1056 ahc_aic7855_setup(struct pci_attach_args *pa, char *channel, 1057 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1058 { 1059 *channel = 'A'; 1060 *chip = AHC_AIC7855; 1061 *features = AHC_AIC7855_FE; 1062 return (0); 1063 } 1064 1065 static int 1066 ahc_aic7859_setup(struct pci_attach_args *pa, char *channel, 1067 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1068 { 1069 *channel = 'A'; 1070 *chip = AHC_AIC7859; 1071 *features = AHC_AIC7859_FE; 1072 return (0); 1073 } 1074 1075 static int 1076 ahc_aic7860_setup(struct pci_attach_args *pa, char *channel, 1077 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1078 { 1079 *channel = 'A'; 1080 *chip = AHC_AIC7860; 1081 *features = AHC_AIC7860_FE; 1082 return (0); 1083 } 1084 1085 static int 1086 ahc_aic7870_setup(struct pci_attach_args *pa, char *channel, 1087 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1088 { 1089 *channel = 'A'; 1090 *chip = AHC_AIC7870; 1091 *features = AHC_AIC7870_FE; 1092 return (0); 1093 } 1094 1095 static int 1096 ahc_aha394X_setup(struct pci_attach_args *pa, char *channel, 1097 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1098 { 1099 int error; 1100 1101 error = ahc_aic7870_setup(pa, channel, chip, features, flags); 1102 if (error == 0) 1103 error = ahc_aha394XX_setup(pa, channel, chip, features, flags); 1104 return (error); 1105 } 1106 1107 static int 1108 ahc_aha398X_setup(struct pci_attach_args *pa, char *channel, 1109 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1110 { 1111 int error; 1112 1113 error = ahc_aic7870_setup(pa, channel, chip, features, flags); 1114 if (error == 0) 1115 error = ahc_aha398XX_setup(pa, channel, chip, features, flags); 1116 return (error); 1117 } 1118 1119 static int 1120 ahc_aic7880_setup(struct pci_attach_args *pa, char *channel, 1121 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1122 { 1123 *channel = 'A'; 1124 *chip = AHC_AIC7880; 1125 *features = AHC_AIC7880_FE; 1126 return (0); 1127 } 1128 1129 static int 1130 ahc_2940Pro_setup(struct pci_attach_args *pa, char *channel, 1131 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1132 { 1133 int error; 1134 1135 *flags |= AHC_INT50_SPEEDFLEX; 1136 error = ahc_aic7880_setup(pa, channel, chip, features, flags); 1137 return (0); 1138 } 1139 1140 static int 1141 ahc_aha394XU_setup(struct pci_attach_args *pa, char *channel, 1142 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1143 { 1144 int error; 1145 1146 error = ahc_aic7880_setup(pa, channel, chip, features, flags); 1147 if (error == 0) 1148 error = ahc_aha394XX_setup(pa, channel, chip, features, flags); 1149 return (error); 1150 } 1151 1152 static int 1153 ahc_aha398XU_setup(struct pci_attach_args *pa, char *channel, 1154 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1155 { 1156 int error; 1157 1158 error = ahc_aic7880_setup(pa, channel, chip, features, flags); 1159 if (error == 0) 1160 error = ahc_aha398XX_setup(pa, channel, chip, features, flags); 1161 return (error); 1162 } 1163 1164 static int 1165 ahc_aic7890_setup(struct pci_attach_args *pa, char *channel, 1166 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1167 { 1168 *channel = 'A'; 1169 *chip = AHC_AIC7890; 1170 *features = AHC_AIC7890_FE; 1171 *flags |= AHC_NEWEEPROM_FMT; 1172 return (0); 1173 } 1174 1175 static int 1176 ahc_aic7892_setup(struct pci_attach_args *pa, char *channel, 1177 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1178 { 1179 *channel = 'A'; 1180 *chip = AHC_AIC7892; 1181 *features = AHC_AIC7892_FE; 1182 *flags |= AHC_NEWEEPROM_FMT; 1183 return (0); 1184 } 1185 1186 static int 1187 ahc_aic7895_setup(struct pci_attach_args *pa, char *channel, 1188 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1189 { 1190 pcireg_t devconfig; 1191 1192 *channel = pa->pa_function == 1 ? 'B' : 'A'; 1193 *chip = AHC_AIC7895; 1194 /* The 'C' revision of the aic7895 has a few additional features */ 1195 if (PCI_REVISION(pa->pa_class) >= 4) 1196 *features = AHC_AIC7895C_FE; 1197 else 1198 *features = AHC_AIC7895_FE; 1199 *flags |= AHC_NEWEEPROM_FMT; 1200 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 1201 devconfig &= ~SCBSIZE32; 1202 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); 1203 return (0); 1204 } 1205 1206 static int 1207 ahc_aic7896_setup(struct pci_attach_args *pa, char *channel, 1208 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1209 { 1210 *channel = pa->pa_function == 1 ? 'B' : 'A'; 1211 *chip = AHC_AIC7896; 1212 *features = AHC_AIC7896_FE; 1213 *flags |= AHC_NEWEEPROM_FMT; 1214 return (0); 1215 } 1216 1217 static int 1218 ahc_aic7899_setup(struct pci_attach_args *pa, char *channel, 1219 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1220 { 1221 *channel = pa->pa_function == 1 ? 'B' : 'A'; 1222 *chip = AHC_AIC7899; 1223 *features = AHC_AIC7899_FE; 1224 *flags |= AHC_NEWEEPROM_FMT; 1225 return (0); 1226 } 1227 1228 static int 1229 ahc_raid_setup(struct pci_attach_args *pa, char *channel, 1230 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1231 { 1232 printf("RAID functionality unsupported\n"); 1233 return (ENXIO); 1234 } 1235 1236 static int 1237 ahc_aha394XX_setup(struct pci_attach_args *pa, char *channel, 1238 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1239 { 1240 switch (pa->pa_device) { 1241 case AHC_394X_SLOT_CHANNEL_A: 1242 *channel = 'A'; 1243 break; 1244 case AHC_394X_SLOT_CHANNEL_B: 1245 *channel = 'B'; 1246 break; 1247 default: 1248 printf("adapter at unexpected slot %d\n" 1249 "unable to map to a channel\n", 1250 pa->pa_device); 1251 *channel = 'A'; 1252 } 1253 return (0); 1254 } 1255 1256 static int 1257 ahc_aha398XX_setup(struct pci_attach_args *pa, char *channel, 1258 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1259 { 1260 switch (pa->pa_device) { 1261 case AHC_398X_SLOT_CHANNEL_A: 1262 *channel = 'A'; 1263 break; 1264 case AHC_398X_SLOT_CHANNEL_B: 1265 *channel = 'B'; 1266 break; 1267 case AHC_398X_SLOT_CHANNEL_C: 1268 *channel = 'C'; 1269 break; 1270 default: 1271 printf("adapter at unexpected slot %d\n" 1272 "unable to map to a channel\n", 1273 pa->pa_device); 1274 *channel = 'A'; 1275 } 1276 *flags |= AHC_LARGE_SEEPROM; 1277 return (0); 1278 } 1279
Indexes created Wed Oct 01 19:09:53 GMT 2025