ahc_pci.c revision 1.26
1 /* $NetBSD: ahc_pci.c,v 1.26 2000/09/04 20:21:30 soren Exp $ */ 2 3 /* 4 * Product specific probe and attach routines for: 5 * 3940, 2940, aic7895, aic7890, aic7880, 6 * aic7870, aic7860 and aic7850 SCSI controllers 7 * 8 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * Alternatively, this software may be distributed under the terms of the 21 * the GNU Public License ("GPL"). 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/aic7xxx/ahc_pci.c,v 1.28 2000/02/09 21:00:22 gibbs Exp $ 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/device.h> 44 45 #include <machine/bus.h> 46 #include <machine/intr.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 51 /* XXXX some i386 on-board chips act weird when memory-mapped */ 52 #ifndef __i386__ 53 #define AHC_ALLOW_MEMIO 54 #endif 55 56 #define AHC_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 57 #define AHC_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 58 59 #include <dev/scsipi/scsi_all.h> 60 #include <dev/scsipi/scsipi_all.h> 61 #include <dev/scsipi/scsiconf.h> 62 63 #include <dev/ic/aic7xxxvar.h> 64 #include <dev/ic/smc93cx6var.h> 65 66 #include <dev/microcode/aic7xxx/aic7xxx_reg.h> 67 68 #ifdef DEBUG 69 #define bootverbose 1 70 #else 71 #define bootverbose 1 72 #endif 73 74 struct ahc_pci_busdata { 75 pci_chipset_tag_t pc; 76 pcitag_t tag; 77 u_int dev; 78 u_int func; 79 }; 80 81 static __inline u_int64_t 82 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 83 { 84 u_int64_t id; 85 86 id = subvendor 87 | (subdevice << 16) 88 | ((u_int64_t)vendor << 32) 89 | ((u_int64_t)device << 48); 90 91 return (id); 92 } 93 94 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 95 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 96 #define ID_AIC7850 0x5078900400000000ull 97 #define ID_AHA_2910_15_20_30C 0x5078900478509004ull 98 #define ID_AIC7855 0x5578900400000000ull 99 #define ID_AIC7859 0x3860900400000000ull 100 #define ID_AHA_2930CU 0x3860900438699004ull 101 #define ID_AIC7860 0x6078900400000000ull 102 #define ID_AIC7860C 0x6078900478609004ull 103 #define ID_AHA_2940AU_0 0x6178900400000000ull 104 #define ID_AHA_2940AU_1 0x6178900478619004ull 105 #define ID_AHA_2940AU_CN 0x2178900478219004ull 106 #define ID_AHA_2930C_VAR 0x6038900438689004ull 107 108 #define ID_AIC7870 0x7078900400000000ull 109 #define ID_AHA_2940 0x7178900400000000ull 110 #define ID_AHA_3940 0x7278900400000000ull 111 #define ID_AHA_398X 0x7378900400000000ull 112 #define ID_AHA_2944 0x7478900400000000ull 113 #define ID_AHA_3944 0x7578900400000000ull 114 115 #define ID_AIC7880 0x8078900400000000ull 116 #define ID_AIC7880_B 0x8078900478809004ull 117 #define ID_AHA_2940U 0x8178900400000000ull 118 #define ID_AHA_3940U 0x8278900400000000ull 119 #define ID_AHA_2944U 0x8478900400000000ull 120 #define ID_AHA_3944U 0x8578900400000000ull 121 #define ID_AHA_398XU 0x8378900400000000ull 122 #define ID_AHA_4944U 0x8678900400000000ull 123 #define ID_AHA_2940UB 0x8178900478819004ull 124 #define ID_AHA_2930U 0x8878900478889004ull 125 #define ID_AHA_2940U_PRO 0x8778900478879004ull 126 #define ID_AHA_2940U_CN 0x0078900478009004ull 127 128 #define ID_AIC7895 0x7895900478959004ull 129 #define ID_AIC7895_RAID_PORT 0x7893900478939004ull 130 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 131 #define ID_AHA_3940AU 0x7895900478929004ull 132 #define ID_AHA_3944AU 0x7895900478949004ull 133 134 #define ID_AIC7890 0x001F9005000F9005ull 135 #define ID_AAA_131U2 0x0013900500039005ull 136 #define ID_AHA_2930U2 0x0011900501819005ull 137 #define ID_AHA_2940U2B 0x00109005A1009005ull 138 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 139 #define ID_AHA_2940U2 0x00109005A1809005ull 140 #define ID_AHA_2950U2B 0x00109005E1009005ull 141 142 #define ID_AIC7892 0x008F9005FFFF9005ull 143 #define ID_AHA_29160 0x00809005E2A09005ull 144 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 145 #define ID_AHA_29160N 0x0080900562A09005ull 146 #define ID_AHA_29160B 0x00809005E2209005ull 147 #define ID_AHA_19160B 0x0081900562A19005ull 148 149 #define ID_AIC7896 0x005F9005FFFF9005ull 150 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 151 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 152 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 153 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 154 155 #define ID_AIC7899 0x00CF9005FFFF9005ull 156 #define ID_AHA_3960D 0x00C09005F6209005ull /* AKA AHA-39160 */ 157 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 158 159 #define ID_AIC7810 0x1078900400000000ull 160 #define ID_AIC7815 0x7815900400000000ull 161 162 typedef int (ahc_device_setup_t)(struct pci_attach_args *, char *, 163 ahc_chip *, ahc_feature *, ahc_flag *); 164 165 static ahc_device_setup_t ahc_aic7850_setup; 166 static ahc_device_setup_t ahc_aic7855_setup; 167 static ahc_device_setup_t ahc_aic7859_setup; 168 static ahc_device_setup_t ahc_aic7860_setup; 169 static ahc_device_setup_t ahc_aic7870_setup; 170 static ahc_device_setup_t ahc_aha394X_setup; 171 static ahc_device_setup_t ahc_aha398X_setup; 172 static ahc_device_setup_t ahc_aic7880_setup; 173 static ahc_device_setup_t ahc_2940Pro_setup; 174 static ahc_device_setup_t ahc_aha394XU_setup; 175 static ahc_device_setup_t ahc_aha398XU_setup; 176 static ahc_device_setup_t ahc_aic7890_setup; 177 static ahc_device_setup_t ahc_aic7892_setup; 178 static ahc_device_setup_t ahc_aic7895_setup; 179 static ahc_device_setup_t ahc_aic7896_setup; 180 static ahc_device_setup_t ahc_aic7899_setup; 181 static ahc_device_setup_t ahc_raid_setup; 182 static ahc_device_setup_t ahc_aha394XX_setup; 183 static ahc_device_setup_t ahc_aha398XX_setup; 184 185 struct ahc_pci_identity { 186 u_int64_t full_id; 187 u_int64_t id_mask; 188 char *name; 189 ahc_device_setup_t *setup; 190 }; 191 192 struct ahc_pci_identity ahc_pci_ident_table [] = 193 { 194 /* aic7850 based controllers */ 195 { 196 ID_AHA_2910_15_20_30C, 197 ID_ALL_MASK, 198 "Adaptec 2910/15/20/30C SCSI adapter", 199 ahc_aic7850_setup 200 }, 201 /* aic7859 based controllers */ 202 { 203 ID_AHA_2930CU, 204 ID_ALL_MASK, 205 "Adaptec 2930CU SCSI adapter", 206 ahc_aic7859_setup 207 }, 208 /* aic7860 based controllers */ 209 { 210 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 211 ID_DEV_VENDOR_MASK, 212 "Adaptec 2940A Ultra SCSI adapter", 213 ahc_aic7860_setup 214 }, 215 { 216 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 217 ID_DEV_VENDOR_MASK, 218 "Adaptec 2940A/CN Ultra SCSI adapter", 219 ahc_aic7860_setup 220 }, 221 { 222 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 223 ID_DEV_VENDOR_MASK, 224 "Adaptec 2930C SCSI adapter (VAR)", 225 ahc_aic7860_setup 226 }, 227 /* aic7870 based controllers */ 228 { 229 ID_AHA_2940, 230 ID_ALL_MASK, 231 "Adaptec 2940 SCSI adapter", 232 ahc_aic7870_setup 233 }, 234 { 235 ID_AHA_3940, 236 ID_ALL_MASK, 237 "Adaptec 3940 SCSI adapter", 238 ahc_aha394X_setup 239 }, 240 { 241 ID_AHA_398X, 242 ID_ALL_MASK, 243 "Adaptec 398X SCSI RAID adapter", 244 ahc_aha398X_setup 245 }, 246 { 247 ID_AHA_2944, 248 ID_ALL_MASK, 249 "Adaptec 2944 SCSI adapter", 250 ahc_aic7870_setup 251 }, 252 { 253 ID_AHA_3944, 254 ID_ALL_MASK, 255 "Adaptec 3944 SCSI adapter", 256 ahc_aha394X_setup 257 }, 258 /* aic7880 based controllers */ 259 { 260 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 261 ID_DEV_VENDOR_MASK, 262 "Adaptec 2940 Ultra SCSI adapter", 263 ahc_aic7880_setup 264 }, 265 { 266 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 267 ID_DEV_VENDOR_MASK, 268 "Adaptec 3940 Ultra SCSI adapter", 269 ahc_aha394XU_setup 270 }, 271 { 272 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 273 ID_DEV_VENDOR_MASK, 274 "Adaptec 2944 Ultra SCSI adapter", 275 ahc_aic7880_setup 276 }, 277 { 278 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 279 ID_DEV_VENDOR_MASK, 280 "Adaptec 3944 Ultra SCSI adapter", 281 ahc_aha394XU_setup 282 }, 283 { 284 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 285 ID_DEV_VENDOR_MASK, 286 "Adaptec 398X Ultra SCSI RAID adapter", 287 ahc_aha398XU_setup 288 }, 289 { 290 /* 291 * XXX Don't know the slot numbers 292 * so we can't identify channels 293 */ 294 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 295 ID_DEV_VENDOR_MASK, 296 "Adaptec 4944 Ultra SCSI adapter", 297 ahc_aic7880_setup 298 }, 299 { 300 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 301 ID_DEV_VENDOR_MASK, 302 "Adaptec 2930 Ultra SCSI adapter", 303 ahc_aic7880_setup 304 }, 305 { 306 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 307 ID_DEV_VENDOR_MASK, 308 "Adaptec 2940 Pro Ultra SCSI adapter", 309 ahc_2940Pro_setup 310 }, 311 { 312 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 313 ID_DEV_VENDOR_MASK, 314 "Adaptec 2940/CN Ultra SCSI adapter", 315 ahc_aic7880_setup 316 }, 317 /* aic7890 based controllers */ 318 { 319 ID_AHA_2930U2, 320 ID_ALL_MASK, 321 "Adaptec 2930 Ultra2 SCSI adapter", 322 ahc_aic7890_setup 323 }, 324 { 325 ID_AHA_2940U2B, 326 ID_ALL_MASK, 327 "Adaptec 2940B Ultra2 SCSI adapter", 328 ahc_aic7890_setup 329 }, 330 { 331 ID_AHA_2940U2_OEM, 332 ID_ALL_MASK, 333 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 334 ahc_aic7890_setup 335 }, 336 { 337 ID_AHA_2940U2, 338 ID_ALL_MASK, 339 "Adaptec 2940 Ultra2 SCSI adapter", 340 ahc_aic7890_setup 341 }, 342 { 343 ID_AHA_2950U2B, 344 ID_ALL_MASK, 345 "Adaptec 2950 Ultra2 SCSI adapter", 346 ahc_aic7890_setup 347 }, 348 { 349 ID_AAA_131U2, 350 ID_ALL_MASK, 351 "Adaptec AAA-131 Ultra2 RAID adapter", 352 ahc_aic7890_setup 353 }, 354 /* aic7892 based controllers */ 355 { 356 ID_AHA_29160, 357 ID_ALL_MASK, 358 "Adaptec 29160 Ultra160 SCSI adapter", 359 ahc_aic7892_setup 360 }, 361 { 362 ID_AHA_29160_CPQ, 363 ID_ALL_MASK, 364 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 365 ahc_aic7892_setup 366 }, 367 { 368 ID_AHA_29160N, 369 ID_ALL_MASK, 370 "Adaptec 29160N Ultra160 SCSI adapter", 371 ahc_aic7892_setup 372 }, 373 { 374 ID_AHA_29160B, 375 ID_ALL_MASK, 376 "Adaptec 29160B Ultra160 SCSI adapter", 377 ahc_aic7892_setup 378 }, 379 { 380 ID_AHA_19160B, 381 ID_ALL_MASK, 382 "Adaptec 19160B Ultra160 SCSI adapter", 383 ahc_aic7892_setup 384 }, 385 /* aic7895 based controllers */ 386 { 387 ID_AHA_2940U_DUAL, 388 ID_ALL_MASK, 389 "Adaptec 2940/DUAL Ultra SCSI adapter", 390 ahc_aic7895_setup 391 }, 392 { 393 ID_AHA_3940AU, 394 ID_ALL_MASK, 395 "Adaptec 3940A Ultra SCSI adapter", 396 ahc_aic7895_setup 397 }, 398 { 399 ID_AHA_3944AU, 400 ID_ALL_MASK, 401 "Adaptec 3944A Ultra SCSI adapter", 402 ahc_aic7895_setup 403 }, 404 /* aic7896/97 based controllers */ 405 { 406 ID_AHA_3950U2B_0, 407 ID_ALL_MASK, 408 "Adaptec 3950B Ultra2 SCSI adapter", 409 ahc_aic7896_setup 410 }, 411 { 412 ID_AHA_3950U2B_1, 413 ID_ALL_MASK, 414 "Adaptec 3950B Ultra2 SCSI adapter", 415 ahc_aic7896_setup 416 }, 417 { 418 ID_AHA_3950U2D_0, 419 ID_ALL_MASK, 420 "Adaptec 3950D Ultra2 SCSI adapter", 421 ahc_aic7896_setup 422 }, 423 { 424 ID_AHA_3950U2D_1, 425 ID_ALL_MASK, 426 "Adaptec 3950D Ultra2 SCSI adapter", 427 ahc_aic7896_setup 428 }, 429 /* aic7899 based controllers */ 430 { 431 ID_AHA_3960D, 432 ID_ALL_MASK, 433 "Adaptec 3960D Ultra160 SCSI adapter", 434 ahc_aic7899_setup 435 }, 436 { 437 ID_AHA_3960D_CPQ, 438 ID_ALL_MASK, 439 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 440 ahc_aic7899_setup 441 }, 442 /* Generic chip probes for devices we don't know 'exactly' */ 443 { 444 ID_AIC7850 & ID_DEV_VENDOR_MASK, 445 ID_DEV_VENDOR_MASK, 446 "Adaptec aic7850 SCSI adapter", 447 ahc_aic7850_setup 448 }, 449 { 450 ID_AIC7855 & ID_DEV_VENDOR_MASK, 451 ID_DEV_VENDOR_MASK, 452 "Adaptec aic7855 SCSI adapter", 453 ahc_aic7855_setup 454 }, 455 { 456 ID_AIC7859 & ID_DEV_VENDOR_MASK, 457 ID_DEV_VENDOR_MASK, 458 "Adaptec aic7859 SCSI adapter", 459 ahc_aic7859_setup 460 }, 461 { 462 ID_AIC7860 & ID_DEV_VENDOR_MASK, 463 ID_DEV_VENDOR_MASK, 464 "Adaptec aic7860 SCSI adapter", 465 ahc_aic7860_setup 466 }, 467 { 468 ID_AIC7870 & ID_DEV_VENDOR_MASK, 469 ID_DEV_VENDOR_MASK, 470 "Adaptec aic7870 SCSI adapter", 471 ahc_aic7870_setup 472 }, 473 { 474 ID_AIC7880 & ID_DEV_VENDOR_MASK, 475 ID_DEV_VENDOR_MASK, 476 "Adaptec aic7880 Ultra SCSI adapter", 477 ahc_aic7880_setup 478 }, 479 { 480 ID_AIC7890 & ID_DEV_VENDOR_MASK, 481 ID_DEV_VENDOR_MASK, 482 "Adaptec aic7890/91 Ultra2 SCSI adapter", 483 ahc_aic7890_setup 484 }, 485 { 486 ID_AIC7892 & ID_DEV_VENDOR_MASK, 487 ID_DEV_VENDOR_MASK, 488 "Adaptec aic7892 Ultra160 SCSI adapter", 489 ahc_aic7892_setup 490 }, 491 { 492 ID_AIC7895 & ID_DEV_VENDOR_MASK, 493 ID_DEV_VENDOR_MASK, 494 "Adaptec aic7895 Ultra SCSI adapter", 495 ahc_aic7895_setup 496 }, 497 { 498 ID_AIC7895_RAID_PORT & ID_DEV_VENDOR_MASK, 499 ID_DEV_VENDOR_MASK, 500 "Adaptec aic7895 Ultra SCSI adapter (RAID PORT)", 501 ahc_aic7895_setup 502 }, 503 { 504 ID_AIC7896 & ID_DEV_VENDOR_MASK, 505 ID_DEV_VENDOR_MASK, 506 "Adaptec aic7896/97 Ultra2 SCSI adapter", 507 ahc_aic7896_setup 508 }, 509 { 510 ID_AIC7899 & ID_DEV_VENDOR_MASK, 511 ID_DEV_VENDOR_MASK, 512 "Adaptec aic7899 Ultra160 SCSI adapter", 513 ahc_aic7899_setup 514 }, 515 { 516 ID_AIC7810 & ID_DEV_VENDOR_MASK, 517 ID_DEV_VENDOR_MASK, 518 "Adaptec aic7810 RAID memory controller", 519 ahc_raid_setup 520 }, 521 { 522 ID_AIC7815 & ID_DEV_VENDOR_MASK, 523 ID_DEV_VENDOR_MASK, 524 "Adaptec aic7815 RAID memory controller", 525 ahc_raid_setup 526 } 527 }; 528 529 static const int ahc_num_pci_devs = 530 sizeof(ahc_pci_ident_table) / sizeof(*ahc_pci_ident_table); 531 532 #define AHC_394X_SLOT_CHANNEL_A 4 533 #define AHC_394X_SLOT_CHANNEL_B 5 534 535 #define AHC_398X_SLOT_CHANNEL_A 4 536 #define AHC_398X_SLOT_CHANNEL_B 8 537 #define AHC_398X_SLOT_CHANNEL_C 12 538 539 #define DEVCONFIG 0x40 540 #define SCBSIZE32 0x00010000 /* aic789X only */ 541 #define MPORTMODE 0x00000400 /* aic7870 only */ 542 #define RAMPSM 0x00000200 /* aic7870 only */ 543 #define VOLSENSE 0x00000100 544 #define SCBRAMSEL 0x00000080 545 #define MRDCEN 0x00000040 546 #define EXTSCBTIME 0x00000020 /* aic7870 only */ 547 #define EXTSCBPEN 0x00000010 /* aic7870 only */ 548 #define BERREN 0x00000008 549 #define DACEN 0x00000004 550 #define STPWLEVEL 0x00000002 551 #define DIFACTNEGEN 0x00000001 /* aic7870 only */ 552 553 #define CSIZE_LATTIME 0x0c 554 #define CACHESIZE 0x0000003f /* only 5 bits */ 555 #define LATTIME 0x0000ff00 556 557 static struct ahc_pci_identity *ahc_find_pci_device(pcireg_t, pcireg_t); 558 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 559 static void ahc_ext_scbram_config(struct ahc_softc *ahc, int enable, 560 int pcheck, int fast); 561 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 562 563 int ahc_pci_probe __P((struct device *, struct cfdata *, void *)); 564 void ahc_pci_attach __P((struct device *, struct device *, void *)); 565 566 /* Exported for use in the ahc_intr routine */ 567 int ahc_pci_intr(struct ahc_softc *ahc); 568 569 struct cfattach ahc_pci_ca = { 570 sizeof(struct ahc_softc), ahc_pci_probe, ahc_pci_attach 571 }; 572 573 static struct ahc_pci_identity * 574 ahc_find_pci_device(id, subid) 575 pcireg_t id, subid; 576 { 577 u_int64_t full_id; 578 struct ahc_pci_identity *entry; 579 u_int i; 580 581 full_id = ahc_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 582 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 583 584 for (i = 0; i < ahc_num_pci_devs; i++) { 585 entry = &ahc_pci_ident_table[i]; 586 if (entry->full_id == (full_id & entry->id_mask)) 587 return (entry); 588 } 589 return (NULL); 590 } 591 592 int 593 ahc_pci_probe(parent, match, aux) 594 struct device *parent; 595 struct cfdata *match; 596 void *aux; 597 { 598 struct pci_attach_args *pa = aux; 599 struct ahc_pci_identity *entry; 600 pcireg_t subid; 601 602 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 603 entry = ahc_find_pci_device(pa->pa_id, subid); 604 return entry != NULL ? 1 : 0; 605 } 606 607 void 608 ahc_pci_attach(parent, self, aux) 609 struct device *parent, *self; 610 void *aux; 611 { 612 struct pci_attach_args *pa = aux; 613 struct ahc_pci_identity *entry; 614 struct ahc_softc *ahc = (void *)self; 615 pcireg_t command; 616 ahc_chip ahc_t = AHC_NONE; 617 ahc_feature ahc_fe = AHC_FENONE; 618 ahc_flag ahc_f = AHC_FNONE; 619 u_int our_id = 0; 620 u_int sxfrctl1; 621 u_int scsiseq; 622 int error; 623 char channel; 624 pcireg_t subid; 625 int ioh_valid, memh_valid; 626 bus_space_tag_t st, iot; 627 bus_space_handle_t sh, ioh; 628 #ifdef AHC_ALLOW_MEMIO 629 bus_space_tag_t memt; 630 bus_space_handle_t memh; 631 pcireg_t memtype; 632 #endif 633 pci_intr_handle_t ih; 634 const char *intrstr; 635 struct ahc_pci_busdata *bd; 636 637 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 638 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 639 entry = ahc_find_pci_device(pa->pa_id, subid); 640 if (entry == NULL) 641 return; 642 error = entry->setup(pa, &channel, &ahc_t, &ahc_fe, &ahc_f); 643 if (error != 0) 644 return; 645 646 ioh_valid = memh_valid = 0; 647 648 #ifdef AHC_ALLOW_MEMIO 649 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHC_PCI_MEMADDR); 650 switch (memtype) { 651 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 652 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 653 memh_valid = (pci_mapreg_map(pa, AHC_PCI_MEMADDR, 654 memtype, 0, &memt, &memh, NULL, NULL) == 0); 655 break; 656 default: 657 memh_valid = 0; 658 } 659 #endif 660 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_IOADDR, 661 PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, NULL, NULL) == 0); 662 663 if (ioh_valid) { 664 st = iot; 665 sh = ioh; 666 #ifdef AHC_ALLOW_MEMIO 667 } else if (memh_valid) { 668 st = memt; 669 sh = memh; 670 #endif 671 } else { 672 printf(": unable to map registers\n"); 673 return; 674 } 675 676 printf("\n"); 677 678 679 /* Ensure busmastering is enabled */ 680 command |= PCI_COMMAND_MASTER_ENABLE;; 681 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 682 683 /* On all PCI adapters, we allow SCB paging */ 684 ahc_f |= AHC_PAGESCBS; 685 if (ahc_alloc(ahc, sh, st, pa->pa_dmat, 686 ahc_t|AHC_PCI, ahc_fe, ahc_f) < 0) 687 return; 688 689 bd = malloc(sizeof (struct ahc_pci_busdata), M_DEVBUF, M_NOWAIT); 690 if (bd == NULL) { 691 printf(": unable to allocate bus-specific data\n"); 692 return; 693 } 694 695 bd->pc = pa->pa_pc; 696 bd->tag = pa->pa_tag; 697 bd->func = pa->pa_function; 698 bd->dev = pa->pa_device; 699 700 ahc->bus_data = bd; 701 ahc->bus_intr = ahc_pci_intr; 702 ahc->channel = channel; 703 704 /* Remeber how the card was setup in case there is no SEEPROM */ 705 ahc_outb(ahc, HCNTRL, ahc->pause); 706 if ((ahc->features & AHC_ULTRA2) != 0) 707 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 708 else 709 our_id = ahc_inb(ahc, SCSIID) & OID; 710 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 711 scsiseq = ahc_inb(ahc, SCSISEQ); 712 713 if (ahc_reset(ahc) != 0) { 714 /* Failed */ 715 ahc_free(ahc); 716 return; 717 } 718 719 if ((ahc->features & AHC_DT) != 0) { 720 u_int optionmode; 721 u_int sfunct; 722 723 /* Perform ALT-Mode Setup */ 724 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 725 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 726 optionmode = ahc_inb(ahc, OPTIONMODE); 727 printf("OptionMode = %x\n", optionmode); 728 ahc_outb(ahc, OPTIONMODE, OPTIONMODE_DEFAULTS); 729 /* Send CRC info in target mode every 4K */ 730 ahc_outb(ahc, TARGCRCCNT, 0); 731 ahc_outb(ahc, TARGCRCCNT + 1, 0x10); 732 ahc_outb(ahc, SFUNCT, sfunct); 733 734 /* Normal mode setup */ 735 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 736 |TARGCRCENDEN|TARGCRCCNTEN); 737 } 738 739 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 740 pa->pa_intrline, &ih)) { 741 printf("%s: couldn't map interrupt\n", ahc->sc_dev.dv_xname); 742 ahc_free(ahc); 743 return; 744 } 745 intrstr = pci_intr_string(pa->pa_pc, ih); 746 ahc->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahc_intr, ahc); 747 if (ahc->ih == NULL) { 748 printf("%s: couldn't establish interrupt", 749 ahc->sc_dev.dv_xname); 750 if (intrstr != NULL) 751 printf(" at %s", intrstr); 752 printf("\n"); 753 ahc_free(ahc); 754 return; 755 } 756 if (intrstr != NULL) 757 printf("%s: interrupting at %s\n", ahc->sc_dev.dv_xname, 758 intrstr); 759 760 /* 761 * Do aic7880/aic7870/aic7860/aic7850 specific initialization 762 */ 763 { 764 u_int8_t sblkctl; 765 u_int dscommand0; 766 767 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 768 dscommand0 |= MPARCKEN; 769 if ((ahc->features & AHC_ULTRA2) != 0) { 770 771 /* 772 * DPARCKEN doesn't work correctly on 773 * some MBs so don't use it. 774 */ 775 dscommand0 &= ~(USCBSIZE32|DPARCKEN); 776 dscommand0 |= CACHETHEN; 777 } 778 779 ahc_outb(ahc, DSCOMMAND0, dscommand0); 780 781 /* See if we have an SEEPROM and perform auto-term */ 782 check_extport(ahc, &sxfrctl1); 783 784 /* 785 * Take the LED out of diagnostic mode 786 */ 787 sblkctl = ahc_inb(ahc, SBLKCTL); 788 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 789 790 /* 791 * I don't know where this is set in the SEEPROM or by the 792 * BIOS, so we default to 100% on Ultra or slower controllers 793 * and 75% on ULTRA2 controllers. 794 */ 795 if ((ahc->features & AHC_ULTRA2) != 0) { 796 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 797 } else { 798 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 799 } 800 801 if (ahc->flags & AHC_USEDEFAULTS) { 802 /* 803 * PCI Adapter default setup 804 * Should only be used if the adapter does not have 805 * an SEEPROM. 806 */ 807 /* See if someone else set us up already */ 808 if (scsiseq != 0) { 809 printf("%s: Using left over BIOS settings\n", 810 ahc_name(ahc)); 811 ahc->flags &= ~AHC_USEDEFAULTS; 812 } else { 813 /* 814 * Assume only one connector and always turn 815 * on termination. 816 */ 817 our_id = 0x07; 818 sxfrctl1 = STPWEN; 819 } 820 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 821 822 ahc->our_id = our_id; 823 } 824 } 825 826 /* 827 * Take a look to see if we have external SRAM. 828 * We currently do not attempt to use SRAM that is 829 * shared among multiple controllers. 830 */ 831 ahc_probe_ext_scbram(ahc); 832 833 834 printf("%s: %s ", ahc_name(ahc), 835 ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); 836 837 /* 838 * Record our termination setting for the 839 * generic initialization routine. 840 */ 841 if ((sxfrctl1 & STPWEN) != 0) 842 ahc->flags |= AHC_TERM_ENB_A; 843 844 if (ahc_init(ahc)) { 845 ahc_free(ahc); 846 return; 847 } 848 849 ahc_attach(ahc); 850 } 851 852 /* 853 * Test for the presense of external sram in an 854 * "unshared" configuration. 855 */ 856 static int 857 ahc_ext_scbram_present(struct ahc_softc *ahc) 858 { 859 int ramps; 860 int single_user; 861 pcireg_t devconfig; 862 struct ahc_pci_busdata *bd = ahc->bus_data; 863 864 devconfig = pci_conf_read(bd->pc, bd->tag, DEVCONFIG); 865 single_user = (devconfig & MPORTMODE) != 0; 866 867 if ((ahc->features & AHC_ULTRA2) != 0) 868 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 869 else if ((ahc->chip & AHC_CHIPID_MASK) >= AHC_AIC7870) 870 ramps = (devconfig & RAMPSM) != 0; 871 else 872 ramps = 0; 873 874 if (ramps && single_user) 875 return (1); 876 return (0); 877 } 878 879 /* 880 * Enable external scbram. 881 */ 882 static void 883 ahc_ext_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, int fast) 884 { 885 pcireg_t devconfig; 886 struct ahc_pci_busdata *bd = ahc->bus_data; 887 888 if (ahc->features & AHC_MULTI_FUNC) { 889 /* 890 * Set the SCB Base addr (highest address bit) 891 * depending on which channel we are. 892 */ 893 ahc_outb(ahc, SCBBADDR, (u_int8_t)bd->func); 894 } 895 896 devconfig = pci_conf_read(bd->pc, bd->tag, DEVCONFIG); 897 if ((ahc->features & AHC_ULTRA2) != 0) { 898 u_int dscommand0; 899 900 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 901 if (enable) 902 dscommand0 &= ~INTSCBRAMSEL; 903 else 904 dscommand0 |= INTSCBRAMSEL; 905 ahc_outb(ahc, DSCOMMAND0, dscommand0); 906 } else { 907 if (fast) 908 devconfig &= ~EXTSCBTIME; 909 else 910 devconfig |= EXTSCBTIME; 911 if (enable) 912 devconfig &= ~SCBRAMSEL; 913 else 914 devconfig |= SCBRAMSEL; 915 } 916 if (pcheck) 917 devconfig |= EXTSCBPEN; 918 else 919 devconfig &= ~EXTSCBPEN; 920 921 pci_conf_write(bd->pc, bd->tag, DEVCONFIG, devconfig); 922 } 923 924 /* 925 * Take a look to see if we have external SRAM. 926 * We currently do not attempt to use SRAM that is 927 * shared among multiple controllers. 928 */ 929 static void 930 ahc_probe_ext_scbram(struct ahc_softc *ahc) 931 { 932 int num_scbs; 933 int test_num_scbs; 934 int enable; 935 int pcheck; 936 int fast; 937 938 if (ahc_ext_scbram_present(ahc) == 0) 939 return; 940 941 /* 942 * Probe for the best parameters to use. 943 */ 944 enable = FALSE; 945 pcheck = FALSE; 946 fast = FALSE; 947 ahc_ext_scbram_config(ahc, /*enable*/TRUE, pcheck, fast); 948 num_scbs = ahc_probe_scbs(ahc); 949 if (num_scbs == 0) { 950 /* The SRAM wasn't really present. */ 951 goto done; 952 } 953 enable = TRUE; 954 955 /* 956 * Clear any outstanding parity error 957 * and ensure that parity error reporting 958 * is enabled. 959 */ 960 ahc_outb(ahc, SEQCTL, 0); 961 ahc_outb(ahc, CLRINT, CLRPARERR); 962 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 963 964 /* Now see if we can do parity */ 965 ahc_ext_scbram_config(ahc, enable, /*pcheck*/TRUE, fast); 966 num_scbs = ahc_probe_scbs(ahc); 967 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 968 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 969 pcheck = TRUE; 970 971 /* Clear any resulting parity error */ 972 ahc_outb(ahc, CLRINT, CLRPARERR); 973 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 974 975 /* Now see if we can do fast timing */ 976 ahc_ext_scbram_config(ahc, enable, pcheck, /*fast*/TRUE); 977 test_num_scbs = ahc_probe_scbs(ahc); 978 if (test_num_scbs == num_scbs 979 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 980 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 981 fast = TRUE; 982 983 done: 984 /* 985 * Disable parity error reporting until we 986 * can load instruction ram. 987 */ 988 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 989 /* Clear any latched parity error */ 990 ahc_outb(ahc, CLRINT, CLRPARERR); 991 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 992 if (bootverbose && enable) { 993 printf("%s: External SRAM, %s access%s\n", 994 ahc_name(ahc), fast ? "fast" : "slow", 995 pcheck ? ", parity checking enabled" : ""); 996 997 } 998 ahc_ext_scbram_config(ahc, enable, pcheck, fast); 999 } 1000 1001 #define DPE PCI_STATUS_PARITY_DETECT 1002 #define SSE PCI_STATUS_SPECIAL_ERROR 1003 #define RMA PCI_STATUS_MASTER_ABORT 1004 #define RTA PCI_STATUS_MASTER_TARGET_ABORT 1005 #define STA PCI_STATUS_TARGET_TARGET_ABORT 1006 #define DPR PCI_STATUS_PARITY_ERROR 1007 1008 int 1009 ahc_pci_intr(struct ahc_softc *ahc) 1010 { 1011 pcireg_t status1; 1012 struct ahc_pci_busdata *bd = ahc->bus_data; 1013 1014 if ((ahc_inb(ahc, ERROR) & PCIERRSTAT) == 0) 1015 return 0; 1016 1017 status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 1018 1019 if (status1 & DPE) { 1020 printf("%s: Data Parity Error Detected during address " 1021 "or write data phase\n", ahc_name(ahc)); 1022 } 1023 if (status1 & SSE) { 1024 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1025 } 1026 if (status1 & RMA) { 1027 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1028 } 1029 if (status1 & RTA) { 1030 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1031 } 1032 if (status1 & STA) { 1033 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1034 } 1035 if (status1 & DPR) { 1036 printf("%s: Data Parity Error has been reported via PERR#\n", 1037 ahc_name(ahc)); 1038 } 1039 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1040 printf("%s: Latched PCIERR interrupt with " 1041 "no status bits set\n", ahc_name(ahc)); 1042 } 1043 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, status1); 1044 1045 if (status1 & (DPR|RMA|RTA)) { 1046 ahc_outb(ahc, CLRINT, CLRPARERR); 1047 } 1048 1049 return 1; 1050 } 1051 1052 static int 1053 ahc_aic7850_setup(struct pci_attach_args *pa, char *channel, 1054 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1055 { 1056 *channel = 'A'; 1057 *chip = AHC_AIC7850; 1058 *features = AHC_AIC7850_FE; 1059 return (0); 1060 } 1061 1062 static int 1063 ahc_aic7855_setup(struct pci_attach_args *pa, char *channel, 1064 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1065 { 1066 *channel = 'A'; 1067 *chip = AHC_AIC7855; 1068 *features = AHC_AIC7855_FE; 1069 return (0); 1070 } 1071 1072 static int 1073 ahc_aic7859_setup(struct pci_attach_args *pa, char *channel, 1074 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1075 { 1076 *channel = 'A'; 1077 *chip = AHC_AIC7859; 1078 *features = AHC_AIC7859_FE; 1079 return (0); 1080 } 1081 1082 static int 1083 ahc_aic7860_setup(struct pci_attach_args *pa, char *channel, 1084 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1085 { 1086 *channel = 'A'; 1087 *chip = AHC_AIC7860; 1088 *features = AHC_AIC7860_FE; 1089 return (0); 1090 } 1091 1092 static int 1093 ahc_aic7870_setup(struct pci_attach_args *pa, char *channel, 1094 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1095 { 1096 *channel = 'A'; 1097 *chip = AHC_AIC7870; 1098 *features = AHC_AIC7870_FE; 1099 return (0); 1100 } 1101 1102 static int 1103 ahc_aha394X_setup(struct pci_attach_args *pa, char *channel, 1104 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1105 { 1106 int error; 1107 1108 error = ahc_aic7870_setup(pa, channel, chip, features, flags); 1109 if (error == 0) 1110 error = ahc_aha394XX_setup(pa, channel, chip, features, flags); 1111 return (error); 1112 } 1113 1114 static int 1115 ahc_aha398X_setup(struct pci_attach_args *pa, char *channel, 1116 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1117 { 1118 int error; 1119 1120 error = ahc_aic7870_setup(pa, channel, chip, features, flags); 1121 if (error == 0) 1122 error = ahc_aha398XX_setup(pa, channel, chip, features, flags); 1123 return (error); 1124 } 1125 1126 static int 1127 ahc_aic7880_setup(struct pci_attach_args *pa, char *channel, 1128 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1129 { 1130 *channel = 'A'; 1131 *chip = AHC_AIC7880; 1132 *features = AHC_AIC7880_FE; 1133 return (0); 1134 } 1135 1136 static int 1137 ahc_2940Pro_setup(struct pci_attach_args *pa, char *channel, 1138 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1139 { 1140 int error; 1141 1142 *flags |= AHC_INT50_SPEEDFLEX; 1143 error = ahc_aic7880_setup(pa, channel, chip, features, flags); 1144 return (0); 1145 } 1146 1147 static int 1148 ahc_aha394XU_setup(struct pci_attach_args *pa, char *channel, 1149 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1150 { 1151 int error; 1152 1153 error = ahc_aic7880_setup(pa, channel, chip, features, flags); 1154 if (error == 0) 1155 error = ahc_aha394XX_setup(pa, channel, chip, features, flags); 1156 return (error); 1157 } 1158 1159 static int 1160 ahc_aha398XU_setup(struct pci_attach_args *pa, char *channel, 1161 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1162 { 1163 int error; 1164 1165 error = ahc_aic7880_setup(pa, channel, chip, features, flags); 1166 if (error == 0) 1167 error = ahc_aha398XX_setup(pa, channel, chip, features, flags); 1168 return (error); 1169 } 1170 1171 static int 1172 ahc_aic7890_setup(struct pci_attach_args *pa, char *channel, 1173 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1174 { 1175 *channel = 'A'; 1176 *chip = AHC_AIC7890; 1177 *features = AHC_AIC7890_FE; 1178 *flags |= AHC_NEWEEPROM_FMT; 1179 return (0); 1180 } 1181 1182 static int 1183 ahc_aic7892_setup(struct pci_attach_args *pa, char *channel, 1184 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1185 { 1186 *channel = 'A'; 1187 *chip = AHC_AIC7892; 1188 *features = AHC_AIC7892_FE; 1189 *flags |= AHC_NEWEEPROM_FMT; 1190 return (0); 1191 } 1192 1193 static int 1194 ahc_aic7895_setup(struct pci_attach_args *pa, char *channel, 1195 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1196 { 1197 pcireg_t devconfig; 1198 1199 *channel = pa->pa_function == 1 ? 'B' : 'A'; 1200 *chip = AHC_AIC7895; 1201 /* The 'C' revision of the aic7895 has a few additional features */ 1202 if (PCI_REVISION(pa->pa_class) >= 4) 1203 *features = AHC_AIC7895C_FE; 1204 else 1205 *features = AHC_AIC7895_FE; 1206 *flags |= AHC_NEWEEPROM_FMT; 1207 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 1208 devconfig &= ~SCBSIZE32; 1209 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); 1210 return (0); 1211 } 1212 1213 static int 1214 ahc_aic7896_setup(struct pci_attach_args *pa, char *channel, 1215 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1216 { 1217 *channel = pa->pa_function == 1 ? 'B' : 'A'; 1218 *chip = AHC_AIC7896; 1219 *features = AHC_AIC7896_FE; 1220 *flags |= AHC_NEWEEPROM_FMT; 1221 return (0); 1222 } 1223 1224 static int 1225 ahc_aic7899_setup(struct pci_attach_args *pa, char *channel, 1226 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1227 { 1228 *channel = pa->pa_function == 1 ? 'B' : 'A'; 1229 *chip = AHC_AIC7899; 1230 *features = AHC_AIC7899_FE; 1231 *flags |= AHC_NEWEEPROM_FMT; 1232 return (0); 1233 } 1234 1235 static int 1236 ahc_raid_setup(struct pci_attach_args *pa, char *channel, 1237 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1238 { 1239 printf(": RAID functionality unsupported\n"); 1240 return (ENXIO); 1241 } 1242 1243 static int 1244 ahc_aha394XX_setup(struct pci_attach_args *pa, char *channel, 1245 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1246 { 1247 switch (pa->pa_device) { 1248 case AHC_394X_SLOT_CHANNEL_A: 1249 *channel = 'A'; 1250 break; 1251 case AHC_394X_SLOT_CHANNEL_B: 1252 *channel = 'B'; 1253 break; 1254 default: 1255 printf("adapter at unexpected slot %d\n" 1256 "unable to map to a channel\n", 1257 pa->pa_device); 1258 *channel = 'A'; 1259 } 1260 return (0); 1261 } 1262 1263 static int 1264 ahc_aha398XX_setup(struct pci_attach_args *pa, char *channel, 1265 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1266 { 1267 switch (pa->pa_device) { 1268 case AHC_398X_SLOT_CHANNEL_A: 1269 *channel = 'A'; 1270 break; 1271 case AHC_398X_SLOT_CHANNEL_B: 1272 *channel = 'B'; 1273 break; 1274 case AHC_398X_SLOT_CHANNEL_C: 1275 *channel = 'C'; 1276 break; 1277 default: 1278 printf("adapter at unexpected slot %d\n" 1279 "unable to map to a channel\n", 1280 pa->pa_device); 1281 *channel = 'A'; 1282 } 1283 *flags |= AHC_LARGE_SEEPROM; 1284 return (0); 1285 } 1286
Indexes created Wed Oct 01 19:09:53 GMT 2025