ahc_pci.c revision 1.29.2.4
1 /* $NetBSD: ahc_pci.c,v 1.29.2.4 2002/10/18 02:42:54 nathanw Exp $ */ 2 3 /* 4 * Product specific probe and attach routines for: 5 * 3940, 2940, aic7895, aic7890, aic7880, 6 * aic7870, aic7860 and aic7850 SCSI controllers 7 * 8 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * Alternatively, this software may be distributed under the terms of the 21 * the GNU Public License ("GPL"). 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/aic7xxx/ahc_pci.c,v 1.28 2000/02/09 21:00:22 gibbs Exp $ 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ahc_pci.c,v 1.29.2.4 2002/10/18 02:42:54 nathanw Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/queue.h> 46 #include <sys/device.h> 47 #include <sys/reboot.h> 48 49 #include <machine/bus.h> 50 #include <machine/intr.h> 51 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 55 /* XXXX some i386 on-board chips act weird when memory-mapped */ 56 #ifndef __i386__ 57 #define AHC_ALLOW_MEMIO 58 #endif 59 60 #define AHC_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 61 #define AHC_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 62 63 #include <dev/scsipi/scsi_all.h> 64 #include <dev/scsipi/scsipi_all.h> 65 #include <dev/scsipi/scsiconf.h> 66 67 #include <dev/ic/aic7xxxvar.h> 68 #include <dev/ic/smc93cx6var.h> 69 70 #include <dev/microcode/aic7xxx/aic7xxx_reg.h> 71 72 struct ahc_pci_busdata { 73 pci_chipset_tag_t pc; 74 pcitag_t tag; 75 u_int dev; 76 u_int func; 77 }; 78 79 static __inline u_int64_t 80 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 81 { 82 u_int64_t id; 83 84 id = subvendor 85 | (subdevice << 16) 86 | ((u_int64_t)vendor << 32) 87 | ((u_int64_t)device << 48); 88 89 return (id); 90 } 91 92 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 93 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 94 #define ID_AIC7850 0x5078900400000000ull 95 #define ID_AHA_2910_15_20_30C 0x5078900478509004ull 96 #define ID_AIC7855 0x5578900400000000ull 97 #define ID_AIC7859 0x3860900400000000ull 98 #define ID_AHA_2930CU 0x3860900438699004ull 99 #define ID_AIC7860 0x6078900400000000ull 100 #define ID_AIC7860C 0x6078900478609004ull 101 #define ID_AHA_2940AU_0 0x6178900400000000ull 102 #define ID_AHA_2940AU_1 0x6178900478619004ull 103 #define ID_AHA_2940AU_CN 0x2178900478219004ull 104 #define ID_AHA_2930C_VAR 0x6038900438689004ull 105 106 #define ID_AIC7870 0x7078900400000000ull 107 #define ID_AHA_2940 0x7178900400000000ull 108 #define ID_AHA_3940 0x7278900400000000ull 109 #define ID_AHA_398X 0x7378900400000000ull 110 #define ID_AHA_2944 0x7478900400000000ull 111 #define ID_AHA_3944 0x7578900400000000ull 112 113 #define ID_AIC7880 0x8078900400000000ull 114 #define ID_AIC7880_B 0x8078900478809004ull 115 #define ID_AHA_2940U 0x8178900400000000ull 116 #define ID_AHA_3940U 0x8278900400000000ull 117 #define ID_AHA_2944U 0x8478900400000000ull 118 #define ID_AHA_3944U 0x8578900400000000ull 119 #define ID_AHA_398XU 0x8378900400000000ull 120 #define ID_AHA_4944U 0x8678900400000000ull 121 #define ID_AHA_2940UB 0x8178900478819004ull 122 #define ID_AHA_2930U 0x8878900478889004ull 123 #define ID_AHA_2940U_PRO 0x8778900478879004ull 124 #define ID_AHA_2940U_CN 0x0078900478009004ull 125 126 #define ID_AIC7895 0x7895900478959004ull 127 #define ID_AIC7895_RAID_PORT 0x7893900478939004ull 128 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 129 #define ID_AHA_3940AU 0x7895900478929004ull 130 #define ID_AHA_3944AU 0x7895900478949004ull 131 132 #define ID_AIC7890 0x001F9005000F9005ull 133 #define ID_AAA_131U2 0x0013900500039005ull 134 #define ID_AHA_2930U2 0x0011900501819005ull 135 #define ID_AHA_2940U2B 0x00109005A1009005ull 136 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 137 #define ID_AHA_2940U2 0x00109005A1809005ull 138 #define ID_AHA_2950U2B 0x00109005E1009005ull 139 140 #define ID_AIC7892 0x008F9005FFFF9005ull 141 #define ID_AHA_29160 0x00809005E2A09005ull 142 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 143 #define ID_AHA_29160N 0x0080900562A09005ull 144 #define ID_AHA_29160B 0x00809005E2209005ull 145 #define ID_AHA_19160B 0x0081900562A19005ull 146 147 #define ID_AIC7896 0x005F9005FFFF9005ull 148 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 149 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 150 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 151 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 152 153 #define ID_AIC7899 0x00CF9005FFFF9005ull 154 #define ID_AHA_3960D 0x00C09005F6209005ull /* AKA AHA-39160 */ 155 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 156 157 #define ID_AIC7810 0x1078900400000000ull 158 #define ID_AIC7815 0x7815900400000000ull 159 160 typedef int (ahc_device_setup_t)(struct pci_attach_args *, char *, 161 ahc_chip *, ahc_feature *, ahc_flag *); 162 163 static ahc_device_setup_t ahc_aic7850_setup; 164 static ahc_device_setup_t ahc_aic7855_setup; 165 static ahc_device_setup_t ahc_aic7859_setup; 166 static ahc_device_setup_t ahc_aic7860_setup; 167 static ahc_device_setup_t ahc_aic7870_setup; 168 static ahc_device_setup_t ahc_aha394X_setup; 169 static ahc_device_setup_t ahc_aha398X_setup; 170 static ahc_device_setup_t ahc_aic7880_setup; 171 static ahc_device_setup_t ahc_2940Pro_setup; 172 static ahc_device_setup_t ahc_aha394XU_setup; 173 static ahc_device_setup_t ahc_aha398XU_setup; 174 static ahc_device_setup_t ahc_aic7890_setup; 175 static ahc_device_setup_t ahc_aic7892_setup; 176 static ahc_device_setup_t ahc_aic7895_setup; 177 static ahc_device_setup_t ahc_aic7896_setup; 178 static ahc_device_setup_t ahc_aic7899_setup; 179 static ahc_device_setup_t ahc_raid_setup; 180 static ahc_device_setup_t ahc_aha394XX_setup; 181 static ahc_device_setup_t ahc_aha398XX_setup; 182 183 struct ahc_pci_identity { 184 u_int64_t full_id; 185 u_int64_t id_mask; 186 const char *name; 187 ahc_device_setup_t *setup; 188 }; 189 190 const struct ahc_pci_identity ahc_pci_ident_table [] = 191 { 192 /* aic7850 based controllers */ 193 { 194 ID_AHA_2910_15_20_30C, 195 ID_ALL_MASK, 196 "Adaptec 2910/15/20/30C SCSI adapter", 197 ahc_aic7850_setup 198 }, 199 /* aic7859 based controllers */ 200 { 201 ID_AHA_2930CU, 202 ID_ALL_MASK, 203 "Adaptec 2930CU SCSI adapter", 204 ahc_aic7859_setup 205 }, 206 /* aic7860 based controllers */ 207 { 208 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 209 ID_DEV_VENDOR_MASK, 210 "Adaptec 2940A Ultra SCSI adapter", 211 ahc_aic7860_setup 212 }, 213 { 214 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 215 ID_DEV_VENDOR_MASK, 216 "Adaptec 2940A/CN Ultra SCSI adapter", 217 ahc_aic7860_setup 218 }, 219 { 220 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 221 ID_DEV_VENDOR_MASK, 222 "Adaptec 2930C SCSI adapter (VAR)", 223 ahc_aic7860_setup 224 }, 225 /* aic7870 based controllers */ 226 { 227 ID_AHA_2940, 228 ID_ALL_MASK, 229 "Adaptec 2940 SCSI adapter", 230 ahc_aic7870_setup 231 }, 232 { 233 ID_AHA_3940, 234 ID_ALL_MASK, 235 "Adaptec 3940 SCSI adapter", 236 ahc_aha394X_setup 237 }, 238 { 239 ID_AHA_398X, 240 ID_ALL_MASK, 241 "Adaptec 398X SCSI RAID adapter", 242 ahc_aha398X_setup 243 }, 244 { 245 ID_AHA_2944, 246 ID_ALL_MASK, 247 "Adaptec 2944 SCSI adapter", 248 ahc_aic7870_setup 249 }, 250 { 251 ID_AHA_3944, 252 ID_ALL_MASK, 253 "Adaptec 3944 SCSI adapter", 254 ahc_aha394X_setup 255 }, 256 /* aic7880 based controllers */ 257 { 258 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 259 ID_DEV_VENDOR_MASK, 260 "Adaptec 2940 Ultra SCSI adapter", 261 ahc_aic7880_setup 262 }, 263 { 264 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 265 ID_DEV_VENDOR_MASK, 266 "Adaptec 3940 Ultra SCSI adapter", 267 ahc_aha394XU_setup 268 }, 269 { 270 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 271 ID_DEV_VENDOR_MASK, 272 "Adaptec 2944 Ultra SCSI adapter", 273 ahc_aic7880_setup 274 }, 275 { 276 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 277 ID_DEV_VENDOR_MASK, 278 "Adaptec 3944 Ultra SCSI adapter", 279 ahc_aha394XU_setup 280 }, 281 { 282 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 283 ID_DEV_VENDOR_MASK, 284 "Adaptec 398X Ultra SCSI RAID adapter", 285 ahc_aha398XU_setup 286 }, 287 { 288 /* 289 * XXX Don't know the slot numbers 290 * so we can't identify channels 291 */ 292 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 293 ID_DEV_VENDOR_MASK, 294 "Adaptec 4944 Ultra SCSI adapter", 295 ahc_aic7880_setup 296 }, 297 { 298 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 299 ID_DEV_VENDOR_MASK, 300 "Adaptec 2930 Ultra SCSI adapter", 301 ahc_aic7880_setup 302 }, 303 { 304 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 305 ID_DEV_VENDOR_MASK, 306 "Adaptec 2940 Pro Ultra SCSI adapter", 307 ahc_2940Pro_setup 308 }, 309 { 310 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 311 ID_DEV_VENDOR_MASK, 312 "Adaptec 2940/CN Ultra SCSI adapter", 313 ahc_aic7880_setup 314 }, 315 /* aic7890 based controllers */ 316 { 317 ID_AHA_2930U2, 318 ID_ALL_MASK, 319 "Adaptec 2930 Ultra2 SCSI adapter", 320 ahc_aic7890_setup 321 }, 322 { 323 ID_AHA_2940U2B, 324 ID_ALL_MASK, 325 "Adaptec 2940B Ultra2 SCSI adapter", 326 ahc_aic7890_setup 327 }, 328 { 329 ID_AHA_2940U2_OEM, 330 ID_ALL_MASK, 331 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 332 ahc_aic7890_setup 333 }, 334 { 335 ID_AHA_2940U2, 336 ID_ALL_MASK, 337 "Adaptec 2940 Ultra2 SCSI adapter", 338 ahc_aic7890_setup 339 }, 340 { 341 ID_AHA_2950U2B, 342 ID_ALL_MASK, 343 "Adaptec 2950 Ultra2 SCSI adapter", 344 ahc_aic7890_setup 345 }, 346 { 347 ID_AAA_131U2, 348 ID_ALL_MASK, 349 "Adaptec AAA-131 Ultra2 RAID adapter", 350 ahc_aic7890_setup 351 }, 352 /* aic7892 based controllers */ 353 { 354 ID_AHA_29160, 355 ID_ALL_MASK, 356 "Adaptec 29160 Ultra160 SCSI adapter", 357 ahc_aic7892_setup 358 }, 359 { 360 ID_AHA_29160_CPQ, 361 ID_ALL_MASK, 362 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 363 ahc_aic7892_setup 364 }, 365 { 366 ID_AHA_29160N, 367 ID_ALL_MASK, 368 "Adaptec 29160N Ultra160 SCSI adapter", 369 ahc_aic7892_setup 370 }, 371 { 372 ID_AHA_29160B, 373 ID_ALL_MASK, 374 "Adaptec 29160B Ultra160 SCSI adapter", 375 ahc_aic7892_setup 376 }, 377 { 378 ID_AHA_19160B, 379 ID_ALL_MASK, 380 "Adaptec 19160B Ultra160 SCSI adapter", 381 ahc_aic7892_setup 382 }, 383 /* aic7895 based controllers */ 384 { 385 ID_AHA_2940U_DUAL, 386 ID_ALL_MASK, 387 "Adaptec 2940/DUAL Ultra SCSI adapter", 388 ahc_aic7895_setup 389 }, 390 { 391 ID_AHA_3940AU, 392 ID_ALL_MASK, 393 "Adaptec 3940A Ultra SCSI adapter", 394 ahc_aic7895_setup 395 }, 396 { 397 ID_AHA_3944AU, 398 ID_ALL_MASK, 399 "Adaptec 3944A Ultra SCSI adapter", 400 ahc_aic7895_setup 401 }, 402 /* aic7896/97 based controllers */ 403 { 404 ID_AHA_3950U2B_0, 405 ID_ALL_MASK, 406 "Adaptec 3950B Ultra2 SCSI adapter", 407 ahc_aic7896_setup 408 }, 409 { 410 ID_AHA_3950U2B_1, 411 ID_ALL_MASK, 412 "Adaptec 3950B Ultra2 SCSI adapter", 413 ahc_aic7896_setup 414 }, 415 { 416 ID_AHA_3950U2D_0, 417 ID_ALL_MASK, 418 "Adaptec 3950D Ultra2 SCSI adapter", 419 ahc_aic7896_setup 420 }, 421 { 422 ID_AHA_3950U2D_1, 423 ID_ALL_MASK, 424 "Adaptec 3950D Ultra2 SCSI adapter", 425 ahc_aic7896_setup 426 }, 427 /* aic7899 based controllers */ 428 { 429 ID_AHA_3960D, 430 ID_ALL_MASK, 431 "Adaptec 3960D Ultra160 SCSI adapter", 432 ahc_aic7899_setup 433 }, 434 { 435 ID_AHA_3960D_CPQ, 436 ID_ALL_MASK, 437 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 438 ahc_aic7899_setup 439 }, 440 /* Generic chip probes for devices we don't know 'exactly' */ 441 { 442 ID_AIC7850 & ID_DEV_VENDOR_MASK, 443 ID_DEV_VENDOR_MASK, 444 "Adaptec aic7850 SCSI adapter", 445 ahc_aic7850_setup 446 }, 447 { 448 ID_AIC7855 & ID_DEV_VENDOR_MASK, 449 ID_DEV_VENDOR_MASK, 450 "Adaptec aic7855 SCSI adapter", 451 ahc_aic7855_setup 452 }, 453 { 454 ID_AIC7859 & ID_DEV_VENDOR_MASK, 455 ID_DEV_VENDOR_MASK, 456 "Adaptec aic7859 SCSI adapter", 457 ahc_aic7859_setup 458 }, 459 { 460 ID_AIC7860 & ID_DEV_VENDOR_MASK, 461 ID_DEV_VENDOR_MASK, 462 "Adaptec aic7860 SCSI adapter", 463 ahc_aic7860_setup 464 }, 465 { 466 ID_AIC7870 & ID_DEV_VENDOR_MASK, 467 ID_DEV_VENDOR_MASK, 468 "Adaptec aic7870 SCSI adapter", 469 ahc_aic7870_setup 470 }, 471 { 472 ID_AIC7880 & ID_DEV_VENDOR_MASK, 473 ID_DEV_VENDOR_MASK, 474 "Adaptec aic7880 Ultra SCSI adapter", 475 ahc_aic7880_setup 476 }, 477 { 478 ID_AIC7890 & ID_DEV_VENDOR_MASK, 479 ID_DEV_VENDOR_MASK, 480 "Adaptec aic7890/91 Ultra2 SCSI adapter", 481 ahc_aic7890_setup 482 }, 483 { 484 ID_AIC7892 & ID_DEV_VENDOR_MASK, 485 ID_DEV_VENDOR_MASK, 486 "Adaptec aic7892 Ultra160 SCSI adapter", 487 ahc_aic7892_setup 488 }, 489 { 490 ID_AIC7895 & ID_DEV_VENDOR_MASK, 491 ID_DEV_VENDOR_MASK, 492 "Adaptec aic7895 Ultra SCSI adapter", 493 ahc_aic7895_setup 494 }, 495 { 496 ID_AIC7895_RAID_PORT & ID_DEV_VENDOR_MASK, 497 ID_DEV_VENDOR_MASK, 498 "Adaptec aic7895 Ultra SCSI adapter (RAID PORT)", 499 ahc_aic7895_setup 500 }, 501 { 502 ID_AIC7896 & ID_DEV_VENDOR_MASK, 503 ID_DEV_VENDOR_MASK, 504 "Adaptec aic7896/97 Ultra2 SCSI adapter", 505 ahc_aic7896_setup 506 }, 507 { 508 ID_AIC7899 & ID_DEV_VENDOR_MASK, 509 ID_DEV_VENDOR_MASK, 510 "Adaptec aic7899 Ultra160 SCSI adapter", 511 ahc_aic7899_setup 512 }, 513 { 514 ID_AIC7810 & ID_DEV_VENDOR_MASK, 515 ID_DEV_VENDOR_MASK, 516 "Adaptec aic7810 RAID memory controller", 517 ahc_raid_setup 518 }, 519 { 520 ID_AIC7815 & ID_DEV_VENDOR_MASK, 521 ID_DEV_VENDOR_MASK, 522 "Adaptec aic7815 RAID memory controller", 523 ahc_raid_setup 524 } 525 }; 526 527 static const int ahc_num_pci_devs = 528 sizeof(ahc_pci_ident_table) / sizeof(*ahc_pci_ident_table); 529 530 #define AHC_394X_SLOT_CHANNEL_A 4 531 #define AHC_394X_SLOT_CHANNEL_B 5 532 533 #define AHC_398X_SLOT_CHANNEL_A 4 534 #define AHC_398X_SLOT_CHANNEL_B 8 535 #define AHC_398X_SLOT_CHANNEL_C 12 536 537 #define DEVCONFIG 0x40 538 #define SCBSIZE32 0x00010000 /* aic789X only */ 539 #define MPORTMODE 0x00000400 /* aic7870 only */ 540 #define RAMPSM 0x00000200 /* aic7870 only */ 541 #define VOLSENSE 0x00000100 542 #define SCBRAMSEL 0x00000080 543 #define MRDCEN 0x00000040 544 #define EXTSCBTIME 0x00000020 /* aic7870 only */ 545 #define EXTSCBPEN 0x00000010 /* aic7870 only */ 546 #define BERREN 0x00000008 547 #define DACEN 0x00000004 548 #define STPWLEVEL 0x00000002 549 #define DIFACTNEGEN 0x00000001 /* aic7870 only */ 550 551 #define CSIZE_LATTIME 0x0c 552 #define CACHESIZE 0x0000003f /* only 5 bits */ 553 #define LATTIME 0x0000ff00 554 555 static const struct ahc_pci_identity *ahc_find_pci_device(pcireg_t, pcireg_t); 556 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 557 static void ahc_ext_scbram_config(struct ahc_softc *ahc, int enable, 558 int pcheck, int fast); 559 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 560 561 int ahc_pci_probe __P((struct device *, struct cfdata *, void *)); 562 void ahc_pci_attach __P((struct device *, struct device *, void *)); 563 564 /* Exported for use in the ahc_intr routine */ 565 int ahc_pci_intr(struct ahc_softc *ahc); 566 567 CFATTACH_DECL(ahc_pci, sizeof(struct ahc_softc), 568 ahc_pci_probe, ahc_pci_attach, NULL, NULL); 569 570 static const struct ahc_pci_identity * 571 ahc_find_pci_device(id, subid) 572 pcireg_t id, subid; 573 { 574 u_int64_t full_id; 575 const struct ahc_pci_identity *entry; 576 u_int i; 577 578 full_id = ahc_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 579 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 580 581 for (i = 0; i < ahc_num_pci_devs; i++) { 582 entry = &ahc_pci_ident_table[i]; 583 if (entry->full_id == (full_id & entry->id_mask)) 584 return (entry); 585 } 586 return (NULL); 587 } 588 589 int 590 ahc_pci_probe(parent, match, aux) 591 struct device *parent; 592 struct cfdata *match; 593 void *aux; 594 { 595 struct pci_attach_args *pa = aux; 596 const struct ahc_pci_identity *entry; 597 pcireg_t subid; 598 599 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 600 entry = ahc_find_pci_device(pa->pa_id, subid); 601 return entry != NULL ? 1 : 0; 602 } 603 604 void 605 ahc_pci_attach(parent, self, aux) 606 struct device *parent, *self; 607 void *aux; 608 { 609 struct pci_attach_args *pa = aux; 610 const struct ahc_pci_identity *entry; 611 struct ahc_softc *ahc = (void *)self; 612 pcireg_t command; 613 ahc_chip ahc_t = AHC_NONE; 614 ahc_feature ahc_fe = AHC_FENONE; 615 ahc_flag ahc_f = AHC_FNONE; 616 u_int our_id = 0; 617 u_int sxfrctl1; 618 u_int scsiseq; 619 int error; 620 char channel; 621 pcireg_t subid; 622 int ioh_valid, memh_valid; 623 bus_space_tag_t st, iot; 624 bus_space_handle_t sh, ioh; 625 #ifdef AHC_ALLOW_MEMIO 626 bus_space_tag_t memt; 627 bus_space_handle_t memh; 628 pcireg_t memtype; 629 #endif 630 pci_intr_handle_t ih; 631 const char *intrstr; 632 struct ahc_pci_busdata *bd; 633 634 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 635 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 636 entry = ahc_find_pci_device(pa->pa_id, subid); 637 if (entry == NULL) 638 return; 639 error = entry->setup(pa, &channel, &ahc_t, &ahc_fe, &ahc_f); 640 if (error != 0) 641 return; 642 643 ioh_valid = memh_valid = 0; 644 645 #ifdef AHC_ALLOW_MEMIO 646 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHC_PCI_MEMADDR); 647 switch (memtype) { 648 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 649 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 650 memh_valid = (pci_mapreg_map(pa, AHC_PCI_MEMADDR, 651 memtype, 0, &memt, &memh, NULL, NULL) == 0); 652 break; 653 default: 654 memh_valid = 0; 655 } 656 #endif 657 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_IOADDR, 658 PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, NULL, NULL) == 0); 659 660 if (ioh_valid) { 661 st = iot; 662 sh = ioh; 663 #ifdef AHC_ALLOW_MEMIO 664 } else if (memh_valid) { 665 st = memt; 666 sh = memh; 667 #endif 668 } else { 669 printf(": unable to map registers\n"); 670 return; 671 } 672 673 printf("\n"); 674 675 676 /* Ensure busmastering is enabled */ 677 command |= PCI_COMMAND_MASTER_ENABLE;; 678 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 679 680 /* On all PCI adapters, we allow SCB paging */ 681 ahc_f |= AHC_PAGESCBS; 682 if (ahc_alloc(ahc, sh, st, pa->pa_dmat, 683 ahc_t|AHC_PCI, ahc_fe, ahc_f) < 0) 684 return; 685 686 bd = malloc(sizeof (struct ahc_pci_busdata), M_DEVBUF, M_NOWAIT); 687 if (bd == NULL) { 688 printf(": unable to allocate bus-specific data\n"); 689 return; 690 } 691 692 bd->pc = pa->pa_pc; 693 bd->tag = pa->pa_tag; 694 bd->func = pa->pa_function; 695 bd->dev = pa->pa_device; 696 697 ahc->bus_data = bd; 698 ahc->bus_intr = ahc_pci_intr; 699 ahc->channel = channel; 700 701 /* Remeber how the card was setup in case there is no SEEPROM */ 702 ahc_outb(ahc, HCNTRL, ahc->pause); 703 if ((ahc->features & AHC_ULTRA2) != 0) 704 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 705 else 706 our_id = ahc_inb(ahc, SCSIID) & OID; 707 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 708 scsiseq = ahc_inb(ahc, SCSISEQ); 709 710 if (ahc_reset(ahc) != 0) { 711 /* Failed */ 712 ahc_free(ahc); 713 return; 714 } 715 716 if ((ahc->features & AHC_DT) != 0) { 717 u_int optionmode; 718 u_int sfunct; 719 720 /* Perform ALT-Mode Setup */ 721 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 722 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 723 optionmode = ahc_inb(ahc, OPTIONMODE); 724 #ifdef DEBUG 725 printf("%s: OptionMode = %x\n", ahc->sc_dev.dv_xname, 726 optionmode); 727 #endif 728 ahc_outb(ahc, OPTIONMODE, OPTIONMODE_DEFAULTS); 729 /* Send CRC info in target mode every 4K */ 730 ahc_outb(ahc, TARGCRCCNT, 0); 731 ahc_outb(ahc, TARGCRCCNT + 1, 0x10); 732 ahc_outb(ahc, SFUNCT, sfunct); 733 734 /* Normal mode setup */ 735 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 736 |TARGCRCENDEN|TARGCRCCNTEN); 737 } 738 739 if (pci_intr_map(pa, &ih)) { 740 printf("%s: couldn't map interrupt\n", ahc->sc_dev.dv_xname); 741 ahc_free(ahc); 742 return; 743 } 744 intrstr = pci_intr_string(pa->pa_pc, ih); 745 ahc->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahc_intr, ahc); 746 if (ahc->ih == NULL) { 747 printf("%s: couldn't establish interrupt", 748 ahc->sc_dev.dv_xname); 749 if (intrstr != NULL) 750 printf(" at %s", intrstr); 751 printf("\n"); 752 ahc_free(ahc); 753 return; 754 } 755 if (intrstr != NULL) 756 printf("%s: interrupting at %s\n", ahc->sc_dev.dv_xname, 757 intrstr); 758 759 /* 760 * Do aic7880/aic7870/aic7860/aic7850 specific initialization 761 */ 762 { 763 u_int8_t sblkctl; 764 u_int dscommand0; 765 766 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 767 dscommand0 |= MPARCKEN; 768 if ((ahc->features & AHC_ULTRA2) != 0) { 769 770 /* 771 * DPARCKEN doesn't work correctly on 772 * some MBs so don't use it. 773 */ 774 dscommand0 &= ~(USCBSIZE32|DPARCKEN); 775 dscommand0 |= CACHETHEN; 776 } 777 778 ahc_outb(ahc, DSCOMMAND0, dscommand0); 779 780 /* See if we have an SEEPROM and perform auto-term */ 781 check_extport(ahc, &sxfrctl1); 782 783 /* 784 * Take the LED out of diagnostic mode 785 */ 786 sblkctl = ahc_inb(ahc, SBLKCTL); 787 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 788 789 /* 790 * I don't know where this is set in the SEEPROM or by the 791 * BIOS, so we default to 100% on Ultra or slower controllers 792 * and 75% on ULTRA2 controllers. 793 */ 794 if ((ahc->features & AHC_ULTRA2) != 0) { 795 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 796 } else { 797 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 798 } 799 800 if (ahc->flags & AHC_USEDEFAULTS) { 801 /* 802 * PCI Adapter default setup 803 * Should only be used if the adapter does not have 804 * an SEEPROM. 805 */ 806 /* See if someone else set us up already */ 807 if (scsiseq != 0) { 808 printf("%s: Using left over BIOS settings\n", 809 ahc_name(ahc)); 810 ahc->flags &= ~AHC_USEDEFAULTS; 811 } else { 812 /* 813 * Assume only one connector and always turn 814 * on termination. 815 */ 816 our_id = 0x07; 817 sxfrctl1 = STPWEN; 818 } 819 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 820 821 ahc->our_id = our_id; 822 } 823 } 824 825 /* 826 * Take a look to see if we have external SRAM. 827 * We currently do not attempt to use SRAM that is 828 * shared among multiple controllers. 829 */ 830 ahc_probe_ext_scbram(ahc); 831 832 833 printf("%s: %s ", ahc_name(ahc), 834 ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); 835 836 /* 837 * Record our termination setting for the 838 * generic initialization routine. 839 */ 840 if ((sxfrctl1 & STPWEN) != 0) 841 ahc->flags |= AHC_TERM_ENB_A; 842 843 if (ahc_init(ahc)) { 844 ahc_free(ahc); 845 return; 846 } 847 848 ahc_attach(ahc); 849 } 850 851 /* 852 * Test for the presence of external sram in an 853 * "unshared" configuration. 854 */ 855 static int 856 ahc_ext_scbram_present(struct ahc_softc *ahc) 857 { 858 int ramps; 859 int single_user; 860 pcireg_t devconfig; 861 struct ahc_pci_busdata *bd = ahc->bus_data; 862 863 devconfig = pci_conf_read(bd->pc, bd->tag, DEVCONFIG); 864 single_user = (devconfig & MPORTMODE) != 0; 865 866 if ((ahc->features & AHC_ULTRA2) != 0) 867 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 868 else if ((ahc->chip & AHC_CHIPID_MASK) >= AHC_AIC7870) 869 ramps = (devconfig & RAMPSM) != 0; 870 else 871 ramps = 0; 872 873 if (ramps && single_user) 874 return (1); 875 return (0); 876 } 877 878 /* 879 * Enable external scbram. 880 */ 881 static void 882 ahc_ext_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, int fast) 883 { 884 pcireg_t devconfig; 885 struct ahc_pci_busdata *bd = ahc->bus_data; 886 887 if (ahc->features & AHC_MULTI_FUNC) { 888 /* 889 * Set the SCB Base addr (highest address bit) 890 * depending on which channel we are. 891 */ 892 ahc_outb(ahc, SCBBADDR, (u_int8_t)bd->func); 893 } 894 895 devconfig = pci_conf_read(bd->pc, bd->tag, DEVCONFIG); 896 if ((ahc->features & AHC_ULTRA2) != 0) { 897 u_int dscommand0; 898 899 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 900 if (enable) 901 dscommand0 &= ~INTSCBRAMSEL; 902 else 903 dscommand0 |= INTSCBRAMSEL; 904 ahc_outb(ahc, DSCOMMAND0, dscommand0); 905 } else { 906 if (fast) 907 devconfig &= ~EXTSCBTIME; 908 else 909 devconfig |= EXTSCBTIME; 910 if (enable) 911 devconfig &= ~SCBRAMSEL; 912 else 913 devconfig |= SCBRAMSEL; 914 } 915 if (pcheck) 916 devconfig |= EXTSCBPEN; 917 else 918 devconfig &= ~EXTSCBPEN; 919 920 pci_conf_write(bd->pc, bd->tag, DEVCONFIG, devconfig); 921 } 922 923 /* 924 * Take a look to see if we have external SRAM. 925 * We currently do not attempt to use SRAM that is 926 * shared among multiple controllers. 927 */ 928 static void 929 ahc_probe_ext_scbram(struct ahc_softc *ahc) 930 { 931 int num_scbs; 932 int test_num_scbs; 933 int enable; 934 int pcheck; 935 int fast; 936 937 if (ahc_ext_scbram_present(ahc) == 0) 938 return; 939 940 /* 941 * Probe for the best parameters to use. 942 */ 943 enable = FALSE; 944 pcheck = FALSE; 945 fast = FALSE; 946 ahc_ext_scbram_config(ahc, /*enable*/TRUE, pcheck, fast); 947 num_scbs = ahc_probe_scbs(ahc); 948 if (num_scbs == 0) { 949 /* The SRAM wasn't really present. */ 950 goto done; 951 } 952 enable = TRUE; 953 954 /* 955 * Clear any outstanding parity error 956 * and ensure that parity error reporting 957 * is enabled. 958 */ 959 ahc_outb(ahc, SEQCTL, 0); 960 ahc_outb(ahc, CLRINT, CLRPARERR); 961 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 962 963 /* Now see if we can do parity */ 964 ahc_ext_scbram_config(ahc, enable, /*pcheck*/TRUE, fast); 965 num_scbs = ahc_probe_scbs(ahc); 966 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 967 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 968 pcheck = TRUE; 969 970 /* Clear any resulting parity error */ 971 ahc_outb(ahc, CLRINT, CLRPARERR); 972 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 973 974 /* Now see if we can do fast timing */ 975 ahc_ext_scbram_config(ahc, enable, pcheck, /*fast*/TRUE); 976 test_num_scbs = ahc_probe_scbs(ahc); 977 if (test_num_scbs == num_scbs 978 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 979 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 980 fast = TRUE; 981 982 done: 983 /* 984 * Disable parity error reporting until we 985 * can load instruction ram. 986 */ 987 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 988 /* Clear any latched parity error */ 989 ahc_outb(ahc, CLRINT, CLRPARERR); 990 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 991 if (bootverbose && enable) { 992 printf("%s: External SRAM, %s access%s\n", 993 ahc_name(ahc), fast ? "fast" : "slow", 994 pcheck ? ", parity checking enabled" : ""); 995 996 } 997 ahc_ext_scbram_config(ahc, enable, pcheck, fast); 998 } 999 1000 #define DPE PCI_STATUS_PARITY_DETECT 1001 #define SSE PCI_STATUS_SPECIAL_ERROR 1002 #define RMA PCI_STATUS_MASTER_ABORT 1003 #define RTA PCI_STATUS_MASTER_TARGET_ABORT 1004 #define STA PCI_STATUS_TARGET_TARGET_ABORT 1005 #define DPR PCI_STATUS_PARITY_ERROR 1006 1007 int 1008 ahc_pci_intr(struct ahc_softc *ahc) 1009 { 1010 pcireg_t status1; 1011 struct ahc_pci_busdata *bd = ahc->bus_data; 1012 1013 if ((ahc_inb(ahc, ERROR) & PCIERRSTAT) == 0) 1014 return 0; 1015 1016 status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 1017 1018 if (status1 & DPE) { 1019 printf("%s: Data Parity Error Detected during address " 1020 "or write data phase\n", ahc_name(ahc)); 1021 } 1022 if (status1 & SSE) { 1023 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1024 } 1025 if (status1 & RMA) { 1026 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1027 } 1028 if (status1 & RTA) { 1029 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1030 } 1031 if (status1 & STA) { 1032 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1033 } 1034 if (status1 & DPR) { 1035 printf("%s: Data Parity Error has been reported via PERR#\n", 1036 ahc_name(ahc)); 1037 } 1038 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1039 printf("%s: Latched PCIERR interrupt with " 1040 "no status bits set\n", ahc_name(ahc)); 1041 } 1042 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, status1); 1043 1044 if (status1 & (DPR|RMA|RTA)) { 1045 ahc_outb(ahc, CLRINT, CLRPARERR); 1046 } 1047 1048 return 1; 1049 } 1050 1051 static int 1052 ahc_aic7850_setup(struct pci_attach_args *pa, char *channel, 1053 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1054 { 1055 *channel = 'A'; 1056 *chip = AHC_AIC7850; 1057 *features = AHC_AIC7850_FE; 1058 return (0); 1059 } 1060 1061 static int 1062 ahc_aic7855_setup(struct pci_attach_args *pa, char *channel, 1063 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1064 { 1065 *channel = 'A'; 1066 *chip = AHC_AIC7855; 1067 *features = AHC_AIC7855_FE; 1068 return (0); 1069 } 1070 1071 static int 1072 ahc_aic7859_setup(struct pci_attach_args *pa, char *channel, 1073 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1074 { 1075 *channel = 'A'; 1076 *chip = AHC_AIC7859; 1077 *features = AHC_AIC7859_FE; 1078 return (0); 1079 } 1080 1081 static int 1082 ahc_aic7860_setup(struct pci_attach_args *pa, char *channel, 1083 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1084 { 1085 *channel = 'A'; 1086 *chip = AHC_AIC7860; 1087 *features = AHC_AIC7860_FE; 1088 return (0); 1089 } 1090 1091 static int 1092 ahc_aic7870_setup(struct pci_attach_args *pa, char *channel, 1093 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1094 { 1095 *channel = 'A'; 1096 *chip = AHC_AIC7870; 1097 *features = AHC_AIC7870_FE; 1098 return (0); 1099 } 1100 1101 static int 1102 ahc_aha394X_setup(struct pci_attach_args *pa, char *channel, 1103 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1104 { 1105 int error; 1106 1107 error = ahc_aic7870_setup(pa, channel, chip, features, flags); 1108 if (error == 0) 1109 error = ahc_aha394XX_setup(pa, channel, chip, features, flags); 1110 return (error); 1111 } 1112 1113 static int 1114 ahc_aha398X_setup(struct pci_attach_args *pa, char *channel, 1115 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1116 { 1117 int error; 1118 1119 error = ahc_aic7870_setup(pa, channel, chip, features, flags); 1120 if (error == 0) 1121 error = ahc_aha398XX_setup(pa, channel, chip, features, flags); 1122 return (error); 1123 } 1124 1125 static int 1126 ahc_aic7880_setup(struct pci_attach_args *pa, char *channel, 1127 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1128 { 1129 *channel = 'A'; 1130 *chip = AHC_AIC7880; 1131 *features = AHC_AIC7880_FE; 1132 return (0); 1133 } 1134 1135 static int 1136 ahc_2940Pro_setup(struct pci_attach_args *pa, char *channel, 1137 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1138 { 1139 int error; 1140 1141 *flags |= AHC_INT50_SPEEDFLEX; 1142 error = ahc_aic7880_setup(pa, channel, chip, features, flags); 1143 return (0); 1144 } 1145 1146 static int 1147 ahc_aha394XU_setup(struct pci_attach_args *pa, char *channel, 1148 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1149 { 1150 int error; 1151 1152 error = ahc_aic7880_setup(pa, channel, chip, features, flags); 1153 if (error == 0) 1154 error = ahc_aha394XX_setup(pa, channel, chip, features, flags); 1155 return (error); 1156 } 1157 1158 static int 1159 ahc_aha398XU_setup(struct pci_attach_args *pa, char *channel, 1160 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1161 { 1162 int error; 1163 1164 error = ahc_aic7880_setup(pa, channel, chip, features, flags); 1165 if (error == 0) 1166 error = ahc_aha398XX_setup(pa, channel, chip, features, flags); 1167 return (error); 1168 } 1169 1170 static int 1171 ahc_aic7890_setup(struct pci_attach_args *pa, char *channel, 1172 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1173 { 1174 *channel = 'A'; 1175 *chip = AHC_AIC7890; 1176 *features = AHC_AIC7890_FE; 1177 *flags |= AHC_NEWEEPROM_FMT; 1178 return (0); 1179 } 1180 1181 static int 1182 ahc_aic7892_setup(struct pci_attach_args *pa, char *channel, 1183 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1184 { 1185 *channel = 'A'; 1186 *chip = AHC_AIC7892; 1187 *features = AHC_AIC7892_FE; 1188 *flags |= AHC_NEWEEPROM_FMT; 1189 return (0); 1190 } 1191 1192 static int 1193 ahc_aic7895_setup(struct pci_attach_args *pa, char *channel, 1194 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1195 { 1196 pcireg_t devconfig; 1197 1198 *channel = pa->pa_function == 1 ? 'B' : 'A'; 1199 *chip = AHC_AIC7895; 1200 /* The 'C' revision of the aic7895 has a few additional features */ 1201 if (PCI_REVISION(pa->pa_class) >= 4) 1202 *features = AHC_AIC7895C_FE; 1203 else 1204 *features = AHC_AIC7895_FE; 1205 *flags |= AHC_NEWEEPROM_FMT; 1206 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 1207 devconfig &= ~SCBSIZE32; 1208 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); 1209 return (0); 1210 } 1211 1212 static int 1213 ahc_aic7896_setup(struct pci_attach_args *pa, char *channel, 1214 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1215 { 1216 *channel = pa->pa_function == 1 ? 'B' : 'A'; 1217 *chip = AHC_AIC7896; 1218 *features = AHC_AIC7896_FE; 1219 *flags |= AHC_NEWEEPROM_FMT; 1220 return (0); 1221 } 1222 1223 static int 1224 ahc_aic7899_setup(struct pci_attach_args *pa, char *channel, 1225 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1226 { 1227 *channel = pa->pa_function == 1 ? 'B' : 'A'; 1228 *chip = AHC_AIC7899; 1229 *features = AHC_AIC7899_FE; 1230 *flags |= AHC_NEWEEPROM_FMT; 1231 return (0); 1232 } 1233 1234 static int 1235 ahc_raid_setup(struct pci_attach_args *pa, char *channel, 1236 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1237 { 1238 printf(": RAID functionality unsupported\n"); 1239 return (ENXIO); 1240 } 1241 1242 static int 1243 ahc_aha394XX_setup(struct pci_attach_args *pa, char *channel, 1244 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1245 { 1246 switch (pa->pa_device) { 1247 case AHC_394X_SLOT_CHANNEL_A: 1248 *channel = 'A'; 1249 break; 1250 case AHC_394X_SLOT_CHANNEL_B: 1251 *channel = 'B'; 1252 break; 1253 default: 1254 printf("adapter at unexpected slot %d\n" 1255 "unable to map to a channel\n", 1256 pa->pa_device); 1257 *channel = 'A'; 1258 } 1259 return (0); 1260 } 1261 1262 static int 1263 ahc_aha398XX_setup(struct pci_attach_args *pa, char *channel, 1264 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1265 { 1266 switch (pa->pa_device) { 1267 case AHC_398X_SLOT_CHANNEL_A: 1268 *channel = 'A'; 1269 break; 1270 case AHC_398X_SLOT_CHANNEL_B: 1271 *channel = 'B'; 1272 break; 1273 case AHC_398X_SLOT_CHANNEL_C: 1274 *channel = 'C'; 1275 break; 1276 default: 1277 printf("adapter at unexpected slot %d\n" 1278 "unable to map to a channel\n", 1279 pa->pa_device); 1280 *channel = 'A'; 1281 } 1282 *flags |= AHC_LARGE_SEEPROM; 1283 return (0); 1284 } 1285
Indexes created Wed Oct 01 19:09:53 GMT 2025