ahc_pci.c revision 1.30
1 /* $NetBSD: ahc_pci.c,v 1.30 2001/03/24 02:04:40 christos Exp $ */ 2 3 /* 4 * Product specific probe and attach routines for: 5 * 3940, 2940, aic7895, aic7890, aic7880, 6 * aic7870, aic7860 and aic7850 SCSI controllers 7 * 8 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * Alternatively, this software may be distributed under the terms of the 21 * the GNU Public License ("GPL"). 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/aic7xxx/ahc_pci.c,v 1.28 2000/02/09 21:00:22 gibbs Exp $ 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/device.h> 44 #include <sys/reboot.h> 45 46 #include <machine/bus.h> 47 #include <machine/intr.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 52 /* XXXX some i386 on-board chips act weird when memory-mapped */ 53 #ifndef __i386__ 54 #define AHC_ALLOW_MEMIO 55 #endif 56 57 #define AHC_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 58 #define AHC_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 59 60 #include <dev/scsipi/scsi_all.h> 61 #include <dev/scsipi/scsipi_all.h> 62 #include <dev/scsipi/scsiconf.h> 63 64 #include <dev/ic/aic7xxxvar.h> 65 #include <dev/ic/smc93cx6var.h> 66 67 #include <dev/microcode/aic7xxx/aic7xxx_reg.h> 68 69 struct ahc_pci_busdata { 70 pci_chipset_tag_t pc; 71 pcitag_t tag; 72 u_int dev; 73 u_int func; 74 }; 75 76 static __inline u_int64_t 77 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 78 { 79 u_int64_t id; 80 81 id = subvendor 82 | (subdevice << 16) 83 | ((u_int64_t)vendor << 32) 84 | ((u_int64_t)device << 48); 85 86 return (id); 87 } 88 89 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 90 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 91 #define ID_AIC7850 0x5078900400000000ull 92 #define ID_AHA_2910_15_20_30C 0x5078900478509004ull 93 #define ID_AIC7855 0x5578900400000000ull 94 #define ID_AIC7859 0x3860900400000000ull 95 #define ID_AHA_2930CU 0x3860900438699004ull 96 #define ID_AIC7860 0x6078900400000000ull 97 #define ID_AIC7860C 0x6078900478609004ull 98 #define ID_AHA_2940AU_0 0x6178900400000000ull 99 #define ID_AHA_2940AU_1 0x6178900478619004ull 100 #define ID_AHA_2940AU_CN 0x2178900478219004ull 101 #define ID_AHA_2930C_VAR 0x6038900438689004ull 102 103 #define ID_AIC7870 0x7078900400000000ull 104 #define ID_AHA_2940 0x7178900400000000ull 105 #define ID_AHA_3940 0x7278900400000000ull 106 #define ID_AHA_398X 0x7378900400000000ull 107 #define ID_AHA_2944 0x7478900400000000ull 108 #define ID_AHA_3944 0x7578900400000000ull 109 110 #define ID_AIC7880 0x8078900400000000ull 111 #define ID_AIC7880_B 0x8078900478809004ull 112 #define ID_AHA_2940U 0x8178900400000000ull 113 #define ID_AHA_3940U 0x8278900400000000ull 114 #define ID_AHA_2944U 0x8478900400000000ull 115 #define ID_AHA_3944U 0x8578900400000000ull 116 #define ID_AHA_398XU 0x8378900400000000ull 117 #define ID_AHA_4944U 0x8678900400000000ull 118 #define ID_AHA_2940UB 0x8178900478819004ull 119 #define ID_AHA_2930U 0x8878900478889004ull 120 #define ID_AHA_2940U_PRO 0x8778900478879004ull 121 #define ID_AHA_2940U_CN 0x0078900478009004ull 122 123 #define ID_AIC7895 0x7895900478959004ull 124 #define ID_AIC7895_RAID_PORT 0x7893900478939004ull 125 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 126 #define ID_AHA_3940AU 0x7895900478929004ull 127 #define ID_AHA_3944AU 0x7895900478949004ull 128 129 #define ID_AIC7890 0x001F9005000F9005ull 130 #define ID_AAA_131U2 0x0013900500039005ull 131 #define ID_AHA_2930U2 0x0011900501819005ull 132 #define ID_AHA_2940U2B 0x00109005A1009005ull 133 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 134 #define ID_AHA_2940U2 0x00109005A1809005ull 135 #define ID_AHA_2950U2B 0x00109005E1009005ull 136 137 #define ID_AIC7892 0x008F9005FFFF9005ull 138 #define ID_AHA_29160 0x00809005E2A09005ull 139 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 140 #define ID_AHA_29160N 0x0080900562A09005ull 141 #define ID_AHA_29160B 0x00809005E2209005ull 142 #define ID_AHA_19160B 0x0081900562A19005ull 143 144 #define ID_AIC7896 0x005F9005FFFF9005ull 145 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 146 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 147 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 148 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 149 150 #define ID_AIC7899 0x00CF9005FFFF9005ull 151 #define ID_AHA_3960D 0x00C09005F6209005ull /* AKA AHA-39160 */ 152 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 153 154 #define ID_AIC7810 0x1078900400000000ull 155 #define ID_AIC7815 0x7815900400000000ull 156 157 typedef int (ahc_device_setup_t)(struct pci_attach_args *, char *, 158 ahc_chip *, ahc_feature *, ahc_flag *); 159 160 static ahc_device_setup_t ahc_aic7850_setup; 161 static ahc_device_setup_t ahc_aic7855_setup; 162 static ahc_device_setup_t ahc_aic7859_setup; 163 static ahc_device_setup_t ahc_aic7860_setup; 164 static ahc_device_setup_t ahc_aic7870_setup; 165 static ahc_device_setup_t ahc_aha394X_setup; 166 static ahc_device_setup_t ahc_aha398X_setup; 167 static ahc_device_setup_t ahc_aic7880_setup; 168 static ahc_device_setup_t ahc_2940Pro_setup; 169 static ahc_device_setup_t ahc_aha394XU_setup; 170 static ahc_device_setup_t ahc_aha398XU_setup; 171 static ahc_device_setup_t ahc_aic7890_setup; 172 static ahc_device_setup_t ahc_aic7892_setup; 173 static ahc_device_setup_t ahc_aic7895_setup; 174 static ahc_device_setup_t ahc_aic7896_setup; 175 static ahc_device_setup_t ahc_aic7899_setup; 176 static ahc_device_setup_t ahc_raid_setup; 177 static ahc_device_setup_t ahc_aha394XX_setup; 178 static ahc_device_setup_t ahc_aha398XX_setup; 179 180 struct ahc_pci_identity { 181 u_int64_t full_id; 182 u_int64_t id_mask; 183 const char *name; 184 ahc_device_setup_t *setup; 185 }; 186 187 const struct ahc_pci_identity ahc_pci_ident_table [] = 188 { 189 /* aic7850 based controllers */ 190 { 191 ID_AHA_2910_15_20_30C, 192 ID_ALL_MASK, 193 "Adaptec 2910/15/20/30C SCSI adapter", 194 ahc_aic7850_setup 195 }, 196 /* aic7859 based controllers */ 197 { 198 ID_AHA_2930CU, 199 ID_ALL_MASK, 200 "Adaptec 2930CU SCSI adapter", 201 ahc_aic7859_setup 202 }, 203 /* aic7860 based controllers */ 204 { 205 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 206 ID_DEV_VENDOR_MASK, 207 "Adaptec 2940A Ultra SCSI adapter", 208 ahc_aic7860_setup 209 }, 210 { 211 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 212 ID_DEV_VENDOR_MASK, 213 "Adaptec 2940A/CN Ultra SCSI adapter", 214 ahc_aic7860_setup 215 }, 216 { 217 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 218 ID_DEV_VENDOR_MASK, 219 "Adaptec 2930C SCSI adapter (VAR)", 220 ahc_aic7860_setup 221 }, 222 /* aic7870 based controllers */ 223 { 224 ID_AHA_2940, 225 ID_ALL_MASK, 226 "Adaptec 2940 SCSI adapter", 227 ahc_aic7870_setup 228 }, 229 { 230 ID_AHA_3940, 231 ID_ALL_MASK, 232 "Adaptec 3940 SCSI adapter", 233 ahc_aha394X_setup 234 }, 235 { 236 ID_AHA_398X, 237 ID_ALL_MASK, 238 "Adaptec 398X SCSI RAID adapter", 239 ahc_aha398X_setup 240 }, 241 { 242 ID_AHA_2944, 243 ID_ALL_MASK, 244 "Adaptec 2944 SCSI adapter", 245 ahc_aic7870_setup 246 }, 247 { 248 ID_AHA_3944, 249 ID_ALL_MASK, 250 "Adaptec 3944 SCSI adapter", 251 ahc_aha394X_setup 252 }, 253 /* aic7880 based controllers */ 254 { 255 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 256 ID_DEV_VENDOR_MASK, 257 "Adaptec 2940 Ultra SCSI adapter", 258 ahc_aic7880_setup 259 }, 260 { 261 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 262 ID_DEV_VENDOR_MASK, 263 "Adaptec 3940 Ultra SCSI adapter", 264 ahc_aha394XU_setup 265 }, 266 { 267 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 268 ID_DEV_VENDOR_MASK, 269 "Adaptec 2944 Ultra SCSI adapter", 270 ahc_aic7880_setup 271 }, 272 { 273 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 274 ID_DEV_VENDOR_MASK, 275 "Adaptec 3944 Ultra SCSI adapter", 276 ahc_aha394XU_setup 277 }, 278 { 279 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 280 ID_DEV_VENDOR_MASK, 281 "Adaptec 398X Ultra SCSI RAID adapter", 282 ahc_aha398XU_setup 283 }, 284 { 285 /* 286 * XXX Don't know the slot numbers 287 * so we can't identify channels 288 */ 289 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 290 ID_DEV_VENDOR_MASK, 291 "Adaptec 4944 Ultra SCSI adapter", 292 ahc_aic7880_setup 293 }, 294 { 295 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 296 ID_DEV_VENDOR_MASK, 297 "Adaptec 2930 Ultra SCSI adapter", 298 ahc_aic7880_setup 299 }, 300 { 301 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 302 ID_DEV_VENDOR_MASK, 303 "Adaptec 2940 Pro Ultra SCSI adapter", 304 ahc_2940Pro_setup 305 }, 306 { 307 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 308 ID_DEV_VENDOR_MASK, 309 "Adaptec 2940/CN Ultra SCSI adapter", 310 ahc_aic7880_setup 311 }, 312 /* aic7890 based controllers */ 313 { 314 ID_AHA_2930U2, 315 ID_ALL_MASK, 316 "Adaptec 2930 Ultra2 SCSI adapter", 317 ahc_aic7890_setup 318 }, 319 { 320 ID_AHA_2940U2B, 321 ID_ALL_MASK, 322 "Adaptec 2940B Ultra2 SCSI adapter", 323 ahc_aic7890_setup 324 }, 325 { 326 ID_AHA_2940U2_OEM, 327 ID_ALL_MASK, 328 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 329 ahc_aic7890_setup 330 }, 331 { 332 ID_AHA_2940U2, 333 ID_ALL_MASK, 334 "Adaptec 2940 Ultra2 SCSI adapter", 335 ahc_aic7890_setup 336 }, 337 { 338 ID_AHA_2950U2B, 339 ID_ALL_MASK, 340 "Adaptec 2950 Ultra2 SCSI adapter", 341 ahc_aic7890_setup 342 }, 343 { 344 ID_AAA_131U2, 345 ID_ALL_MASK, 346 "Adaptec AAA-131 Ultra2 RAID adapter", 347 ahc_aic7890_setup 348 }, 349 /* aic7892 based controllers */ 350 { 351 ID_AHA_29160, 352 ID_ALL_MASK, 353 "Adaptec 29160 Ultra160 SCSI adapter", 354 ahc_aic7892_setup 355 }, 356 { 357 ID_AHA_29160_CPQ, 358 ID_ALL_MASK, 359 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 360 ahc_aic7892_setup 361 }, 362 { 363 ID_AHA_29160N, 364 ID_ALL_MASK, 365 "Adaptec 29160N Ultra160 SCSI adapter", 366 ahc_aic7892_setup 367 }, 368 { 369 ID_AHA_29160B, 370 ID_ALL_MASK, 371 "Adaptec 29160B Ultra160 SCSI adapter", 372 ahc_aic7892_setup 373 }, 374 { 375 ID_AHA_19160B, 376 ID_ALL_MASK, 377 "Adaptec 19160B Ultra160 SCSI adapter", 378 ahc_aic7892_setup 379 }, 380 /* aic7895 based controllers */ 381 { 382 ID_AHA_2940U_DUAL, 383 ID_ALL_MASK, 384 "Adaptec 2940/DUAL Ultra SCSI adapter", 385 ahc_aic7895_setup 386 }, 387 { 388 ID_AHA_3940AU, 389 ID_ALL_MASK, 390 "Adaptec 3940A Ultra SCSI adapter", 391 ahc_aic7895_setup 392 }, 393 { 394 ID_AHA_3944AU, 395 ID_ALL_MASK, 396 "Adaptec 3944A Ultra SCSI adapter", 397 ahc_aic7895_setup 398 }, 399 /* aic7896/97 based controllers */ 400 { 401 ID_AHA_3950U2B_0, 402 ID_ALL_MASK, 403 "Adaptec 3950B Ultra2 SCSI adapter", 404 ahc_aic7896_setup 405 }, 406 { 407 ID_AHA_3950U2B_1, 408 ID_ALL_MASK, 409 "Adaptec 3950B Ultra2 SCSI adapter", 410 ahc_aic7896_setup 411 }, 412 { 413 ID_AHA_3950U2D_0, 414 ID_ALL_MASK, 415 "Adaptec 3950D Ultra2 SCSI adapter", 416 ahc_aic7896_setup 417 }, 418 { 419 ID_AHA_3950U2D_1, 420 ID_ALL_MASK, 421 "Adaptec 3950D Ultra2 SCSI adapter", 422 ahc_aic7896_setup 423 }, 424 /* aic7899 based controllers */ 425 { 426 ID_AHA_3960D, 427 ID_ALL_MASK, 428 "Adaptec 3960D Ultra160 SCSI adapter", 429 ahc_aic7899_setup 430 }, 431 { 432 ID_AHA_3960D_CPQ, 433 ID_ALL_MASK, 434 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 435 ahc_aic7899_setup 436 }, 437 /* Generic chip probes for devices we don't know 'exactly' */ 438 { 439 ID_AIC7850 & ID_DEV_VENDOR_MASK, 440 ID_DEV_VENDOR_MASK, 441 "Adaptec aic7850 SCSI adapter", 442 ahc_aic7850_setup 443 }, 444 { 445 ID_AIC7855 & ID_DEV_VENDOR_MASK, 446 ID_DEV_VENDOR_MASK, 447 "Adaptec aic7855 SCSI adapter", 448 ahc_aic7855_setup 449 }, 450 { 451 ID_AIC7859 & ID_DEV_VENDOR_MASK, 452 ID_DEV_VENDOR_MASK, 453 "Adaptec aic7859 SCSI adapter", 454 ahc_aic7859_setup 455 }, 456 { 457 ID_AIC7860 & ID_DEV_VENDOR_MASK, 458 ID_DEV_VENDOR_MASK, 459 "Adaptec aic7860 SCSI adapter", 460 ahc_aic7860_setup 461 }, 462 { 463 ID_AIC7870 & ID_DEV_VENDOR_MASK, 464 ID_DEV_VENDOR_MASK, 465 "Adaptec aic7870 SCSI adapter", 466 ahc_aic7870_setup 467 }, 468 { 469 ID_AIC7880 & ID_DEV_VENDOR_MASK, 470 ID_DEV_VENDOR_MASK, 471 "Adaptec aic7880 Ultra SCSI adapter", 472 ahc_aic7880_setup 473 }, 474 { 475 ID_AIC7890 & ID_DEV_VENDOR_MASK, 476 ID_DEV_VENDOR_MASK, 477 "Adaptec aic7890/91 Ultra2 SCSI adapter", 478 ahc_aic7890_setup 479 }, 480 { 481 ID_AIC7892 & ID_DEV_VENDOR_MASK, 482 ID_DEV_VENDOR_MASK, 483 "Adaptec aic7892 Ultra160 SCSI adapter", 484 ahc_aic7892_setup 485 }, 486 { 487 ID_AIC7895 & ID_DEV_VENDOR_MASK, 488 ID_DEV_VENDOR_MASK, 489 "Adaptec aic7895 Ultra SCSI adapter", 490 ahc_aic7895_setup 491 }, 492 { 493 ID_AIC7895_RAID_PORT & ID_DEV_VENDOR_MASK, 494 ID_DEV_VENDOR_MASK, 495 "Adaptec aic7895 Ultra SCSI adapter (RAID PORT)", 496 ahc_aic7895_setup 497 }, 498 { 499 ID_AIC7896 & ID_DEV_VENDOR_MASK, 500 ID_DEV_VENDOR_MASK, 501 "Adaptec aic7896/97 Ultra2 SCSI adapter", 502 ahc_aic7896_setup 503 }, 504 { 505 ID_AIC7899 & ID_DEV_VENDOR_MASK, 506 ID_DEV_VENDOR_MASK, 507 "Adaptec aic7899 Ultra160 SCSI adapter", 508 ahc_aic7899_setup 509 }, 510 { 511 ID_AIC7810 & ID_DEV_VENDOR_MASK, 512 ID_DEV_VENDOR_MASK, 513 "Adaptec aic7810 RAID memory controller", 514 ahc_raid_setup 515 }, 516 { 517 ID_AIC7815 & ID_DEV_VENDOR_MASK, 518 ID_DEV_VENDOR_MASK, 519 "Adaptec aic7815 RAID memory controller", 520 ahc_raid_setup 521 } 522 }; 523 524 static const int ahc_num_pci_devs = 525 sizeof(ahc_pci_ident_table) / sizeof(*ahc_pci_ident_table); 526 527 #define AHC_394X_SLOT_CHANNEL_A 4 528 #define AHC_394X_SLOT_CHANNEL_B 5 529 530 #define AHC_398X_SLOT_CHANNEL_A 4 531 #define AHC_398X_SLOT_CHANNEL_B 8 532 #define AHC_398X_SLOT_CHANNEL_C 12 533 534 #define DEVCONFIG 0x40 535 #define SCBSIZE32 0x00010000 /* aic789X only */ 536 #define MPORTMODE 0x00000400 /* aic7870 only */ 537 #define RAMPSM 0x00000200 /* aic7870 only */ 538 #define VOLSENSE 0x00000100 539 #define SCBRAMSEL 0x00000080 540 #define MRDCEN 0x00000040 541 #define EXTSCBTIME 0x00000020 /* aic7870 only */ 542 #define EXTSCBPEN 0x00000010 /* aic7870 only */ 543 #define BERREN 0x00000008 544 #define DACEN 0x00000004 545 #define STPWLEVEL 0x00000002 546 #define DIFACTNEGEN 0x00000001 /* aic7870 only */ 547 548 #define CSIZE_LATTIME 0x0c 549 #define CACHESIZE 0x0000003f /* only 5 bits */ 550 #define LATTIME 0x0000ff00 551 552 static const struct ahc_pci_identity *ahc_find_pci_device(pcireg_t, pcireg_t); 553 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 554 static void ahc_ext_scbram_config(struct ahc_softc *ahc, int enable, 555 int pcheck, int fast); 556 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 557 558 int ahc_pci_probe __P((struct device *, struct cfdata *, void *)); 559 void ahc_pci_attach __P((struct device *, struct device *, void *)); 560 561 /* Exported for use in the ahc_intr routine */ 562 int ahc_pci_intr(struct ahc_softc *ahc); 563 564 struct cfattach ahc_pci_ca = { 565 sizeof(struct ahc_softc), ahc_pci_probe, ahc_pci_attach 566 }; 567 568 static const struct ahc_pci_identity * 569 ahc_find_pci_device(id, subid) 570 pcireg_t id, subid; 571 { 572 u_int64_t full_id; 573 const struct ahc_pci_identity *entry; 574 u_int i; 575 576 full_id = ahc_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 577 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 578 579 for (i = 0; i < ahc_num_pci_devs; i++) { 580 entry = &ahc_pci_ident_table[i]; 581 if (entry->full_id == (full_id & entry->id_mask)) 582 return (entry); 583 } 584 return (NULL); 585 } 586 587 int 588 ahc_pci_probe(parent, match, aux) 589 struct device *parent; 590 struct cfdata *match; 591 void *aux; 592 { 593 struct pci_attach_args *pa = aux; 594 const struct ahc_pci_identity *entry; 595 pcireg_t subid; 596 597 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 598 entry = ahc_find_pci_device(pa->pa_id, subid); 599 return entry != NULL ? 1 : 0; 600 } 601 602 void 603 ahc_pci_attach(parent, self, aux) 604 struct device *parent, *self; 605 void *aux; 606 { 607 struct pci_attach_args *pa = aux; 608 const struct ahc_pci_identity *entry; 609 struct ahc_softc *ahc = (void *)self; 610 pcireg_t command; 611 ahc_chip ahc_t = AHC_NONE; 612 ahc_feature ahc_fe = AHC_FENONE; 613 ahc_flag ahc_f = AHC_FNONE; 614 u_int our_id = 0; 615 u_int sxfrctl1; 616 u_int scsiseq; 617 int error; 618 char channel; 619 pcireg_t subid; 620 int ioh_valid, memh_valid; 621 bus_space_tag_t st, iot; 622 bus_space_handle_t sh, ioh; 623 #ifdef AHC_ALLOW_MEMIO 624 bus_space_tag_t memt; 625 bus_space_handle_t memh; 626 pcireg_t memtype; 627 #endif 628 pci_intr_handle_t ih; 629 const char *intrstr; 630 struct ahc_pci_busdata *bd; 631 632 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 633 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 634 entry = ahc_find_pci_device(pa->pa_id, subid); 635 if (entry == NULL) 636 return; 637 error = entry->setup(pa, &channel, &ahc_t, &ahc_fe, &ahc_f); 638 if (error != 0) 639 return; 640 641 ioh_valid = memh_valid = 0; 642 643 #ifdef AHC_ALLOW_MEMIO 644 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHC_PCI_MEMADDR); 645 switch (memtype) { 646 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 647 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 648 memh_valid = (pci_mapreg_map(pa, AHC_PCI_MEMADDR, 649 memtype, 0, &memt, &memh, NULL, NULL) == 0); 650 break; 651 default: 652 memh_valid = 0; 653 } 654 #endif 655 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_IOADDR, 656 PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, NULL, NULL) == 0); 657 658 if (ioh_valid) { 659 st = iot; 660 sh = ioh; 661 #ifdef AHC_ALLOW_MEMIO 662 } else if (memh_valid) { 663 st = memt; 664 sh = memh; 665 #endif 666 } else { 667 printf(": unable to map registers\n"); 668 return; 669 } 670 671 printf("\n"); 672 673 674 /* Ensure busmastering is enabled */ 675 command |= PCI_COMMAND_MASTER_ENABLE;; 676 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 677 678 /* On all PCI adapters, we allow SCB paging */ 679 ahc_f |= AHC_PAGESCBS; 680 if (ahc_alloc(ahc, sh, st, pa->pa_dmat, 681 ahc_t|AHC_PCI, ahc_fe, ahc_f) < 0) 682 return; 683 684 bd = malloc(sizeof (struct ahc_pci_busdata), M_DEVBUF, M_NOWAIT); 685 if (bd == NULL) { 686 printf(": unable to allocate bus-specific data\n"); 687 return; 688 } 689 690 bd->pc = pa->pa_pc; 691 bd->tag = pa->pa_tag; 692 bd->func = pa->pa_function; 693 bd->dev = pa->pa_device; 694 695 ahc->bus_data = bd; 696 ahc->bus_intr = ahc_pci_intr; 697 ahc->channel = channel; 698 699 /* Remeber how the card was setup in case there is no SEEPROM */ 700 ahc_outb(ahc, HCNTRL, ahc->pause); 701 if ((ahc->features & AHC_ULTRA2) != 0) 702 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 703 else 704 our_id = ahc_inb(ahc, SCSIID) & OID; 705 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 706 scsiseq = ahc_inb(ahc, SCSISEQ); 707 708 if (ahc_reset(ahc) != 0) { 709 /* Failed */ 710 ahc_free(ahc); 711 return; 712 } 713 714 if ((ahc->features & AHC_DT) != 0) { 715 u_int optionmode; 716 u_int sfunct; 717 718 /* Perform ALT-Mode Setup */ 719 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 720 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 721 optionmode = ahc_inb(ahc, OPTIONMODE); 722 #ifdef DEBUG 723 printf("%s: OptionMode = %x\n", ahc->sc_dev.dv_xname, 724 optionmode); 725 #endif 726 ahc_outb(ahc, OPTIONMODE, OPTIONMODE_DEFAULTS); 727 /* Send CRC info in target mode every 4K */ 728 ahc_outb(ahc, TARGCRCCNT, 0); 729 ahc_outb(ahc, TARGCRCCNT + 1, 0x10); 730 ahc_outb(ahc, SFUNCT, sfunct); 731 732 /* Normal mode setup */ 733 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 734 |TARGCRCENDEN|TARGCRCCNTEN); 735 } 736 737 if (pci_intr_map(pa, &ih)) { 738 printf("%s: couldn't map interrupt\n", ahc->sc_dev.dv_xname); 739 ahc_free(ahc); 740 return; 741 } 742 intrstr = pci_intr_string(pa->pa_pc, ih); 743 ahc->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahc_intr, ahc); 744 if (ahc->ih == NULL) { 745 printf("%s: couldn't establish interrupt", 746 ahc->sc_dev.dv_xname); 747 if (intrstr != NULL) 748 printf(" at %s", intrstr); 749 printf("\n"); 750 ahc_free(ahc); 751 return; 752 } 753 if (intrstr != NULL) 754 printf("%s: interrupting at %s\n", ahc->sc_dev.dv_xname, 755 intrstr); 756 757 /* 758 * Do aic7880/aic7870/aic7860/aic7850 specific initialization 759 */ 760 { 761 u_int8_t sblkctl; 762 u_int dscommand0; 763 764 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 765 dscommand0 |= MPARCKEN; 766 if ((ahc->features & AHC_ULTRA2) != 0) { 767 768 /* 769 * DPARCKEN doesn't work correctly on 770 * some MBs so don't use it. 771 */ 772 dscommand0 &= ~(USCBSIZE32|DPARCKEN); 773 dscommand0 |= CACHETHEN; 774 } 775 776 ahc_outb(ahc, DSCOMMAND0, dscommand0); 777 778 /* See if we have an SEEPROM and perform auto-term */ 779 check_extport(ahc, &sxfrctl1); 780 781 /* 782 * Take the LED out of diagnostic mode 783 */ 784 sblkctl = ahc_inb(ahc, SBLKCTL); 785 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 786 787 /* 788 * I don't know where this is set in the SEEPROM or by the 789 * BIOS, so we default to 100% on Ultra or slower controllers 790 * and 75% on ULTRA2 controllers. 791 */ 792 if ((ahc->features & AHC_ULTRA2) != 0) { 793 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 794 } else { 795 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 796 } 797 798 if (ahc->flags & AHC_USEDEFAULTS) { 799 /* 800 * PCI Adapter default setup 801 * Should only be used if the adapter does not have 802 * an SEEPROM. 803 */ 804 /* See if someone else set us up already */ 805 if (scsiseq != 0) { 806 printf("%s: Using left over BIOS settings\n", 807 ahc_name(ahc)); 808 ahc->flags &= ~AHC_USEDEFAULTS; 809 } else { 810 /* 811 * Assume only one connector and always turn 812 * on termination. 813 */ 814 our_id = 0x07; 815 sxfrctl1 = STPWEN; 816 } 817 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 818 819 ahc->our_id = our_id; 820 } 821 } 822 823 /* 824 * Take a look to see if we have external SRAM. 825 * We currently do not attempt to use SRAM that is 826 * shared among multiple controllers. 827 */ 828 ahc_probe_ext_scbram(ahc); 829 830 831 printf("%s: %s ", ahc_name(ahc), 832 ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); 833 834 /* 835 * Record our termination setting for the 836 * generic initialization routine. 837 */ 838 if ((sxfrctl1 & STPWEN) != 0) 839 ahc->flags |= AHC_TERM_ENB_A; 840 841 if (ahc_init(ahc)) { 842 ahc_free(ahc); 843 return; 844 } 845 846 ahc_attach(ahc); 847 } 848 849 /* 850 * Test for the presense of external sram in an 851 * "unshared" configuration. 852 */ 853 static int 854 ahc_ext_scbram_present(struct ahc_softc *ahc) 855 { 856 int ramps; 857 int single_user; 858 pcireg_t devconfig; 859 struct ahc_pci_busdata *bd = ahc->bus_data; 860 861 devconfig = pci_conf_read(bd->pc, bd->tag, DEVCONFIG); 862 single_user = (devconfig & MPORTMODE) != 0; 863 864 if ((ahc->features & AHC_ULTRA2) != 0) 865 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 866 else if ((ahc->chip & AHC_CHIPID_MASK) >= AHC_AIC7870) 867 ramps = (devconfig & RAMPSM) != 0; 868 else 869 ramps = 0; 870 871 if (ramps && single_user) 872 return (1); 873 return (0); 874 } 875 876 /* 877 * Enable external scbram. 878 */ 879 static void 880 ahc_ext_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, int fast) 881 { 882 pcireg_t devconfig; 883 struct ahc_pci_busdata *bd = ahc->bus_data; 884 885 if (ahc->features & AHC_MULTI_FUNC) { 886 /* 887 * Set the SCB Base addr (highest address bit) 888 * depending on which channel we are. 889 */ 890 ahc_outb(ahc, SCBBADDR, (u_int8_t)bd->func); 891 } 892 893 devconfig = pci_conf_read(bd->pc, bd->tag, DEVCONFIG); 894 if ((ahc->features & AHC_ULTRA2) != 0) { 895 u_int dscommand0; 896 897 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 898 if (enable) 899 dscommand0 &= ~INTSCBRAMSEL; 900 else 901 dscommand0 |= INTSCBRAMSEL; 902 ahc_outb(ahc, DSCOMMAND0, dscommand0); 903 } else { 904 if (fast) 905 devconfig &= ~EXTSCBTIME; 906 else 907 devconfig |= EXTSCBTIME; 908 if (enable) 909 devconfig &= ~SCBRAMSEL; 910 else 911 devconfig |= SCBRAMSEL; 912 } 913 if (pcheck) 914 devconfig |= EXTSCBPEN; 915 else 916 devconfig &= ~EXTSCBPEN; 917 918 pci_conf_write(bd->pc, bd->tag, DEVCONFIG, devconfig); 919 } 920 921 /* 922 * Take a look to see if we have external SRAM. 923 * We currently do not attempt to use SRAM that is 924 * shared among multiple controllers. 925 */ 926 static void 927 ahc_probe_ext_scbram(struct ahc_softc *ahc) 928 { 929 int num_scbs; 930 int test_num_scbs; 931 int enable; 932 int pcheck; 933 int fast; 934 935 if (ahc_ext_scbram_present(ahc) == 0) 936 return; 937 938 /* 939 * Probe for the best parameters to use. 940 */ 941 enable = FALSE; 942 pcheck = FALSE; 943 fast = FALSE; 944 ahc_ext_scbram_config(ahc, /*enable*/TRUE, pcheck, fast); 945 num_scbs = ahc_probe_scbs(ahc); 946 if (num_scbs == 0) { 947 /* The SRAM wasn't really present. */ 948 goto done; 949 } 950 enable = TRUE; 951 952 /* 953 * Clear any outstanding parity error 954 * and ensure that parity error reporting 955 * is enabled. 956 */ 957 ahc_outb(ahc, SEQCTL, 0); 958 ahc_outb(ahc, CLRINT, CLRPARERR); 959 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 960 961 /* Now see if we can do parity */ 962 ahc_ext_scbram_config(ahc, enable, /*pcheck*/TRUE, fast); 963 num_scbs = ahc_probe_scbs(ahc); 964 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 965 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 966 pcheck = TRUE; 967 968 /* Clear any resulting parity error */ 969 ahc_outb(ahc, CLRINT, CLRPARERR); 970 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 971 972 /* Now see if we can do fast timing */ 973 ahc_ext_scbram_config(ahc, enable, pcheck, /*fast*/TRUE); 974 test_num_scbs = ahc_probe_scbs(ahc); 975 if (test_num_scbs == num_scbs 976 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 977 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 978 fast = TRUE; 979 980 done: 981 /* 982 * Disable parity error reporting until we 983 * can load instruction ram. 984 */ 985 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 986 /* Clear any latched parity error */ 987 ahc_outb(ahc, CLRINT, CLRPARERR); 988 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 989 if (bootverbose && enable) { 990 printf("%s: External SRAM, %s access%s\n", 991 ahc_name(ahc), fast ? "fast" : "slow", 992 pcheck ? ", parity checking enabled" : ""); 993 994 } 995 ahc_ext_scbram_config(ahc, enable, pcheck, fast); 996 } 997 998 #define DPE PCI_STATUS_PARITY_DETECT 999 #define SSE PCI_STATUS_SPECIAL_ERROR 1000 #define RMA PCI_STATUS_MASTER_ABORT 1001 #define RTA PCI_STATUS_MASTER_TARGET_ABORT 1002 #define STA PCI_STATUS_TARGET_TARGET_ABORT 1003 #define DPR PCI_STATUS_PARITY_ERROR 1004 1005 int 1006 ahc_pci_intr(struct ahc_softc *ahc) 1007 { 1008 pcireg_t status1; 1009 struct ahc_pci_busdata *bd = ahc->bus_data; 1010 1011 if ((ahc_inb(ahc, ERROR) & PCIERRSTAT) == 0) 1012 return 0; 1013 1014 status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 1015 1016 if (status1 & DPE) { 1017 printf("%s: Data Parity Error Detected during address " 1018 "or write data phase\n", ahc_name(ahc)); 1019 } 1020 if (status1 & SSE) { 1021 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1022 } 1023 if (status1 & RMA) { 1024 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1025 } 1026 if (status1 & RTA) { 1027 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1028 } 1029 if (status1 & STA) { 1030 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1031 } 1032 if (status1 & DPR) { 1033 printf("%s: Data Parity Error has been reported via PERR#\n", 1034 ahc_name(ahc)); 1035 } 1036 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1037 printf("%s: Latched PCIERR interrupt with " 1038 "no status bits set\n", ahc_name(ahc)); 1039 } 1040 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, status1); 1041 1042 if (status1 & (DPR|RMA|RTA)) { 1043 ahc_outb(ahc, CLRINT, CLRPARERR); 1044 } 1045 1046 return 1; 1047 } 1048 1049 static int 1050 ahc_aic7850_setup(struct pci_attach_args *pa, char *channel, 1051 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1052 { 1053 *channel = 'A'; 1054 *chip = AHC_AIC7850; 1055 *features = AHC_AIC7850_FE; 1056 return (0); 1057 } 1058 1059 static int 1060 ahc_aic7855_setup(struct pci_attach_args *pa, char *channel, 1061 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1062 { 1063 *channel = 'A'; 1064 *chip = AHC_AIC7855; 1065 *features = AHC_AIC7855_FE; 1066 return (0); 1067 } 1068 1069 static int 1070 ahc_aic7859_setup(struct pci_attach_args *pa, char *channel, 1071 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1072 { 1073 *channel = 'A'; 1074 *chip = AHC_AIC7859; 1075 *features = AHC_AIC7859_FE; 1076 return (0); 1077 } 1078 1079 static int 1080 ahc_aic7860_setup(struct pci_attach_args *pa, char *channel, 1081 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1082 { 1083 *channel = 'A'; 1084 *chip = AHC_AIC7860; 1085 *features = AHC_AIC7860_FE; 1086 return (0); 1087 } 1088 1089 static int 1090 ahc_aic7870_setup(struct pci_attach_args *pa, char *channel, 1091 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1092 { 1093 *channel = 'A'; 1094 *chip = AHC_AIC7870; 1095 *features = AHC_AIC7870_FE; 1096 return (0); 1097 } 1098 1099 static int 1100 ahc_aha394X_setup(struct pci_attach_args *pa, char *channel, 1101 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1102 { 1103 int error; 1104 1105 error = ahc_aic7870_setup(pa, channel, chip, features, flags); 1106 if (error == 0) 1107 error = ahc_aha394XX_setup(pa, channel, chip, features, flags); 1108 return (error); 1109 } 1110 1111 static int 1112 ahc_aha398X_setup(struct pci_attach_args *pa, char *channel, 1113 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1114 { 1115 int error; 1116 1117 error = ahc_aic7870_setup(pa, channel, chip, features, flags); 1118 if (error == 0) 1119 error = ahc_aha398XX_setup(pa, channel, chip, features, flags); 1120 return (error); 1121 } 1122 1123 static int 1124 ahc_aic7880_setup(struct pci_attach_args *pa, char *channel, 1125 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1126 { 1127 *channel = 'A'; 1128 *chip = AHC_AIC7880; 1129 *features = AHC_AIC7880_FE; 1130 return (0); 1131 } 1132 1133 static int 1134 ahc_2940Pro_setup(struct pci_attach_args *pa, char *channel, 1135 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1136 { 1137 int error; 1138 1139 *flags |= AHC_INT50_SPEEDFLEX; 1140 error = ahc_aic7880_setup(pa, channel, chip, features, flags); 1141 return (0); 1142 } 1143 1144 static int 1145 ahc_aha394XU_setup(struct pci_attach_args *pa, char *channel, 1146 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1147 { 1148 int error; 1149 1150 error = ahc_aic7880_setup(pa, channel, chip, features, flags); 1151 if (error == 0) 1152 error = ahc_aha394XX_setup(pa, channel, chip, features, flags); 1153 return (error); 1154 } 1155 1156 static int 1157 ahc_aha398XU_setup(struct pci_attach_args *pa, char *channel, 1158 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1159 { 1160 int error; 1161 1162 error = ahc_aic7880_setup(pa, channel, chip, features, flags); 1163 if (error == 0) 1164 error = ahc_aha398XX_setup(pa, channel, chip, features, flags); 1165 return (error); 1166 } 1167 1168 static int 1169 ahc_aic7890_setup(struct pci_attach_args *pa, char *channel, 1170 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1171 { 1172 *channel = 'A'; 1173 *chip = AHC_AIC7890; 1174 *features = AHC_AIC7890_FE; 1175 *flags |= AHC_NEWEEPROM_FMT; 1176 return (0); 1177 } 1178 1179 static int 1180 ahc_aic7892_setup(struct pci_attach_args *pa, char *channel, 1181 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1182 { 1183 *channel = 'A'; 1184 *chip = AHC_AIC7892; 1185 *features = AHC_AIC7892_FE; 1186 *flags |= AHC_NEWEEPROM_FMT; 1187 return (0); 1188 } 1189 1190 static int 1191 ahc_aic7895_setup(struct pci_attach_args *pa, char *channel, 1192 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1193 { 1194 pcireg_t devconfig; 1195 1196 *channel = pa->pa_function == 1 ? 'B' : 'A'; 1197 *chip = AHC_AIC7895; 1198 /* The 'C' revision of the aic7895 has a few additional features */ 1199 if (PCI_REVISION(pa->pa_class) >= 4) 1200 *features = AHC_AIC7895C_FE; 1201 else 1202 *features = AHC_AIC7895_FE; 1203 *flags |= AHC_NEWEEPROM_FMT; 1204 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 1205 devconfig &= ~SCBSIZE32; 1206 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); 1207 return (0); 1208 } 1209 1210 static int 1211 ahc_aic7896_setup(struct pci_attach_args *pa, char *channel, 1212 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1213 { 1214 *channel = pa->pa_function == 1 ? 'B' : 'A'; 1215 *chip = AHC_AIC7896; 1216 *features = AHC_AIC7896_FE; 1217 *flags |= AHC_NEWEEPROM_FMT; 1218 return (0); 1219 } 1220 1221 static int 1222 ahc_aic7899_setup(struct pci_attach_args *pa, char *channel, 1223 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1224 { 1225 *channel = pa->pa_function == 1 ? 'B' : 'A'; 1226 *chip = AHC_AIC7899; 1227 *features = AHC_AIC7899_FE; 1228 *flags |= AHC_NEWEEPROM_FMT; 1229 return (0); 1230 } 1231 1232 static int 1233 ahc_raid_setup(struct pci_attach_args *pa, char *channel, 1234 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1235 { 1236 printf(": RAID functionality unsupported\n"); 1237 return (ENXIO); 1238 } 1239 1240 static int 1241 ahc_aha394XX_setup(struct pci_attach_args *pa, char *channel, 1242 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1243 { 1244 switch (pa->pa_device) { 1245 case AHC_394X_SLOT_CHANNEL_A: 1246 *channel = 'A'; 1247 break; 1248 case AHC_394X_SLOT_CHANNEL_B: 1249 *channel = 'B'; 1250 break; 1251 default: 1252 printf("adapter at unexpected slot %d\n" 1253 "unable to map to a channel\n", 1254 pa->pa_device); 1255 *channel = 'A'; 1256 } 1257 return (0); 1258 } 1259 1260 static int 1261 ahc_aha398XX_setup(struct pci_attach_args *pa, char *channel, 1262 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1263 { 1264 switch (pa->pa_device) { 1265 case AHC_398X_SLOT_CHANNEL_A: 1266 *channel = 'A'; 1267 break; 1268 case AHC_398X_SLOT_CHANNEL_B: 1269 *channel = 'B'; 1270 break; 1271 case AHC_398X_SLOT_CHANNEL_C: 1272 *channel = 'C'; 1273 break; 1274 default: 1275 printf("adapter at unexpected slot %d\n" 1276 "unable to map to a channel\n", 1277 pa->pa_device); 1278 *channel = 'A'; 1279 } 1280 *flags |= AHC_LARGE_SEEPROM; 1281 return (0); 1282 } 1283
Indexes created Wed Oct 01 19:09:53 GMT 2025