ahc_pci.c revision 1.32.10.1
1 /* $NetBSD: ahc_pci.c,v 1.32.10.1 2003/08/23 06:44:46 tron Exp $ */ 2 3 /* 4 * Product specific probe and attach routines for: 5 * 3940, 2940, aic7895, aic7890, aic7880, 6 * aic7870, aic7860 and aic7850 SCSI controllers 7 * 8 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * Alternatively, this software may be distributed under the terms of the 21 * the GNU Public License ("GPL"). 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/aic7xxx/ahc_pci.c,v 1.28 2000/02/09 21:00:22 gibbs Exp $ 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ahc_pci.c,v 1.32.10.1 2003/08/23 06:44:46 tron Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/queue.h> 46 #include <sys/device.h> 47 #include <sys/reboot.h> 48 49 #include <machine/bus.h> 50 #include <machine/intr.h> 51 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 55 /* XXXX some i386 on-board chips act weird when memory-mapped */ 56 #ifndef __i386__ 57 #define AHC_ALLOW_MEMIO 58 #endif 59 60 #define AHC_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 61 #define AHC_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 62 63 #include <dev/scsipi/scsi_all.h> 64 #include <dev/scsipi/scsipi_all.h> 65 #include <dev/scsipi/scsiconf.h> 66 67 #include <dev/ic/aic7xxxvar.h> 68 #include <dev/ic/smc93cx6var.h> 69 70 #include <dev/microcode/aic7xxx/aic7xxx_reg.h> 71 72 struct ahc_pci_busdata { 73 pci_chipset_tag_t pc; 74 pcitag_t tag; 75 u_int dev; 76 u_int func; 77 }; 78 79 static __inline u_int64_t 80 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 81 { 82 u_int64_t id; 83 84 id = subvendor 85 | (subdevice << 16) 86 | ((u_int64_t)vendor << 32) 87 | ((u_int64_t)device << 48); 88 89 return (id); 90 } 91 92 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 93 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 94 #define ID_AIC7850 0x5078900400000000ull 95 #define ID_AHA_2910_15_20_30C 0x5078900478509004ull 96 #define ID_AIC7855 0x5578900400000000ull 97 #define ID_AIC7859 0x3860900400000000ull 98 #define ID_AHA_2930CU 0x3860900438699004ull 99 #define ID_AIC7860 0x6078900400000000ull 100 #define ID_AIC7860C 0x6078900478609004ull 101 #define ID_AHA_2940AU_0 0x6178900400000000ull 102 #define ID_AHA_2940AU_1 0x6178900478619004ull 103 #define ID_AHA_2940AU_CN 0x2178900478219004ull 104 #define ID_AHA_2930C_VAR 0x6038900438689004ull 105 106 #define ID_AIC7870 0x7078900400000000ull 107 #define ID_AHA_2940 0x7178900400000000ull 108 #define ID_AHA_3940 0x7278900400000000ull 109 #define ID_AHA_398X 0x7378900400000000ull 110 #define ID_AHA_2944 0x7478900400000000ull 111 #define ID_AHA_3944 0x7578900400000000ull 112 113 #define ID_AIC7880 0x8078900400000000ull 114 #define ID_AIC7880_B 0x8078900478809004ull 115 #define ID_AHA_2940U 0x8178900400000000ull 116 #define ID_AHA_3940U 0x8278900400000000ull 117 #define ID_AHA_2944U 0x8478900400000000ull 118 #define ID_AHA_3944U 0x8578900400000000ull 119 #define ID_AHA_398XU 0x8378900400000000ull 120 #define ID_AHA_4944U 0x8678900400000000ull 121 #define ID_AHA_2940UB 0x8178900478819004ull 122 #define ID_AHA_2930U 0x8878900478889004ull 123 #define ID_AHA_2940U_PRO 0x8778900478879004ull 124 #define ID_AHA_2940U_CN 0x0078900478009004ull 125 126 #define ID_AIC7895 0x7895900478959004ull 127 #define ID_AIC7895_RAID_PORT 0x7893900478939004ull 128 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 129 #define ID_AHA_3940AU 0x7895900478929004ull 130 #define ID_AHA_3944AU 0x7895900478949004ull 131 132 #define ID_AIC7890 0x001F9005000F9005ull 133 #define ID_AAA_131U2 0x0013900500039005ull 134 #define ID_AHA_2930U2 0x0011900501819005ull 135 #define ID_AHA_2940U2B 0x00109005A1009005ull 136 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 137 #define ID_AHA_2940U2 0x00109005A1809005ull 138 #define ID_AHA_2950U2B 0x00109005E1009005ull 139 140 #define ID_AIC7892 0x008F9005FFFF9005ull 141 #define ID_AHA_2915LP 0x0082900502109005ull 142 #define ID_AHA_29160 0x00809005E2A09005ull 143 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 144 #define ID_AHA_29160N 0x0080900562A09005ull 145 #define ID_AHA_29160B 0x00809005E2209005ull 146 #define ID_AHA_19160B 0x0081900562A19005ull 147 148 #define ID_AIC7896 0x005F9005FFFF9005ull 149 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 150 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 151 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 152 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 153 154 #define ID_AIC7899 0x00CF9005FFFF9005ull 155 #define ID_AHA_3960D 0x00C09005F6209005ull /* AKA AHA-39160 */ 156 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 157 158 #define ID_AIC7810 0x1078900400000000ull 159 #define ID_AIC7815 0x7815900400000000ull 160 161 typedef int (ahc_device_setup_t)(struct pci_attach_args *, char *, 162 ahc_chip *, ahc_feature *, ahc_flag *); 163 164 static ahc_device_setup_t ahc_aic7850_setup; 165 static ahc_device_setup_t ahc_aic7855_setup; 166 static ahc_device_setup_t ahc_aic7859_setup; 167 static ahc_device_setup_t ahc_aic7860_setup; 168 static ahc_device_setup_t ahc_aic7870_setup; 169 static ahc_device_setup_t ahc_aha394X_setup; 170 static ahc_device_setup_t ahc_aha398X_setup; 171 static ahc_device_setup_t ahc_aic7880_setup; 172 static ahc_device_setup_t ahc_2940Pro_setup; 173 static ahc_device_setup_t ahc_aha394XU_setup; 174 static ahc_device_setup_t ahc_aha398XU_setup; 175 static ahc_device_setup_t ahc_aic7890_setup; 176 static ahc_device_setup_t ahc_aic7892_setup; 177 static ahc_device_setup_t ahc_aic7895_setup; 178 static ahc_device_setup_t ahc_aic7896_setup; 179 static ahc_device_setup_t ahc_aic7899_setup; 180 static ahc_device_setup_t ahc_raid_setup; 181 static ahc_device_setup_t ahc_aha394XX_setup; 182 static ahc_device_setup_t ahc_aha398XX_setup; 183 184 struct ahc_pci_identity { 185 u_int64_t full_id; 186 u_int64_t id_mask; 187 const char *name; 188 ahc_device_setup_t *setup; 189 }; 190 191 const struct ahc_pci_identity ahc_pci_ident_table [] = 192 { 193 /* aic7850 based controllers */ 194 { 195 ID_AHA_2910_15_20_30C, 196 ID_ALL_MASK, 197 "Adaptec 2910/15/20/30C SCSI adapter", 198 ahc_aic7850_setup 199 }, 200 /* aic7859 based controllers */ 201 { 202 ID_AHA_2930CU, 203 ID_ALL_MASK, 204 "Adaptec 2930CU SCSI adapter", 205 ahc_aic7859_setup 206 }, 207 /* aic7860 based controllers */ 208 { 209 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 210 ID_DEV_VENDOR_MASK, 211 "Adaptec 2940A Ultra SCSI adapter", 212 ahc_aic7860_setup 213 }, 214 { 215 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 216 ID_DEV_VENDOR_MASK, 217 "Adaptec 2940A/CN Ultra SCSI adapter", 218 ahc_aic7860_setup 219 }, 220 { 221 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 222 ID_DEV_VENDOR_MASK, 223 "Adaptec 2930C SCSI adapter (VAR)", 224 ahc_aic7860_setup 225 }, 226 /* aic7870 based controllers */ 227 { 228 ID_AHA_2940, 229 ID_ALL_MASK, 230 "Adaptec 2940 SCSI adapter", 231 ahc_aic7870_setup 232 }, 233 { 234 ID_AHA_3940, 235 ID_ALL_MASK, 236 "Adaptec 3940 SCSI adapter", 237 ahc_aha394X_setup 238 }, 239 { 240 ID_AHA_398X, 241 ID_ALL_MASK, 242 "Adaptec 398X SCSI RAID adapter", 243 ahc_aha398X_setup 244 }, 245 { 246 ID_AHA_2944, 247 ID_ALL_MASK, 248 "Adaptec 2944 SCSI adapter", 249 ahc_aic7870_setup 250 }, 251 { 252 ID_AHA_3944, 253 ID_ALL_MASK, 254 "Adaptec 3944 SCSI adapter", 255 ahc_aha394X_setup 256 }, 257 /* aic7880 based controllers */ 258 { 259 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 260 ID_DEV_VENDOR_MASK, 261 "Adaptec 2940 Ultra SCSI adapter", 262 ahc_aic7880_setup 263 }, 264 { 265 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 266 ID_DEV_VENDOR_MASK, 267 "Adaptec 3940 Ultra SCSI adapter", 268 ahc_aha394XU_setup 269 }, 270 { 271 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 272 ID_DEV_VENDOR_MASK, 273 "Adaptec 2944 Ultra SCSI adapter", 274 ahc_aic7880_setup 275 }, 276 { 277 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 278 ID_DEV_VENDOR_MASK, 279 "Adaptec 3944 Ultra SCSI adapter", 280 ahc_aha394XU_setup 281 }, 282 { 283 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 284 ID_DEV_VENDOR_MASK, 285 "Adaptec 398X Ultra SCSI RAID adapter", 286 ahc_aha398XU_setup 287 }, 288 { 289 /* 290 * XXX Don't know the slot numbers 291 * so we can't identify channels 292 */ 293 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 294 ID_DEV_VENDOR_MASK, 295 "Adaptec 4944 Ultra SCSI adapter", 296 ahc_aic7880_setup 297 }, 298 { 299 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 300 ID_DEV_VENDOR_MASK, 301 "Adaptec 2930 Ultra SCSI adapter", 302 ahc_aic7880_setup 303 }, 304 { 305 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 306 ID_DEV_VENDOR_MASK, 307 "Adaptec 2940 Pro Ultra SCSI adapter", 308 ahc_2940Pro_setup 309 }, 310 { 311 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 312 ID_DEV_VENDOR_MASK, 313 "Adaptec 2940/CN Ultra SCSI adapter", 314 ahc_aic7880_setup 315 }, 316 /* aic7890 based controllers */ 317 { 318 ID_AHA_2930U2, 319 ID_ALL_MASK, 320 "Adaptec 2930 Ultra2 SCSI adapter", 321 ahc_aic7890_setup 322 }, 323 { 324 ID_AHA_2940U2B, 325 ID_ALL_MASK, 326 "Adaptec 2940B Ultra2 SCSI adapter", 327 ahc_aic7890_setup 328 }, 329 { 330 ID_AHA_2940U2_OEM, 331 ID_ALL_MASK, 332 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 333 ahc_aic7890_setup 334 }, 335 { 336 ID_AHA_2940U2, 337 ID_ALL_MASK, 338 "Adaptec 2940 Ultra2 SCSI adapter", 339 ahc_aic7890_setup 340 }, 341 { 342 ID_AHA_2950U2B, 343 ID_ALL_MASK, 344 "Adaptec 2950 Ultra2 SCSI adapter", 345 ahc_aic7890_setup 346 }, 347 { 348 ID_AAA_131U2, 349 ID_ALL_MASK, 350 "Adaptec AAA-131 Ultra2 RAID adapter", 351 ahc_aic7890_setup 352 }, 353 /* aic7892 based controllers */ 354 { 355 ID_AHA_29160, 356 ID_ALL_MASK, 357 "Adaptec 29160 Ultra160 SCSI adapter", 358 ahc_aic7892_setup 359 }, 360 { 361 ID_AHA_29160_CPQ, 362 ID_ALL_MASK, 363 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 364 ahc_aic7892_setup 365 }, 366 { 367 ID_AHA_29160N, 368 ID_ALL_MASK, 369 "Adaptec 29160N Ultra160 SCSI adapter", 370 ahc_aic7892_setup 371 }, 372 { 373 ID_AHA_29160B, 374 ID_ALL_MASK, 375 "Adaptec 29160B Ultra160 SCSI adapter", 376 ahc_aic7892_setup 377 }, 378 { 379 ID_AHA_19160B, 380 ID_ALL_MASK, 381 "Adaptec 19160B Ultra160 SCSI adapter", 382 ahc_aic7892_setup 383 }, 384 { 385 ID_AHA_2915LP, 386 ID_ALL_MASK, 387 "Adaptec 2915LP Ultra160 SCSI adapter", 388 ahc_aic7892_setup 389 }, 390 /* aic7895 based controllers */ 391 { 392 ID_AHA_2940U_DUAL, 393 ID_ALL_MASK, 394 "Adaptec 2940/DUAL Ultra SCSI adapter", 395 ahc_aic7895_setup 396 }, 397 { 398 ID_AHA_3940AU, 399 ID_ALL_MASK, 400 "Adaptec 3940A Ultra SCSI adapter", 401 ahc_aic7895_setup 402 }, 403 { 404 ID_AHA_3944AU, 405 ID_ALL_MASK, 406 "Adaptec 3944A Ultra SCSI adapter", 407 ahc_aic7895_setup 408 }, 409 /* aic7896/97 based controllers */ 410 { 411 ID_AHA_3950U2B_0, 412 ID_ALL_MASK, 413 "Adaptec 3950B Ultra2 SCSI adapter", 414 ahc_aic7896_setup 415 }, 416 { 417 ID_AHA_3950U2B_1, 418 ID_ALL_MASK, 419 "Adaptec 3950B Ultra2 SCSI adapter", 420 ahc_aic7896_setup 421 }, 422 { 423 ID_AHA_3950U2D_0, 424 ID_ALL_MASK, 425 "Adaptec 3950D Ultra2 SCSI adapter", 426 ahc_aic7896_setup 427 }, 428 { 429 ID_AHA_3950U2D_1, 430 ID_ALL_MASK, 431 "Adaptec 3950D Ultra2 SCSI adapter", 432 ahc_aic7896_setup 433 }, 434 /* aic7899 based controllers */ 435 { 436 ID_AHA_3960D, 437 ID_ALL_MASK, 438 "Adaptec 3960D Ultra160 SCSI adapter", 439 ahc_aic7899_setup 440 }, 441 { 442 ID_AHA_3960D_CPQ, 443 ID_ALL_MASK, 444 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 445 ahc_aic7899_setup 446 }, 447 /* Generic chip probes for devices we don't know 'exactly' */ 448 { 449 ID_AIC7850 & ID_DEV_VENDOR_MASK, 450 ID_DEV_VENDOR_MASK, 451 "Adaptec aic7850 SCSI adapter", 452 ahc_aic7850_setup 453 }, 454 { 455 ID_AIC7855 & ID_DEV_VENDOR_MASK, 456 ID_DEV_VENDOR_MASK, 457 "Adaptec aic7855 SCSI adapter", 458 ahc_aic7855_setup 459 }, 460 { 461 ID_AIC7859 & ID_DEV_VENDOR_MASK, 462 ID_DEV_VENDOR_MASK, 463 "Adaptec aic7859 SCSI adapter", 464 ahc_aic7859_setup 465 }, 466 { 467 ID_AIC7860 & ID_DEV_VENDOR_MASK, 468 ID_DEV_VENDOR_MASK, 469 "Adaptec aic7860 SCSI adapter", 470 ahc_aic7860_setup 471 }, 472 { 473 ID_AIC7870 & ID_DEV_VENDOR_MASK, 474 ID_DEV_VENDOR_MASK, 475 "Adaptec aic7870 SCSI adapter", 476 ahc_aic7870_setup 477 }, 478 { 479 ID_AIC7880 & ID_DEV_VENDOR_MASK, 480 ID_DEV_VENDOR_MASK, 481 "Adaptec aic7880 Ultra SCSI adapter", 482 ahc_aic7880_setup 483 }, 484 { 485 ID_AIC7890 & ID_DEV_VENDOR_MASK, 486 ID_DEV_VENDOR_MASK, 487 "Adaptec aic7890/91 Ultra2 SCSI adapter", 488 ahc_aic7890_setup 489 }, 490 { 491 ID_AIC7892 & ID_DEV_VENDOR_MASK, 492 ID_DEV_VENDOR_MASK, 493 "Adaptec aic7892 Ultra160 SCSI adapter", 494 ahc_aic7892_setup 495 }, 496 { 497 ID_AIC7895 & ID_DEV_VENDOR_MASK, 498 ID_DEV_VENDOR_MASK, 499 "Adaptec aic7895 Ultra SCSI adapter", 500 ahc_aic7895_setup 501 }, 502 { 503 ID_AIC7895_RAID_PORT & ID_DEV_VENDOR_MASK, 504 ID_DEV_VENDOR_MASK, 505 "Adaptec aic7895 Ultra SCSI adapter (RAID PORT)", 506 ahc_aic7895_setup 507 }, 508 { 509 ID_AIC7896 & ID_DEV_VENDOR_MASK, 510 ID_DEV_VENDOR_MASK, 511 "Adaptec aic7896/97 Ultra2 SCSI adapter", 512 ahc_aic7896_setup 513 }, 514 { 515 ID_AIC7899 & ID_DEV_VENDOR_MASK, 516 ID_DEV_VENDOR_MASK, 517 "Adaptec aic7899 Ultra160 SCSI adapter", 518 ahc_aic7899_setup 519 }, 520 { 521 ID_AIC7810 & ID_DEV_VENDOR_MASK, 522 ID_DEV_VENDOR_MASK, 523 "Adaptec aic7810 RAID memory controller", 524 ahc_raid_setup 525 }, 526 { 527 ID_AIC7815 & ID_DEV_VENDOR_MASK, 528 ID_DEV_VENDOR_MASK, 529 "Adaptec aic7815 RAID memory controller", 530 ahc_raid_setup 531 } 532 }; 533 534 static const int ahc_num_pci_devs = 535 sizeof(ahc_pci_ident_table) / sizeof(*ahc_pci_ident_table); 536 537 #define AHC_394X_SLOT_CHANNEL_A 4 538 #define AHC_394X_SLOT_CHANNEL_B 5 539 540 #define AHC_398X_SLOT_CHANNEL_A 4 541 #define AHC_398X_SLOT_CHANNEL_B 8 542 #define AHC_398X_SLOT_CHANNEL_C 12 543 544 #define DEVCONFIG 0x40 545 #define SCBSIZE32 0x00010000 /* aic789X only */ 546 #define MPORTMODE 0x00000400 /* aic7870 only */ 547 #define RAMPSM 0x00000200 /* aic7870 only */ 548 #define VOLSENSE 0x00000100 549 #define SCBRAMSEL 0x00000080 550 #define MRDCEN 0x00000040 551 #define EXTSCBTIME 0x00000020 /* aic7870 only */ 552 #define EXTSCBPEN 0x00000010 /* aic7870 only */ 553 #define BERREN 0x00000008 554 #define DACEN 0x00000004 555 #define STPWLEVEL 0x00000002 556 #define DIFACTNEGEN 0x00000001 /* aic7870 only */ 557 558 #define CSIZE_LATTIME 0x0c 559 #define CACHESIZE 0x0000003f /* only 5 bits */ 560 #define LATTIME 0x0000ff00 561 562 static const struct ahc_pci_identity *ahc_find_pci_device(pcireg_t, pcireg_t); 563 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 564 static void ahc_ext_scbram_config(struct ahc_softc *ahc, int enable, 565 int pcheck, int fast); 566 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 567 568 int ahc_pci_probe __P((struct device *, struct cfdata *, void *)); 569 void ahc_pci_attach __P((struct device *, struct device *, void *)); 570 571 /* Exported for use in the ahc_intr routine */ 572 int ahc_pci_intr(struct ahc_softc *ahc); 573 574 struct cfattach ahc_pci_ca = { 575 sizeof(struct ahc_softc), ahc_pci_probe, ahc_pci_attach 576 }; 577 578 static const struct ahc_pci_identity * 579 ahc_find_pci_device(id, subid) 580 pcireg_t id, subid; 581 { 582 u_int64_t full_id; 583 const struct ahc_pci_identity *entry; 584 u_int i; 585 586 full_id = ahc_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 587 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 588 589 for (i = 0; i < ahc_num_pci_devs; i++) { 590 entry = &ahc_pci_ident_table[i]; 591 if (entry->full_id == (full_id & entry->id_mask)) 592 return (entry); 593 } 594 return (NULL); 595 } 596 597 int 598 ahc_pci_probe(parent, match, aux) 599 struct device *parent; 600 struct cfdata *match; 601 void *aux; 602 { 603 struct pci_attach_args *pa = aux; 604 const struct ahc_pci_identity *entry; 605 pcireg_t subid; 606 607 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 608 entry = ahc_find_pci_device(pa->pa_id, subid); 609 return entry != NULL ? 1 : 0; 610 } 611 612 void 613 ahc_pci_attach(parent, self, aux) 614 struct device *parent, *self; 615 void *aux; 616 { 617 struct pci_attach_args *pa = aux; 618 const struct ahc_pci_identity *entry; 619 struct ahc_softc *ahc = (void *)self; 620 pcireg_t command; 621 ahc_chip ahc_t = AHC_NONE; 622 ahc_feature ahc_fe = AHC_FENONE; 623 ahc_flag ahc_f = AHC_FNONE; 624 u_int our_id = 0; 625 u_int sxfrctl1; 626 u_int scsiseq; 627 int error; 628 char channel; 629 pcireg_t subid; 630 int ioh_valid, memh_valid; 631 bus_space_tag_t st, iot; 632 bus_space_handle_t sh, ioh; 633 #ifdef AHC_ALLOW_MEMIO 634 bus_space_tag_t memt; 635 bus_space_handle_t memh; 636 pcireg_t memtype; 637 #endif 638 pci_intr_handle_t ih; 639 const char *intrstr; 640 struct ahc_pci_busdata *bd; 641 642 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 643 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 644 entry = ahc_find_pci_device(pa->pa_id, subid); 645 if (entry == NULL) 646 return; 647 error = entry->setup(pa, &channel, &ahc_t, &ahc_fe, &ahc_f); 648 if (error != 0) 649 return; 650 651 ioh_valid = memh_valid = 0; 652 653 #ifdef AHC_ALLOW_MEMIO 654 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHC_PCI_MEMADDR); 655 switch (memtype) { 656 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 657 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 658 memh_valid = (pci_mapreg_map(pa, AHC_PCI_MEMADDR, 659 memtype, 0, &memt, &memh, NULL, NULL) == 0); 660 break; 661 default: 662 memh_valid = 0; 663 } 664 #endif 665 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_IOADDR, 666 PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, NULL, NULL) == 0); 667 668 if (ioh_valid) { 669 st = iot; 670 sh = ioh; 671 #ifdef AHC_ALLOW_MEMIO 672 } else if (memh_valid) { 673 st = memt; 674 sh = memh; 675 #endif 676 } else { 677 printf(": unable to map registers\n"); 678 return; 679 } 680 681 printf("\n"); 682 683 684 /* Ensure busmastering is enabled */ 685 command |= PCI_COMMAND_MASTER_ENABLE;; 686 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 687 688 /* On all PCI adapters, we allow SCB paging */ 689 ahc_f |= AHC_PAGESCBS; 690 if (ahc_alloc(ahc, sh, st, pa->pa_dmat, 691 ahc_t|AHC_PCI, ahc_fe, ahc_f) < 0) 692 return; 693 694 bd = malloc(sizeof (struct ahc_pci_busdata), M_DEVBUF, M_NOWAIT); 695 if (bd == NULL) { 696 printf(": unable to allocate bus-specific data\n"); 697 return; 698 } 699 700 bd->pc = pa->pa_pc; 701 bd->tag = pa->pa_tag; 702 bd->func = pa->pa_function; 703 bd->dev = pa->pa_device; 704 705 ahc->bus_data = bd; 706 ahc->bus_intr = ahc_pci_intr; 707 ahc->channel = channel; 708 709 /* Remeber how the card was setup in case there is no SEEPROM */ 710 ahc_outb(ahc, HCNTRL, ahc->pause); 711 if ((ahc->features & AHC_ULTRA2) != 0) 712 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 713 else 714 our_id = ahc_inb(ahc, SCSIID) & OID; 715 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 716 scsiseq = ahc_inb(ahc, SCSISEQ); 717 718 if (ahc_reset(ahc) != 0) { 719 /* Failed */ 720 ahc_free(ahc); 721 return; 722 } 723 724 if ((ahc->features & AHC_DT) != 0) { 725 u_int optionmode; 726 u_int sfunct; 727 728 /* Perform ALT-Mode Setup */ 729 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 730 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 731 optionmode = ahc_inb(ahc, OPTIONMODE); 732 #ifdef DEBUG 733 printf("%s: OptionMode = %x\n", ahc->sc_dev.dv_xname, 734 optionmode); 735 #endif 736 ahc_outb(ahc, OPTIONMODE, OPTIONMODE_DEFAULTS); 737 /* Send CRC info in target mode every 4K */ 738 ahc_outb(ahc, TARGCRCCNT, 0); 739 ahc_outb(ahc, TARGCRCCNT + 1, 0x10); 740 ahc_outb(ahc, SFUNCT, sfunct); 741 742 /* Normal mode setup */ 743 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 744 |TARGCRCENDEN|TARGCRCCNTEN); 745 } 746 747 if (pci_intr_map(pa, &ih)) { 748 printf("%s: couldn't map interrupt\n", ahc->sc_dev.dv_xname); 749 ahc_free(ahc); 750 return; 751 } 752 intrstr = pci_intr_string(pa->pa_pc, ih); 753 ahc->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahc_intr, ahc); 754 if (ahc->ih == NULL) { 755 printf("%s: couldn't establish interrupt", 756 ahc->sc_dev.dv_xname); 757 if (intrstr != NULL) 758 printf(" at %s", intrstr); 759 printf("\n"); 760 ahc_free(ahc); 761 return; 762 } 763 if (intrstr != NULL) 764 printf("%s: interrupting at %s\n", ahc->sc_dev.dv_xname, 765 intrstr); 766 767 /* 768 * Do aic7880/aic7870/aic7860/aic7850 specific initialization 769 */ 770 { 771 u_int8_t sblkctl; 772 u_int dscommand0; 773 774 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 775 dscommand0 |= MPARCKEN; 776 if ((ahc->features & AHC_ULTRA2) != 0) { 777 778 /* 779 * DPARCKEN doesn't work correctly on 780 * some MBs so don't use it. 781 */ 782 dscommand0 &= ~(USCBSIZE32|DPARCKEN); 783 dscommand0 |= CACHETHEN; 784 } 785 786 ahc_outb(ahc, DSCOMMAND0, dscommand0); 787 788 /* See if we have an SEEPROM and perform auto-term */ 789 check_extport(ahc, &sxfrctl1); 790 791 /* 792 * Take the LED out of diagnostic mode 793 */ 794 sblkctl = ahc_inb(ahc, SBLKCTL); 795 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 796 797 /* 798 * I don't know where this is set in the SEEPROM or by the 799 * BIOS, so we default to 100% on Ultra or slower controllers 800 * and 75% on ULTRA2 controllers. 801 */ 802 if ((ahc->features & AHC_ULTRA2) != 0) { 803 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 804 } else { 805 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 806 } 807 808 if (ahc->flags & AHC_USEDEFAULTS) { 809 /* 810 * PCI Adapter default setup 811 * Should only be used if the adapter does not have 812 * an SEEPROM. 813 */ 814 /* See if someone else set us up already */ 815 if (scsiseq != 0) { 816 printf("%s: Using left over BIOS settings\n", 817 ahc_name(ahc)); 818 ahc->flags &= ~AHC_USEDEFAULTS; 819 } else { 820 /* 821 * Assume only one connector and always turn 822 * on termination. 823 */ 824 our_id = 0x07; 825 sxfrctl1 = STPWEN; 826 } 827 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 828 829 ahc->our_id = our_id; 830 } 831 } 832 833 /* 834 * Take a look to see if we have external SRAM. 835 * We currently do not attempt to use SRAM that is 836 * shared among multiple controllers. 837 */ 838 ahc_probe_ext_scbram(ahc); 839 840 841 printf("%s: %s ", ahc_name(ahc), 842 ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); 843 844 /* 845 * Record our termination setting for the 846 * generic initialization routine. 847 */ 848 if ((sxfrctl1 & STPWEN) != 0) 849 ahc->flags |= AHC_TERM_ENB_A; 850 851 if (ahc_init(ahc)) { 852 ahc_free(ahc); 853 return; 854 } 855 856 ahc_attach(ahc); 857 } 858 859 /* 860 * Test for the presence of external sram in an 861 * "unshared" configuration. 862 */ 863 static int 864 ahc_ext_scbram_present(struct ahc_softc *ahc) 865 { 866 int ramps; 867 int single_user; 868 pcireg_t devconfig; 869 struct ahc_pci_busdata *bd = ahc->bus_data; 870 871 devconfig = pci_conf_read(bd->pc, bd->tag, DEVCONFIG); 872 single_user = (devconfig & MPORTMODE) != 0; 873 874 if ((ahc->features & AHC_ULTRA2) != 0) 875 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 876 else if ((ahc->chip & AHC_CHIPID_MASK) >= AHC_AIC7870) 877 ramps = (devconfig & RAMPSM) != 0; 878 else 879 ramps = 0; 880 881 if (ramps && single_user) 882 return (1); 883 return (0); 884 } 885 886 /* 887 * Enable external scbram. 888 */ 889 static void 890 ahc_ext_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, int fast) 891 { 892 pcireg_t devconfig; 893 struct ahc_pci_busdata *bd = ahc->bus_data; 894 895 if (ahc->features & AHC_MULTI_FUNC) { 896 /* 897 * Set the SCB Base addr (highest address bit) 898 * depending on which channel we are. 899 */ 900 ahc_outb(ahc, SCBBADDR, (u_int8_t)bd->func); 901 } 902 903 devconfig = pci_conf_read(bd->pc, bd->tag, DEVCONFIG); 904 if ((ahc->features & AHC_ULTRA2) != 0) { 905 u_int dscommand0; 906 907 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 908 if (enable) 909 dscommand0 &= ~INTSCBRAMSEL; 910 else 911 dscommand0 |= INTSCBRAMSEL; 912 ahc_outb(ahc, DSCOMMAND0, dscommand0); 913 } else { 914 if (fast) 915 devconfig &= ~EXTSCBTIME; 916 else 917 devconfig |= EXTSCBTIME; 918 if (enable) 919 devconfig &= ~SCBRAMSEL; 920 else 921 devconfig |= SCBRAMSEL; 922 } 923 if (pcheck) 924 devconfig |= EXTSCBPEN; 925 else 926 devconfig &= ~EXTSCBPEN; 927 928 pci_conf_write(bd->pc, bd->tag, DEVCONFIG, devconfig); 929 } 930 931 /* 932 * Take a look to see if we have external SRAM. 933 * We currently do not attempt to use SRAM that is 934 * shared among multiple controllers. 935 */ 936 static void 937 ahc_probe_ext_scbram(struct ahc_softc *ahc) 938 { 939 int num_scbs; 940 int test_num_scbs; 941 int enable; 942 int pcheck; 943 int fast; 944 945 if (ahc_ext_scbram_present(ahc) == 0) 946 return; 947 948 /* 949 * Probe for the best parameters to use. 950 */ 951 enable = FALSE; 952 pcheck = FALSE; 953 fast = FALSE; 954 ahc_ext_scbram_config(ahc, /*enable*/TRUE, pcheck, fast); 955 num_scbs = ahc_probe_scbs(ahc); 956 if (num_scbs == 0) { 957 /* The SRAM wasn't really present. */ 958 goto done; 959 } 960 enable = TRUE; 961 962 /* 963 * Clear any outstanding parity error 964 * and ensure that parity error reporting 965 * is enabled. 966 */ 967 ahc_outb(ahc, SEQCTL, 0); 968 ahc_outb(ahc, CLRINT, CLRPARERR); 969 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 970 971 /* Now see if we can do parity */ 972 ahc_ext_scbram_config(ahc, enable, /*pcheck*/TRUE, fast); 973 num_scbs = ahc_probe_scbs(ahc); 974 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 975 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 976 pcheck = TRUE; 977 978 /* Clear any resulting parity error */ 979 ahc_outb(ahc, CLRINT, CLRPARERR); 980 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 981 982 /* Now see if we can do fast timing */ 983 ahc_ext_scbram_config(ahc, enable, pcheck, /*fast*/TRUE); 984 test_num_scbs = ahc_probe_scbs(ahc); 985 if (test_num_scbs == num_scbs 986 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 987 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 988 fast = TRUE; 989 990 done: 991 /* 992 * Disable parity error reporting until we 993 * can load instruction ram. 994 */ 995 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 996 /* Clear any latched parity error */ 997 ahc_outb(ahc, CLRINT, CLRPARERR); 998 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 999 if (bootverbose && enable) { 1000 printf("%s: External SRAM, %s access%s\n", 1001 ahc_name(ahc), fast ? "fast" : "slow", 1002 pcheck ? ", parity checking enabled" : ""); 1003 1004 } 1005 ahc_ext_scbram_config(ahc, enable, pcheck, fast); 1006 } 1007 1008 #define DPE PCI_STATUS_PARITY_DETECT 1009 #define SSE PCI_STATUS_SPECIAL_ERROR 1010 #define RMA PCI_STATUS_MASTER_ABORT 1011 #define RTA PCI_STATUS_MASTER_TARGET_ABORT 1012 #define STA PCI_STATUS_TARGET_TARGET_ABORT 1013 #define DPR PCI_STATUS_PARITY_ERROR 1014 1015 int 1016 ahc_pci_intr(struct ahc_softc *ahc) 1017 { 1018 pcireg_t status1; 1019 struct ahc_pci_busdata *bd = ahc->bus_data; 1020 1021 if ((ahc_inb(ahc, ERROR) & PCIERRSTAT) == 0) 1022 return 0; 1023 1024 status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 1025 1026 if (status1 & DPE) { 1027 printf("%s: Data Parity Error Detected during address " 1028 "or write data phase\n", ahc_name(ahc)); 1029 } 1030 if (status1 & SSE) { 1031 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1032 } 1033 if (status1 & RMA) { 1034 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1035 } 1036 if (status1 & RTA) { 1037 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1038 } 1039 if (status1 & STA) { 1040 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1041 } 1042 if (status1 & DPR) { 1043 printf("%s: Data Parity Error has been reported via PERR#\n", 1044 ahc_name(ahc)); 1045 } 1046 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1047 printf("%s: Latched PCIERR interrupt with " 1048 "no status bits set\n", ahc_name(ahc)); 1049 } 1050 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, status1); 1051 1052 if (status1 & (DPR|RMA|RTA)) { 1053 ahc_outb(ahc, CLRINT, CLRPARERR); 1054 } 1055 1056 return 1; 1057 } 1058 1059 static int 1060 ahc_aic7850_setup(struct pci_attach_args *pa, char *channel, 1061 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1062 { 1063 *channel = 'A'; 1064 *chip = AHC_AIC7850; 1065 *features = AHC_AIC7850_FE; 1066 return (0); 1067 } 1068 1069 static int 1070 ahc_aic7855_setup(struct pci_attach_args *pa, char *channel, 1071 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1072 { 1073 *channel = 'A'; 1074 *chip = AHC_AIC7855; 1075 *features = AHC_AIC7855_FE; 1076 return (0); 1077 } 1078 1079 static int 1080 ahc_aic7859_setup(struct pci_attach_args *pa, char *channel, 1081 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1082 { 1083 *channel = 'A'; 1084 *chip = AHC_AIC7859; 1085 *features = AHC_AIC7859_FE; 1086 return (0); 1087 } 1088 1089 static int 1090 ahc_aic7860_setup(struct pci_attach_args *pa, char *channel, 1091 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1092 { 1093 *channel = 'A'; 1094 *chip = AHC_AIC7860; 1095 *features = AHC_AIC7860_FE; 1096 return (0); 1097 } 1098 1099 static int 1100 ahc_aic7870_setup(struct pci_attach_args *pa, char *channel, 1101 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1102 { 1103 *channel = 'A'; 1104 *chip = AHC_AIC7870; 1105 *features = AHC_AIC7870_FE; 1106 return (0); 1107 } 1108 1109 static int 1110 ahc_aha394X_setup(struct pci_attach_args *pa, char *channel, 1111 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1112 { 1113 int error; 1114 1115 error = ahc_aic7870_setup(pa, channel, chip, features, flags); 1116 if (error == 0) 1117 error = ahc_aha394XX_setup(pa, channel, chip, features, flags); 1118 return (error); 1119 } 1120 1121 static int 1122 ahc_aha398X_setup(struct pci_attach_args *pa, char *channel, 1123 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1124 { 1125 int error; 1126 1127 error = ahc_aic7870_setup(pa, channel, chip, features, flags); 1128 if (error == 0) 1129 error = ahc_aha398XX_setup(pa, channel, chip, features, flags); 1130 return (error); 1131 } 1132 1133 static int 1134 ahc_aic7880_setup(struct pci_attach_args *pa, char *channel, 1135 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1136 { 1137 *channel = 'A'; 1138 *chip = AHC_AIC7880; 1139 *features = AHC_AIC7880_FE; 1140 return (0); 1141 } 1142 1143 static int 1144 ahc_2940Pro_setup(struct pci_attach_args *pa, char *channel, 1145 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1146 { 1147 int error; 1148 1149 *flags |= AHC_INT50_SPEEDFLEX; 1150 error = ahc_aic7880_setup(pa, channel, chip, features, flags); 1151 return (0); 1152 } 1153 1154 static int 1155 ahc_aha394XU_setup(struct pci_attach_args *pa, char *channel, 1156 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1157 { 1158 int error; 1159 1160 error = ahc_aic7880_setup(pa, channel, chip, features, flags); 1161 if (error == 0) 1162 error = ahc_aha394XX_setup(pa, channel, chip, features, flags); 1163 return (error); 1164 } 1165 1166 static int 1167 ahc_aha398XU_setup(struct pci_attach_args *pa, char *channel, 1168 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1169 { 1170 int error; 1171 1172 error = ahc_aic7880_setup(pa, channel, chip, features, flags); 1173 if (error == 0) 1174 error = ahc_aha398XX_setup(pa, channel, chip, features, flags); 1175 return (error); 1176 } 1177 1178 static int 1179 ahc_aic7890_setup(struct pci_attach_args *pa, char *channel, 1180 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1181 { 1182 *channel = 'A'; 1183 *chip = AHC_AIC7890; 1184 *features = AHC_AIC7890_FE; 1185 *flags |= AHC_NEWEEPROM_FMT; 1186 return (0); 1187 } 1188 1189 static int 1190 ahc_aic7892_setup(struct pci_attach_args *pa, char *channel, 1191 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1192 { 1193 *channel = 'A'; 1194 *chip = AHC_AIC7892; 1195 *features = AHC_AIC7892_FE; 1196 *flags |= AHC_NEWEEPROM_FMT; 1197 return (0); 1198 } 1199 1200 static int 1201 ahc_aic7895_setup(struct pci_attach_args *pa, char *channel, 1202 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1203 { 1204 pcireg_t devconfig; 1205 1206 *channel = pa->pa_function == 1 ? 'B' : 'A'; 1207 *chip = AHC_AIC7895; 1208 /* The 'C' revision of the aic7895 has a few additional features */ 1209 if (PCI_REVISION(pa->pa_class) >= 4) 1210 *features = AHC_AIC7895C_FE; 1211 else 1212 *features = AHC_AIC7895_FE; 1213 *flags |= AHC_NEWEEPROM_FMT; 1214 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 1215 devconfig &= ~SCBSIZE32; 1216 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); 1217 return (0); 1218 } 1219 1220 static int 1221 ahc_aic7896_setup(struct pci_attach_args *pa, char *channel, 1222 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1223 { 1224 *channel = pa->pa_function == 1 ? 'B' : 'A'; 1225 *chip = AHC_AIC7896; 1226 *features = AHC_AIC7896_FE; 1227 *flags |= AHC_NEWEEPROM_FMT; 1228 return (0); 1229 } 1230 1231 static int 1232 ahc_aic7899_setup(struct pci_attach_args *pa, char *channel, 1233 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1234 { 1235 *channel = pa->pa_function == 1 ? 'B' : 'A'; 1236 *chip = AHC_AIC7899; 1237 *features = AHC_AIC7899_FE; 1238 *flags |= AHC_NEWEEPROM_FMT; 1239 return (0); 1240 } 1241 1242 static int 1243 ahc_raid_setup(struct pci_attach_args *pa, char *channel, 1244 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1245 { 1246 printf(": RAID functionality unsupported\n"); 1247 return (ENXIO); 1248 } 1249 1250 static int 1251 ahc_aha394XX_setup(struct pci_attach_args *pa, char *channel, 1252 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1253 { 1254 switch (pa->pa_device) { 1255 case AHC_394X_SLOT_CHANNEL_A: 1256 *channel = 'A'; 1257 break; 1258 case AHC_394X_SLOT_CHANNEL_B: 1259 *channel = 'B'; 1260 break; 1261 default: 1262 printf("adapter at unexpected slot %d\n" 1263 "unable to map to a channel\n", 1264 pa->pa_device); 1265 *channel = 'A'; 1266 } 1267 return (0); 1268 } 1269 1270 static int 1271 ahc_aha398XX_setup(struct pci_attach_args *pa, char *channel, 1272 ahc_chip *chip, ahc_feature *features, ahc_flag *flags) 1273 { 1274 switch (pa->pa_device) { 1275 case AHC_398X_SLOT_CHANNEL_A: 1276 *channel = 'A'; 1277 break; 1278 case AHC_398X_SLOT_CHANNEL_B: 1279 *channel = 'B'; 1280 break; 1281 case AHC_398X_SLOT_CHANNEL_C: 1282 *channel = 'C'; 1283 break; 1284 default: 1285 printf("adapter at unexpected slot %d\n" 1286 "unable to map to a channel\n", 1287 pa->pa_device); 1288 *channel = 'A'; 1289 } 1290 *flags |= AHC_LARGE_SEEPROM; 1291 return (0); 1292 } 1293
Indexes created Wed Oct 01 19:09:53 GMT 2025