ahc_pci.c revision 1.40
1 /* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1994-2001 Justin T. Gibbs. 7 * Copyright (c) 2000-2001 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: ahc_pci.c,v 1.40 2003/04/25 16:02:52 fvdl Exp $ 43 * 44 * //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#57 $ 45 * 46 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.22 2003/01/20 20:44:55 gibbs Exp $ 47 */ 48 /* 49 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 50 */ 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/malloc.h> 55 #include <sys/kernel.h> 56 #include <sys/queue.h> 57 #include <sys/device.h> 58 #include <sys/reboot.h> 59 60 #include <machine/bus.h> 61 #include <machine/intr.h> 62 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 66 #define AHC_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 67 #define AHC_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 68 69 #include <dev/ic/aic7xxx_osm.h> 70 #include <dev/ic/aic7xxx_inline.h> 71 72 #include <dev/ic/smc93cx6var.h> 73 74 75 static __inline uint64_t 76 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 77 { 78 uint64_t id; 79 80 id = subvendor 81 | (subdevice << 16) 82 | ((uint64_t)vendor << 32) 83 | ((uint64_t)device << 48); 84 85 return (id); 86 } 87 88 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 89 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 90 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 91 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull 92 #define ID_9005_SISL_ID 0x0005900500000000ull 93 #define ID_AIC7850 0x5078900400000000ull 94 #define ID_AHA_2902_04_10_15_20_30C 0x5078900478509004ull 95 #define ID_AIC7855 0x5578900400000000ull 96 #define ID_AIC7859 0x3860900400000000ull 97 #define ID_AHA_2930CU 0x3860900438699004ull 98 #define ID_AIC7860 0x6078900400000000ull 99 #define ID_AIC7860C 0x6078900478609004ull 100 #define ID_AHA_1480A 0x6075900400000000ull 101 #define ID_AHA_2940AU_0 0x6178900400000000ull 102 #define ID_AHA_2940AU_1 0x6178900478619004ull 103 #define ID_AHA_2940AU_CN 0x2178900478219004ull 104 #define ID_AHA_2930C_VAR 0x6038900438689004ull 105 106 #define ID_AIC7870 0x7078900400000000ull 107 #define ID_AHA_2940 0x7178900400000000ull 108 #define ID_AHA_3940 0x7278900400000000ull 109 #define ID_AHA_398X 0x7378900400000000ull 110 #define ID_AHA_2944 0x7478900400000000ull 111 #define ID_AHA_3944 0x7578900400000000ull 112 #define ID_AHA_4944 0x7678900400000000ull 113 114 #define ID_AIC7880 0x8078900400000000ull 115 #define ID_AIC7880_B 0x8078900478809004ull 116 #define ID_AHA_2940U 0x8178900400000000ull 117 #define ID_AHA_3940U 0x8278900400000000ull 118 #define ID_AHA_2944U 0x8478900400000000ull 119 #define ID_AHA_3944U 0x8578900400000000ull 120 #define ID_AHA_398XU 0x8378900400000000ull 121 #define ID_AHA_4944U 0x8678900400000000ull 122 #define ID_AHA_2940UB 0x8178900478819004ull 123 #define ID_AHA_2930U 0x8878900478889004ull 124 #define ID_AHA_2940U_PRO 0x8778900478879004ull 125 #define ID_AHA_2940U_CN 0x0078900478009004ull 126 127 #define ID_AIC7895 0x7895900478959004ull 128 #define ID_AIC7895_ARO 0x7890900478939004ull 129 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull 130 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 131 #define ID_AHA_3940AU 0x7895900478929004ull 132 #define ID_AHA_3944AU 0x7895900478949004ull 133 134 #define ID_AIC7890 0x001F9005000F9005ull 135 #define ID_AIC7890_ARO 0x00139005000F9005ull 136 #define ID_AAA_131U2 0x0013900500039005ull 137 #define ID_AHA_2930U2 0x0011900501819005ull 138 #define ID_AHA_2940U2B 0x00109005A1009005ull 139 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 140 #define ID_AHA_2940U2 0x00109005A1809005ull 141 #define ID_AHA_2950U2B 0x00109005E1009005ull 142 143 #define ID_AIC7892 0x008F9005FFFF9005ull 144 #define ID_AIC7892_ARO 0x00839005FFFF9005ull 145 #define ID_AHA_29160 0x00809005E2A09005ull 146 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 147 #define ID_AHA_29160N 0x0080900562A09005ull 148 #define ID_AHA_29160C 0x0080900562209005ull 149 #define ID_AHA_29160B 0x00809005E2209005ull 150 #define ID_AHA_19160B 0x0081900562A19005ull 151 152 #define ID_AIC7896 0x005F9005FFFF9005ull 153 #define ID_AIC7896_ARO 0x00539005FFFF9005ull 154 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 155 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 156 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 157 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 158 159 #define ID_AIC7899 0x00CF9005FFFF9005ull 160 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull 161 #define ID_AHA_3960D 0x00C09005F6209005ull 162 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 163 164 #define ID_AIC7810 0x1078900400000000ull 165 #define ID_AIC7815 0x7815900400000000ull 166 167 #define DEVID_9005_TYPE(id) ((id) & 0xF) 168 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 169 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ 170 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */ 171 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 172 173 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 174 #define DEVID_9005_MAXRATE_U160 0x0 175 #define DEVID_9005_MAXRATE_ULTRA2 0x1 176 #define DEVID_9005_MAXRATE_ULTRA 0x2 177 #define DEVID_9005_MAXRATE_FAST 0x3 178 179 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) 180 181 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) 182 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ 183 184 #define SUBID_9005_TYPE(id) ((id) & 0xF) 185 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 186 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 187 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 188 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 189 190 #define SUBID_9005_TYPE_KNOWN(id) \ 191 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ 192 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ 193 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ 194 || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) 195 196 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 197 #define SUBID_9005_MAXRATE_ULTRA2 0x0 198 #define SUBID_9005_MAXRATE_ULTRA 0x1 199 #define SUBID_9005_MAXRATE_U160 0x2 200 #define SUBID_9005_MAXRATE_RESERVED 0x3 201 202 #define SUBID_9005_SEEPTYPE(id) \ 203 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 204 ? ((id) & 0xC0) >> 6 \ 205 : ((id) & 0x300) >> 8) 206 #define SUBID_9005_SEEPTYPE_NONE 0x0 207 #define SUBID_9005_SEEPTYPE_1K 0x1 208 #define SUBID_9005_SEEPTYPE_2K_4K 0x2 209 #define SUBID_9005_SEEPTYPE_RESERVED 0x3 210 #define SUBID_9005_AUTOTERM(id) \ 211 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 212 ? (((id) & 0x400) >> 10) == 0 \ 213 : (((id) & 0x40) >> 6) == 0) 214 215 #define SUBID_9005_NUMCHAN(id) \ 216 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 217 ? ((id) & 0x300) >> 8 \ 218 : ((id) & 0xC00) >> 10) 219 220 #define SUBID_9005_LEGACYCONN(id) \ 221 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 222 ? 0 \ 223 : ((id) & 0x80) >> 7) 224 225 #define SUBID_9005_MFUNCENB(id) \ 226 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 227 ? ((id) & 0x800) >> 11 \ 228 : ((id) & 0x1000) >> 12) 229 /* 230 * Informational only. Should use chip register to be 231 * certain, but may be use in identification strings. 232 */ 233 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 234 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 235 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000 236 237 static ahc_device_setup_t ahc_aic785X_setup; 238 static ahc_device_setup_t ahc_aic7860_setup; 239 static ahc_device_setup_t ahc_apa1480_setup; 240 static ahc_device_setup_t ahc_aic7870_setup; 241 static ahc_device_setup_t ahc_aha394X_setup; 242 static ahc_device_setup_t ahc_aha494X_setup; 243 static ahc_device_setup_t ahc_aha398X_setup; 244 static ahc_device_setup_t ahc_aic7880_setup; 245 static ahc_device_setup_t ahc_aha2940Pro_setup; 246 static ahc_device_setup_t ahc_aha394XU_setup; 247 static ahc_device_setup_t ahc_aha398XU_setup; 248 static ahc_device_setup_t ahc_aic7890_setup; 249 static ahc_device_setup_t ahc_aic7892_setup; 250 static ahc_device_setup_t ahc_aic7895_setup; 251 static ahc_device_setup_t ahc_aic7896_setup; 252 static ahc_device_setup_t ahc_aic7899_setup; 253 static ahc_device_setup_t ahc_aha29160C_setup; 254 static ahc_device_setup_t ahc_raid_setup; 255 static ahc_device_setup_t ahc_aha394XX_setup; 256 static ahc_device_setup_t ahc_aha494XX_setup; 257 static ahc_device_setup_t ahc_aha398XX_setup; 258 259 struct ahc_pci_identity ahc_pci_ident_table [] = 260 { 261 /* aic7850 based controllers */ 262 { 263 ID_AHA_2902_04_10_15_20_30C, 264 ID_ALL_MASK, 265 "Adaptec 2902/04/10/15/20/30C SCSI adapter", 266 ahc_aic785X_setup 267 }, 268 /* aic7860 based controllers */ 269 { 270 ID_AHA_2930CU, 271 ID_ALL_MASK, 272 "Adaptec 2930CU SCSI adapter", 273 ahc_aic7860_setup 274 }, 275 { 276 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 277 ID_DEV_VENDOR_MASK, 278 "Adaptec 1480A Ultra SCSI adapter", 279 ahc_apa1480_setup 280 }, 281 { 282 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 283 ID_DEV_VENDOR_MASK, 284 "Adaptec 2940A Ultra SCSI adapter", 285 ahc_aic7860_setup 286 }, 287 { 288 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 289 ID_DEV_VENDOR_MASK, 290 "Adaptec 2940A/CN Ultra SCSI adapter", 291 ahc_aic7860_setup 292 }, 293 { 294 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 295 ID_DEV_VENDOR_MASK, 296 "Adaptec 2930C Ultra SCSI adapter (VAR)", 297 ahc_aic7860_setup 298 }, 299 /* aic7870 based controllers */ 300 { 301 ID_AHA_2940, 302 ID_ALL_MASK, 303 "Adaptec 2940 SCSI adapter", 304 ahc_aic7870_setup 305 }, 306 { 307 ID_AHA_3940, 308 ID_ALL_MASK, 309 "Adaptec 3940 SCSI adapter", 310 ahc_aha394X_setup 311 }, 312 { 313 ID_AHA_398X, 314 ID_ALL_MASK, 315 "Adaptec 398X SCSI RAID adapter", 316 ahc_aha398X_setup 317 }, 318 { 319 ID_AHA_2944, 320 ID_ALL_MASK, 321 "Adaptec 2944 SCSI adapter", 322 ahc_aic7870_setup 323 }, 324 { 325 ID_AHA_3944, 326 ID_ALL_MASK, 327 "Adaptec 3944 SCSI adapter", 328 ahc_aha394X_setup 329 }, 330 { 331 ID_AHA_4944, 332 ID_ALL_MASK, 333 "Adaptec 4944 SCSI adapter", 334 ahc_aha494X_setup 335 }, 336 /* aic7880 based controllers */ 337 { 338 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 339 ID_DEV_VENDOR_MASK, 340 "Adaptec 2940 Ultra SCSI adapter", 341 ahc_aic7880_setup 342 }, 343 { 344 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 345 ID_DEV_VENDOR_MASK, 346 "Adaptec 3940 Ultra SCSI adapter", 347 ahc_aha394XU_setup 348 }, 349 { 350 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 351 ID_DEV_VENDOR_MASK, 352 "Adaptec 2944 Ultra SCSI adapter", 353 ahc_aic7880_setup 354 }, 355 { 356 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 357 ID_DEV_VENDOR_MASK, 358 "Adaptec 3944 Ultra SCSI adapter", 359 ahc_aha394XU_setup 360 }, 361 { 362 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 363 ID_DEV_VENDOR_MASK, 364 "Adaptec 398X Ultra SCSI RAID adapter", 365 ahc_aha398XU_setup 366 }, 367 { 368 /* 369 * XXX Don't know the slot numbers 370 * so we can't identify channels 371 */ 372 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 373 ID_DEV_VENDOR_MASK, 374 "Adaptec 4944 Ultra SCSI adapter", 375 ahc_aic7880_setup 376 }, 377 { 378 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 379 ID_DEV_VENDOR_MASK, 380 "Adaptec 2930 Ultra SCSI adapter", 381 ahc_aic7880_setup 382 }, 383 { 384 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 385 ID_DEV_VENDOR_MASK, 386 "Adaptec 2940 Pro Ultra SCSI adapter", 387 ahc_aha2940Pro_setup 388 }, 389 { 390 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 391 ID_DEV_VENDOR_MASK, 392 "Adaptec 2940/CN Ultra SCSI adapter", 393 ahc_aic7880_setup 394 }, 395 /* Ignore all SISL (AAC on MB) based controllers. */ 396 { 397 ID_9005_SISL_ID, 398 ID_9005_SISL_MASK, 399 NULL, 400 NULL 401 }, 402 /* aic7890 based controllers */ 403 { 404 ID_AHA_2930U2, 405 ID_ALL_MASK, 406 "Adaptec 2930 Ultra2 SCSI adapter", 407 ahc_aic7890_setup 408 }, 409 { 410 ID_AHA_2940U2B, 411 ID_ALL_MASK, 412 "Adaptec 2940B Ultra2 SCSI adapter", 413 ahc_aic7890_setup 414 }, 415 { 416 ID_AHA_2940U2_OEM, 417 ID_ALL_MASK, 418 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 419 ahc_aic7890_setup 420 }, 421 { 422 ID_AHA_2940U2, 423 ID_ALL_MASK, 424 "Adaptec 2940 Ultra2 SCSI adapter", 425 ahc_aic7890_setup 426 }, 427 { 428 ID_AHA_2950U2B, 429 ID_ALL_MASK, 430 "Adaptec 2950 Ultra2 SCSI adapter", 431 ahc_aic7890_setup 432 }, 433 { 434 ID_AIC7890_ARO, 435 ID_ALL_MASK, 436 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)", 437 ahc_aic7890_setup 438 }, 439 { 440 ID_AAA_131U2, 441 ID_ALL_MASK, 442 "Adaptec AAA-131 Ultra2 RAID adapter", 443 ahc_aic7890_setup 444 }, 445 /* aic7892 based controllers */ 446 { 447 ID_AHA_29160, 448 ID_ALL_MASK, 449 "Adaptec 29160 Ultra160 SCSI adapter", 450 ahc_aic7892_setup 451 }, 452 { 453 ID_AHA_29160_CPQ, 454 ID_ALL_MASK, 455 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 456 ahc_aic7892_setup 457 }, 458 { 459 ID_AHA_29160N, 460 ID_ALL_MASK, 461 "Adaptec 29160N Ultra160 SCSI adapter", 462 ahc_aic7892_setup 463 }, 464 { 465 ID_AHA_29160C, 466 ID_ALL_MASK, 467 "Adaptec 29160C Ultra160 SCSI adapter", 468 ahc_aha29160C_setup 469 }, 470 { 471 ID_AHA_29160B, 472 ID_ALL_MASK, 473 "Adaptec 29160B Ultra160 SCSI adapter", 474 ahc_aic7892_setup 475 }, 476 { 477 ID_AHA_19160B, 478 ID_ALL_MASK, 479 "Adaptec 19160B Ultra160 SCSI adapter", 480 ahc_aic7892_setup 481 }, 482 { 483 ID_AIC7892_ARO, 484 ID_ALL_MASK, 485 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)", 486 ahc_aic7892_setup 487 }, 488 /* aic7895 based controllers */ 489 { 490 ID_AHA_2940U_DUAL, 491 ID_ALL_MASK, 492 "Adaptec 2940/DUAL Ultra SCSI adapter", 493 ahc_aic7895_setup 494 }, 495 { 496 ID_AHA_3940AU, 497 ID_ALL_MASK, 498 "Adaptec 3940A Ultra SCSI adapter", 499 ahc_aic7895_setup 500 }, 501 { 502 ID_AHA_3944AU, 503 ID_ALL_MASK, 504 "Adaptec 3944A Ultra SCSI adapter", 505 ahc_aic7895_setup 506 }, 507 { 508 ID_AIC7895_ARO, 509 ID_AIC7895_ARO_MASK, 510 "Adaptec aic7895 Ultra SCSI adapter (ARO)", 511 ahc_aic7895_setup 512 }, 513 /* aic7896/97 based controllers */ 514 { 515 ID_AHA_3950U2B_0, 516 ID_ALL_MASK, 517 "Adaptec 3950B Ultra2 SCSI adapter", 518 ahc_aic7896_setup 519 }, 520 { 521 ID_AHA_3950U2B_1, 522 ID_ALL_MASK, 523 "Adaptec 3950B Ultra2 SCSI adapter", 524 ahc_aic7896_setup 525 }, 526 { 527 ID_AHA_3950U2D_0, 528 ID_ALL_MASK, 529 "Adaptec 3950D Ultra2 SCSI adapter", 530 ahc_aic7896_setup 531 }, 532 { 533 ID_AHA_3950U2D_1, 534 ID_ALL_MASK, 535 "Adaptec 3950D Ultra2 SCSI adapter", 536 ahc_aic7896_setup 537 }, 538 { 539 ID_AIC7896_ARO, 540 ID_ALL_MASK, 541 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)", 542 ahc_aic7896_setup 543 }, 544 /* aic7899 based controllers */ 545 { 546 ID_AHA_3960D, 547 ID_ALL_MASK, 548 "Adaptec 3960D Ultra160 SCSI adapter", 549 ahc_aic7899_setup 550 }, 551 { 552 ID_AHA_3960D_CPQ, 553 ID_ALL_MASK, 554 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 555 ahc_aic7899_setup 556 }, 557 { 558 ID_AIC7899_ARO, 559 ID_ALL_MASK, 560 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)", 561 ahc_aic7899_setup 562 }, 563 /* Generic chip probes for devices we don't know 'exactly' */ 564 { 565 ID_AIC7850 & ID_DEV_VENDOR_MASK, 566 ID_DEV_VENDOR_MASK, 567 "Adaptec aic7850 SCSI adapter", 568 ahc_aic785X_setup 569 }, 570 { 571 ID_AIC7855 & ID_DEV_VENDOR_MASK, 572 ID_DEV_VENDOR_MASK, 573 "Adaptec aic7855 SCSI adapter", 574 ahc_aic785X_setup 575 }, 576 { 577 ID_AIC7859 & ID_DEV_VENDOR_MASK, 578 ID_DEV_VENDOR_MASK, 579 "Adaptec aic7859 SCSI adapter", 580 ahc_aic7860_setup 581 }, 582 { 583 ID_AIC7860 & ID_DEV_VENDOR_MASK, 584 ID_DEV_VENDOR_MASK, 585 "Adaptec aic7860 Ultra SCSI adapter", 586 ahc_aic7860_setup 587 }, 588 { 589 ID_AIC7870 & ID_DEV_VENDOR_MASK, 590 ID_DEV_VENDOR_MASK, 591 "Adaptec aic7870 SCSI adapter", 592 ahc_aic7870_setup 593 }, 594 { 595 ID_AIC7880 & ID_DEV_VENDOR_MASK, 596 ID_DEV_VENDOR_MASK, 597 "Adaptec aic7880 Ultra SCSI adapter", 598 ahc_aic7880_setup 599 }, 600 { 601 ID_AIC7890 & ID_9005_GENERIC_MASK, 602 ID_9005_GENERIC_MASK, 603 "Adaptec aic7890/91 Ultra2 SCSI adapter", 604 ahc_aic7890_setup 605 }, 606 { 607 ID_AIC7892 & ID_9005_GENERIC_MASK, 608 ID_9005_GENERIC_MASK, 609 "Adaptec aic7892 Ultra160 SCSI adapter", 610 ahc_aic7892_setup 611 }, 612 { 613 ID_AIC7895 & ID_DEV_VENDOR_MASK, 614 ID_DEV_VENDOR_MASK, 615 "Adaptec aic7895 Ultra SCSI adapter", 616 ahc_aic7895_setup 617 }, 618 { 619 ID_AIC7896 & ID_9005_GENERIC_MASK, 620 ID_9005_GENERIC_MASK, 621 "Adaptec aic7896/97 Ultra2 SCSI adapter", 622 ahc_aic7896_setup 623 }, 624 { 625 ID_AIC7899 & ID_9005_GENERIC_MASK, 626 ID_9005_GENERIC_MASK, 627 "Adaptec aic7899 Ultra160 SCSI adapter", 628 ahc_aic7899_setup 629 }, 630 { 631 ID_AIC7810 & ID_DEV_VENDOR_MASK, 632 ID_DEV_VENDOR_MASK, 633 "Adaptec aic7810 RAID memory controller", 634 ahc_raid_setup 635 }, 636 { 637 ID_AIC7815 & ID_DEV_VENDOR_MASK, 638 ID_DEV_VENDOR_MASK, 639 "Adaptec aic7815 RAID memory controller", 640 ahc_raid_setup 641 } 642 }; 643 644 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table); 645 646 #define AHC_394X_SLOT_CHANNEL_A 4 647 #define AHC_394X_SLOT_CHANNEL_B 5 648 649 #define AHC_398X_SLOT_CHANNEL_A 4 650 #define AHC_398X_SLOT_CHANNEL_B 8 651 #define AHC_398X_SLOT_CHANNEL_C 12 652 653 #define AHC_494X_SLOT_CHANNEL_A 4 654 #define AHC_494X_SLOT_CHANNEL_B 5 655 #define AHC_494X_SLOT_CHANNEL_C 6 656 #define AHC_494X_SLOT_CHANNEL_D 7 657 658 #define DEVCONFIG 0x40 659 #define PCIERRGENDIS 0x80000000ul 660 #define SCBSIZE32 0x00010000ul /* aic789X only */ 661 #define REXTVALID 0x00001000ul /* ultra cards only */ 662 #define MPORTMODE 0x00000400ul /* aic7870+ only */ 663 #define RAMPSM 0x00000200ul /* aic7870+ only */ 664 #define VOLSENSE 0x00000100ul 665 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ 666 #define SCBRAMSEL 0x00000080ul 667 #define MRDCEN 0x00000040ul 668 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 669 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 670 #define BERREN 0x00000008ul 671 #define DACEN 0x00000004ul 672 #define STPWLEVEL 0x00000002ul 673 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 674 675 #define CSIZE_LATTIME 0x0c 676 #define CACHESIZE 0x0000003ful /* only 5 bits */ 677 #define LATTIME 0x0000ff00ul 678 679 /* PCI STATUS definitions */ 680 #define DPE 0x80 681 #define SSE 0x40 682 #define RMA 0x20 683 #define RTA 0x10 684 #define STA 0x08 685 #define DPR 0x01 686 687 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device, 688 uint16_t subvendor, uint16_t subdevice); 689 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 690 static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 691 int pcheck, int fast, int large); 692 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 693 694 int ahc_pci_probe __P((struct device *, struct cfdata *, void *)); 695 void ahc_pci_attach __P((struct device *, struct device *, void *)); 696 697 698 CFATTACH_DECL(ahc_pci, sizeof(struct ahc_softc), 699 ahc_pci_probe, ahc_pci_attach, NULL, NULL); 700 701 const struct ahc_pci_identity * 702 ahc_find_pci_device(id, subid, func) 703 pcireg_t id, subid; 704 u_int func; 705 { 706 u_int64_t full_id; 707 const struct ahc_pci_identity *entry; 708 u_int i; 709 710 full_id = ahc_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 711 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 712 713 /* 714 * If the second function is not hooked up, ignore it. 715 * Unfortunately, not all MB vendors implement the 716 * subdevice ID as per the Adaptec spec, so do our best 717 * to sanity check it prior to accepting the subdevice 718 * ID as valid. 719 */ 720 if (func > 0 721 && ahc_9005_subdevinfo_valid(PCI_VENDOR(id), PCI_PRODUCT(id), 722 PCI_VENDOR(subid), PCI_PRODUCT(subid)) 723 && SUBID_9005_MFUNCENB(PCI_PRODUCT(subid)) == 0) 724 return (NULL); 725 726 for (i = 0; i < ahc_num_pci_devs; i++) { 727 entry = &ahc_pci_ident_table[i]; 728 if (entry->full_id == (full_id & entry->id_mask)) 729 return (entry); 730 } 731 return (NULL); 732 } 733 734 int 735 ahc_pci_probe(parent, match, aux) 736 struct device *parent; 737 struct cfdata *match; 738 void *aux; 739 { 740 struct pci_attach_args *pa = aux; 741 const struct ahc_pci_identity *entry; 742 pcireg_t subid; 743 744 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 745 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); 746 return entry != NULL ? 1 : 0; 747 } 748 749 void 750 ahc_pci_attach(parent, self, aux) 751 struct device *parent, *self; 752 void *aux; 753 { 754 struct pci_attach_args *pa = aux; 755 const struct ahc_pci_identity *entry; 756 struct ahc_softc *ahc = (void *)self; 757 pcireg_t command; 758 u_int our_id = 0; 759 u_int sxfrctl1; 760 u_int scsiseq; 761 u_int sblkctl; 762 uint8_t dscommand0; 763 uint32_t devconfig; 764 int error; 765 pcireg_t subid; 766 int ioh_valid, memh_valid; 767 bus_space_tag_t st, iot; 768 bus_space_handle_t sh, ioh; 769 #ifdef AHC_ALLOW_MEMIO 770 bus_space_tag_t memt; 771 bus_space_handle_t memh; 772 pcireg_t memtype; 773 #endif 774 pci_intr_handle_t ih; 775 const char *intrstr; 776 struct ahc_pci_busdata *bd; 777 778 ahc_set_name(ahc, ahc->sc_dev.dv_xname); 779 ahc->parent_dmat = pa->pa_dmat; 780 781 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 782 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 783 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); 784 if (entry == NULL) 785 return; 786 787 /* Keep information about the PCI bus */ 788 bd = malloc(sizeof (struct ahc_pci_busdata), M_DEVBUF, M_NOWAIT); 789 if (bd == NULL) { 790 printf("%s: unable to allocate bus-specific data\n", ahc_name(ahc)); 791 return; 792 } 793 memset(bd, 0, sizeof(struct ahc_pci_busdata)); 794 795 bd->pc = pa->pa_pc; 796 bd->tag = pa->pa_tag; 797 bd->func = pa->pa_function; 798 bd->dev = pa->pa_device; 799 bd->class = pa->pa_class; 800 801 ahc->bd = bd; 802 803 ahc->description = entry->name; 804 805 error = entry->setup(ahc); 806 if (error != 0) 807 return; 808 809 ioh_valid = memh_valid = 0; 810 811 #ifdef AHC_ALLOW_MEMIO 812 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHC_PCI_MEMADDR); 813 switch (memtype) { 814 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 815 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 816 memh_valid = (pci_mapreg_map(pa, AHC_PCI_MEMADDR, 817 memtype, 0, &memt, &memh, NULL, NULL) == 0); 818 break; 819 default: 820 memh_valid = 0; 821 } 822 #endif 823 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_IOADDR, 824 PCI_MAPREG_TYPE_IO, 0, &iot, 825 &ioh, NULL, NULL) == 0); 826 #if 0 827 printf("%s: mem mapping: memt 0x%x, memh 0x%x, iot 0x%x, ioh 0x%lx\n", 828 ahc_name(ahc), memt, (u_int32_t)memh, (u_int32_t)iot, ioh); 829 #endif 830 831 if (ioh_valid) { 832 st = iot; 833 sh = ioh; 834 #ifdef AHC_ALLOW_MEMIO 835 } else if (memh_valid) { 836 st = memt; 837 sh = memh; 838 #endif 839 } else { 840 printf(": unable to map registers\n"); 841 return; 842 } 843 ahc->tag = st; 844 ahc->bsh = sh; 845 846 ahc->chip |= AHC_PCI; 847 /* 848 * Before we continue probing the card, ensure that 849 * its interrupts are *disabled*. We don't want 850 * a misstep to hang the machine in an interrupt 851 * storm. 852 */ 853 ahc_intr_enable(ahc, FALSE); 854 855 /* 856 * XXX somehow reading this once fails on some sparc64 systems. 857 * This may be a problem in the sparc64 PCI code. Doing it 858 * twice works around it. 859 */ 860 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 861 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 862 863 /* 864 * If we need to support high memory, enable dual 865 * address cycles. This bit must be set to enable 866 * high address bit generation even if we are on a 867 * 64bit bus (PCI64BIT set in devconfig). 868 */ 869 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 870 871 if (1/*bootverbose*/) 872 printf("%s: Enabling 39Bit Addressing\n", 873 ahc_name(ahc)); 874 devconfig |= DACEN; 875 } 876 877 /* Ensure that pci error generation, a test feature, is disabled. */ 878 devconfig |= PCIERRGENDIS; 879 880 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); 881 882 /* Ensure busmastering is enabled */ 883 command |= PCI_COMMAND_MASTER_ENABLE;; 884 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 885 886 /* 887 * Disable PCI parity error reporting. Users typically 888 * do this to work around broken PCI chipsets that get 889 * the parity timing wrong and thus generate lots of spurious 890 * errors. 891 */ 892 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0) 893 command &= ~PCI_COMMAND_PARITY_ENABLE; 894 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 895 896 /* On all PCI adapters, we allow SCB paging */ 897 ahc->flags |= AHC_PAGESCBS; 898 error = ahc_softc_init(ahc); 899 if (error != 0) 900 goto error_out; 901 902 ahc->bus_intr = ahc_pci_intr; 903 904 /* Remember how the card was setup in case there is no SEEPROM */ 905 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 906 ahc_pause(ahc); 907 if ((ahc->features & AHC_ULTRA2) != 0) 908 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 909 else 910 our_id = ahc_inb(ahc, SCSIID) & OID; 911 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 912 scsiseq = ahc_inb(ahc, SCSISEQ); 913 } else { 914 sxfrctl1 = STPWEN; 915 our_id = 7; 916 scsiseq = 0; 917 } 918 919 error = ahc_reset(ahc); 920 if (error != 0) 921 goto error_out; 922 923 if ((ahc->features & AHC_DT) != 0) { 924 u_int sfunct; 925 926 /* Perform ALT-Mode Setup */ 927 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 928 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 929 ahc_outb(ahc, OPTIONMODE, 930 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 931 ahc_outb(ahc, SFUNCT, sfunct); 932 933 /* Normal mode setup */ 934 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 935 |TARGCRCENDEN); 936 } 937 938 if (pci_intr_map(pa, &ih)) { 939 printf("%s: couldn't map interrupt\n", ahc_name(ahc)); 940 ahc_free(ahc); 941 return; 942 } 943 intrstr = pci_intr_string(pa->pa_pc, ih); 944 ahc->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahc_intr, ahc); 945 if (ahc->ih == NULL) { 946 printf("%s: couldn't establish interrupt", 947 ahc->sc_dev.dv_xname); 948 if (intrstr != NULL) 949 printf(" at %s", intrstr); 950 printf("\n"); 951 ahc_free(ahc); 952 return; 953 } 954 printf("\n"); 955 if (intrstr != NULL) 956 printf("%s: interrupting at %s\n", ahc_name(ahc), intrstr); 957 958 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 959 dscommand0 |= MPARCKEN|CACHETHEN; 960 if ((ahc->features & AHC_ULTRA2) != 0) { 961 962 /* 963 * DPARCKEN doesn't work correctly on 964 * some MBs so don't use it. 965 */ 966 dscommand0 &= ~DPARCKEN; 967 } 968 969 /* 970 * Handle chips that must have cache line 971 * streaming (dis/en)abled. 972 */ 973 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 974 dscommand0 |= CACHETHEN; 975 976 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 977 dscommand0 &= ~CACHETHEN; 978 979 ahc_outb(ahc, DSCOMMAND0, dscommand0); 980 981 ahc->pci_cachesize = 982 pci_conf_read(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME) & CACHESIZE; 983 ahc->pci_cachesize *= 4; 984 985 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 986 && ahc->pci_cachesize == 4) { 987 pci_conf_write(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME, 0); 988 ahc->pci_cachesize = 0; 989 } 990 991 /* 992 * We cannot perform ULTRA speeds without the presence 993 * of the external precision resistor. 994 */ 995 if ((ahc->features & AHC_ULTRA) != 0) { 996 uint32_t devconfig; 997 998 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 999 if ((devconfig & REXTVALID) == 0) 1000 ahc->features &= ~AHC_ULTRA; 1001 } 1002 1003 ahc->seep_config = malloc(sizeof(*ahc->seep_config), 1004 M_DEVBUF, M_NOWAIT); 1005 if (ahc->seep_config == NULL) 1006 goto error_out; 1007 1008 memset(ahc->seep_config, 0, sizeof(*ahc->seep_config)); 1009 1010 /* See if we have a SEEPROM and perform auto-term */ 1011 ahc_check_extport(ahc, &sxfrctl1); 1012 1013 /* 1014 * Take the LED out of diagnostic mode 1015 */ 1016 sblkctl = ahc_inb(ahc, SBLKCTL); 1017 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 1018 1019 if ((ahc->features & AHC_ULTRA2) != 0) { 1020 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 1021 } else { 1022 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 1023 } 1024 1025 if (ahc->flags & AHC_USEDEFAULTS) { 1026 /* 1027 * PCI Adapter default setup 1028 * Should only be used if the adapter does not have 1029 * a SEEPROM. 1030 */ 1031 /* See if someone else set us up already */ 1032 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0 1033 && scsiseq != 0) { 1034 printf("%s: Using left over BIOS settings\n", 1035 ahc_name(ahc)); 1036 ahc->flags &= ~AHC_USEDEFAULTS; 1037 ahc->flags |= AHC_BIOS_ENABLED; 1038 } else { 1039 /* 1040 * Assume only one connector and always turn 1041 * on termination. 1042 */ 1043 our_id = 0x07; 1044 sxfrctl1 = STPWEN; 1045 } 1046 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 1047 1048 ahc->our_id = our_id; 1049 } 1050 1051 /* 1052 * Take a look to see if we have external SRAM. 1053 * We currently do not attempt to use SRAM that is 1054 * shared among multiple controllers. 1055 */ 1056 ahc_probe_ext_scbram(ahc); 1057 1058 /* 1059 * Record our termination setting for the 1060 * generic initialization routine. 1061 */ 1062 if ((sxfrctl1 & STPWEN) != 0) 1063 ahc->flags |= AHC_TERM_ENB_A; 1064 1065 if (ahc_init(ahc)) 1066 goto error_out; 1067 1068 ahc_attach(ahc); 1069 1070 return; 1071 1072 error_out: 1073 ahc_free(ahc); 1074 return; 1075 } 1076 1077 static int 1078 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, 1079 uint16_t subdevice, uint16_t subvendor) 1080 { 1081 int result; 1082 1083 /* Default to invalid. */ 1084 result = 0; 1085 if (vendor == 0x9005 1086 && subvendor == 0x9005 1087 && subdevice != device 1088 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) { 1089 1090 switch (SUBID_9005_TYPE(subdevice)) { 1091 case SUBID_9005_TYPE_MB: 1092 break; 1093 case SUBID_9005_TYPE_CARD: 1094 case SUBID_9005_TYPE_LCCARD: 1095 /* 1096 * Currently only trust Adaptec cards to 1097 * get the sub device info correct. 1098 */ 1099 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA) 1100 result = 1; 1101 break; 1102 case SUBID_9005_TYPE_RAID: 1103 break; 1104 default: 1105 break; 1106 } 1107 } 1108 return (result); 1109 } 1110 1111 1112 /* 1113 * Test for the presense of external sram in an 1114 * "unshared" configuration. 1115 */ 1116 static int 1117 ahc_ext_scbram_present(struct ahc_softc *ahc) 1118 { 1119 u_int chip; 1120 int ramps; 1121 int single_user; 1122 uint32_t devconfig; 1123 1124 chip = ahc->chip & AHC_CHIPID_MASK; 1125 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1126 single_user = (devconfig & MPORTMODE) != 0; 1127 1128 if ((ahc->features & AHC_ULTRA2) != 0) 1129 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 1130 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C) 1131 /* 1132 * External SCBRAM arbitration is flakey 1133 * on these chips. Unfortunately this means 1134 * we don't use the extra SCB ram space on the 1135 * 3940AUW. 1136 */ 1137 ramps = 0; 1138 else if (chip >= AHC_AIC7870) 1139 ramps = (devconfig & RAMPSM) != 0; 1140 else 1141 ramps = 0; 1142 1143 if (ramps && single_user) 1144 return (1); 1145 return (0); 1146 } 1147 1148 /* 1149 * Enable external scbram. 1150 */ 1151 static void 1152 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 1153 int fast, int large) 1154 { 1155 uint32_t devconfig; 1156 1157 if (ahc->features & AHC_MULTI_FUNC) { 1158 /* 1159 * Set the SCB Base addr (highest address bit) 1160 * depending on which channel we are. 1161 */ 1162 ahc_outb(ahc, SCBBADDR, ahc->bd->func); 1163 } 1164 1165 ahc->flags &= ~AHC_LSCBS_ENABLED; 1166 if (large) 1167 ahc->flags |= AHC_LSCBS_ENABLED; 1168 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1169 if ((ahc->features & AHC_ULTRA2) != 0) { 1170 u_int dscommand0; 1171 1172 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1173 if (enable) 1174 dscommand0 &= ~INTSCBRAMSEL; 1175 else 1176 dscommand0 |= INTSCBRAMSEL; 1177 if (large) 1178 dscommand0 &= ~USCBSIZE32; 1179 else 1180 dscommand0 |= USCBSIZE32; 1181 ahc_outb(ahc, DSCOMMAND0, dscommand0); 1182 } else { 1183 if (fast) 1184 devconfig &= ~EXTSCBTIME; 1185 else 1186 devconfig |= EXTSCBTIME; 1187 if (enable) 1188 devconfig &= ~SCBRAMSEL; 1189 else 1190 devconfig |= SCBRAMSEL; 1191 if (large) 1192 devconfig &= ~SCBSIZE32; 1193 else 1194 devconfig |= SCBSIZE32; 1195 } 1196 if (pcheck) 1197 devconfig |= EXTSCBPEN; 1198 else 1199 devconfig &= ~EXTSCBPEN; 1200 1201 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig); 1202 } 1203 1204 /* 1205 * Take a look to see if we have external SRAM. 1206 * We currently do not attempt to use SRAM that is 1207 * shared among multiple controllers. 1208 */ 1209 static void 1210 ahc_probe_ext_scbram(struct ahc_softc *ahc) 1211 { 1212 int num_scbs; 1213 int test_num_scbs; 1214 int enable; 1215 int pcheck; 1216 int fast; 1217 int large; 1218 1219 enable = FALSE; 1220 pcheck = FALSE; 1221 fast = FALSE; 1222 large = FALSE; 1223 num_scbs = 0; 1224 1225 if (ahc_ext_scbram_present(ahc) == 0) 1226 goto done; 1227 1228 /* 1229 * Probe for the best parameters to use. 1230 */ 1231 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 1232 num_scbs = ahc_probe_scbs(ahc); 1233 if (num_scbs == 0) { 1234 /* The SRAM wasn't really present. */ 1235 goto done; 1236 } 1237 enable = TRUE; 1238 1239 /* 1240 * Clear any outstanding parity error 1241 * and ensure that parity error reporting 1242 * is enabled. 1243 */ 1244 ahc_outb(ahc, SEQCTL, 0); 1245 ahc_outb(ahc, CLRINT, CLRPARERR); 1246 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1247 1248 /* Now see if we can do parity */ 1249 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1250 num_scbs = ahc_probe_scbs(ahc); 1251 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1252 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1253 pcheck = TRUE; 1254 1255 /* Clear any resulting parity error */ 1256 ahc_outb(ahc, CLRINT, CLRPARERR); 1257 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1258 1259 /* Now see if we can do fast timing */ 1260 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1261 test_num_scbs = ahc_probe_scbs(ahc); 1262 if (test_num_scbs == num_scbs 1263 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1264 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1265 fast = TRUE; 1266 1267 /* 1268 * See if we can use large SCBs and still maintain 1269 * the same overall count of SCBs. 1270 */ 1271 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1272 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1273 test_num_scbs = ahc_probe_scbs(ahc); 1274 if (test_num_scbs >= num_scbs) { 1275 large = TRUE; 1276 num_scbs = test_num_scbs; 1277 if (num_scbs >= 64) { 1278 /* 1279 * We have enough space to move the 1280 * "busy targets table" into SCB space 1281 * and make it qualify all the way to the 1282 * lun level. 1283 */ 1284 ahc->flags |= AHC_SCB_BTT; 1285 } 1286 } 1287 } 1288 done: 1289 /* 1290 * Disable parity error reporting until we 1291 * can load instruction ram. 1292 */ 1293 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1294 /* Clear any latched parity error */ 1295 ahc_outb(ahc, CLRINT, CLRPARERR); 1296 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1297 if (1/*bootverbose*/ && enable) { 1298 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1299 ahc_name(ahc), fast ? "fast" : "slow", 1300 pcheck ? ", parity checking enabled" : "", 1301 large ? 64 : 32); 1302 } 1303 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1304 } 1305 1306 #if 0 1307 /* 1308 * Perform some simple tests that should catch situations where 1309 * our registers are invalidly mapped. 1310 */ 1311 int 1312 ahc_pci_test_register_access(struct ahc_softc *ahc) 1313 { 1314 int error; 1315 u_int status1; 1316 uint32_t cmd; 1317 uint8_t hcntrl; 1318 1319 error = EIO; 1320 1321 /* 1322 * Enable PCI error interrupt status, but suppress NMIs 1323 * generated by SERR raised due to target aborts. 1324 */ 1325 cmd = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND); 1326 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND, 1327 cmd & ~PCIM_CMD_SERRESPEN); 1328 1329 /* 1330 * First a simple test to see if any 1331 * registers can be read. Reading 1332 * HCNTRL has no side effects and has 1333 * at least one bit that is guaranteed to 1334 * be zero so it is a good register to 1335 * use for this test. 1336 */ 1337 hcntrl = ahc_inb(ahc, HCNTRL); 1338 if (hcntrl == 0xFF) 1339 goto fail; 1340 1341 /* 1342 * Next create a situation where write combining 1343 * or read prefetching could be initiated by the 1344 * CPU or host bridge. Our device does not support 1345 * either, so look for data corruption and/or flagged 1346 * PCI errors. 1347 */ 1348 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE); 1349 while (ahc_is_paused(ahc) == 0) 1350 ; 1351 ahc_outb(ahc, SEQCTL, PERRORDIS); 1352 ahc_outb(ahc, SCBPTR, 0); 1353 ahc_outl(ahc, SCB_BASE, 0x5aa555aa); 1354 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa) 1355 goto fail; 1356 1357 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1358 PCI_COMMAND_STATUS_REG + 1); 1359 if ((status1 & STA) != 0) 1360 goto fail; 1361 1362 error = 0; 1363 1364 fail: 1365 /* Silently clear any latched errors. */ 1366 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG + 1); 1367 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1368 status1, /*bytes*/1); 1369 ahc_outb(ahc, CLRINT, CLRPARERR); 1370 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1371 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 1372 return (error); 1373 } 1374 #endif 1375 1376 void 1377 ahc_pci_intr(struct ahc_softc *ahc) 1378 { 1379 u_int error; 1380 u_int status1; 1381 1382 error = ahc_inb(ahc, ERROR); 1383 if ((error & PCIERRSTAT) == 0) 1384 return; 1385 1386 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG); 1387 1388 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1389 ahc_name(ahc), 1390 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1391 1392 if (status1 & DPE) { 1393 printf("%s: Data Parity Error Detected during address " 1394 "or write data phase\n", ahc_name(ahc)); 1395 } 1396 if (status1 & SSE) { 1397 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1398 } 1399 if (status1 & RMA) { 1400 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1401 } 1402 if (status1 & RTA) { 1403 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1404 } 1405 if (status1 & STA) { 1406 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1407 } 1408 if (status1 & DPR) { 1409 printf("%s: Data Parity Error has been reported via PERR#\n", 1410 ahc_name(ahc)); 1411 } 1412 1413 /* Clear latched errors. */ 1414 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG, status1); 1415 1416 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1417 printf("%s: Latched PCIERR interrupt with " 1418 "no status bits set\n", ahc_name(ahc)); 1419 } else { 1420 ahc_outb(ahc, CLRINT, CLRPARERR); 1421 } 1422 1423 ahc_unpause(ahc); 1424 } 1425 1426 static int 1427 ahc_aic785X_setup(struct ahc_softc *ahc) 1428 { 1429 uint8_t rev; 1430 1431 ahc->channel = 'A'; 1432 ahc->chip = AHC_AIC7850; 1433 ahc->features = AHC_AIC7850_FE; 1434 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1435 rev = PCI_REVISION(ahc->bd->class); 1436 if (rev >= 1) 1437 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1438 return (0); 1439 } 1440 1441 static int 1442 ahc_aic7860_setup(struct ahc_softc *ahc) 1443 { 1444 uint8_t rev; 1445 1446 ahc->channel = 'A'; 1447 ahc->chip = AHC_AIC7860; 1448 ahc->features = AHC_AIC7860_FE; 1449 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1450 rev = PCI_REVISION(ahc->bd->class); 1451 if (rev >= 1) 1452 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1453 return (0); 1454 } 1455 1456 static int 1457 ahc_apa1480_setup(struct ahc_softc *ahc) 1458 { 1459 int error; 1460 1461 error = ahc_aic7860_setup(ahc); 1462 if (error != 0) 1463 return (error); 1464 ahc->features |= AHC_REMOVABLE; 1465 return (0); 1466 } 1467 1468 static int 1469 ahc_aic7870_setup(struct ahc_softc *ahc) 1470 { 1471 1472 ahc->channel = 'A'; 1473 ahc->chip = AHC_AIC7870; 1474 ahc->features = AHC_AIC7870_FE; 1475 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1476 return (0); 1477 } 1478 1479 static int 1480 ahc_aha394X_setup(struct ahc_softc *ahc) 1481 { 1482 int error; 1483 1484 error = ahc_aic7870_setup(ahc); 1485 if (error == 0) 1486 error = ahc_aha394XX_setup(ahc); 1487 return (error); 1488 } 1489 1490 static int 1491 ahc_aha398X_setup(struct ahc_softc *ahc) 1492 { 1493 int error; 1494 1495 error = ahc_aic7870_setup(ahc); 1496 if (error == 0) 1497 error = ahc_aha398XX_setup(ahc); 1498 return (error); 1499 } 1500 1501 static int 1502 ahc_aha494X_setup(struct ahc_softc *ahc) 1503 { 1504 int error; 1505 1506 error = ahc_aic7870_setup(ahc); 1507 if (error == 0) 1508 error = ahc_aha494XX_setup(ahc); 1509 return (error); 1510 } 1511 1512 static int 1513 ahc_aic7880_setup(struct ahc_softc *ahc) 1514 { 1515 uint8_t rev; 1516 1517 ahc->channel = 'A'; 1518 ahc->chip = AHC_AIC7880; 1519 ahc->features = AHC_AIC7880_FE; 1520 ahc->bugs |= AHC_TMODE_WIDEODD_BUG; 1521 rev = PCI_REVISION(ahc->bd->class); 1522 if (rev >= 1) { 1523 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1524 } else { 1525 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1526 } 1527 return (0); 1528 } 1529 1530 static int 1531 ahc_aha2940Pro_setup(struct ahc_softc *ahc) 1532 { 1533 1534 ahc->flags |= AHC_INT50_SPEEDFLEX; 1535 return (ahc_aic7880_setup(ahc)); 1536 } 1537 1538 static int 1539 ahc_aha394XU_setup(struct ahc_softc *ahc) 1540 { 1541 int error; 1542 1543 error = ahc_aic7880_setup(ahc); 1544 if (error == 0) 1545 error = ahc_aha394XX_setup(ahc); 1546 return (error); 1547 } 1548 1549 static int 1550 ahc_aha398XU_setup(struct ahc_softc *ahc) 1551 { 1552 int error; 1553 1554 error = ahc_aic7880_setup(ahc); 1555 if (error == 0) 1556 error = ahc_aha398XX_setup(ahc); 1557 return (error); 1558 } 1559 1560 static int 1561 ahc_aic7890_setup(struct ahc_softc *ahc) 1562 { 1563 uint8_t rev; 1564 1565 ahc->channel = 'A'; 1566 ahc->chip = AHC_AIC7890; 1567 ahc->features = AHC_AIC7890_FE; 1568 ahc->flags |= AHC_NEWEEPROM_FMT; 1569 rev = PCI_REVISION(ahc->bd->class); 1570 if (rev == 0) 1571 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 1572 return (0); 1573 } 1574 1575 static int 1576 ahc_aic7892_setup(struct ahc_softc *ahc) 1577 { 1578 1579 ahc->channel = 'A'; 1580 ahc->chip = AHC_AIC7892; 1581 ahc->features = AHC_AIC7892_FE; 1582 ahc->flags |= AHC_NEWEEPROM_FMT; 1583 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1584 return (0); 1585 } 1586 1587 static int 1588 ahc_aic7895_setup(struct ahc_softc *ahc) 1589 { 1590 uint8_t rev; 1591 1592 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1593 /* 1594 * The 'C' revision of the aic7895 has a few additional features. 1595 */ 1596 rev = PCI_REVISION(ahc->bd->class); 1597 if (rev >= 4) { 1598 ahc->chip = AHC_AIC7895C; 1599 ahc->features = AHC_AIC7895C_FE; 1600 } else { 1601 u_int command; 1602 1603 ahc->chip = AHC_AIC7895; 1604 ahc->features = AHC_AIC7895_FE; 1605 1606 /* 1607 * The BIOS disables the use of MWI transactions 1608 * since it does not have the MWI bug work around 1609 * we have. Disabling MWI reduces performance, so 1610 * turn it on again. 1611 */ 1612 command = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG); 1613 command |= PCI_COMMAND_INVALIDATE_ENABLE; 1614 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG, command); 1615 ahc->bugs |= AHC_PCI_MWI_BUG; 1616 } 1617 /* 1618 * XXX Does CACHETHEN really not work??? What about PCI retry? 1619 * on C level chips. Need to test, but for now, play it safe. 1620 */ 1621 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 1622 | AHC_CACHETHEN_BUG; 1623 1624 #if 0 1625 uint32_t devconfig; 1626 1627 /* 1628 * Cachesize must also be zero due to stray DAC 1629 * problem when sitting behind some bridges. 1630 */ 1631 pci_conf_write(ahc->bd->pc, ahc->bd->tag, CSIZE_LATTIME, 0); 1632 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1633 devconfig |= MRDCEN; 1634 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig); 1635 #endif 1636 ahc->flags |= AHC_NEWEEPROM_FMT; 1637 return (0); 1638 } 1639 1640 static int 1641 ahc_aic7896_setup(struct ahc_softc *ahc) 1642 { 1643 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1644 ahc->chip = AHC_AIC7896; 1645 ahc->features = AHC_AIC7896_FE; 1646 ahc->flags |= AHC_NEWEEPROM_FMT; 1647 ahc->bugs |= AHC_CACHETHEN_DIS_BUG; 1648 return (0); 1649 } 1650 1651 static int 1652 ahc_aic7899_setup(struct ahc_softc *ahc) 1653 { 1654 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1655 ahc->chip = AHC_AIC7899; 1656 ahc->features = AHC_AIC7899_FE; 1657 ahc->flags |= AHC_NEWEEPROM_FMT; 1658 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1659 return (0); 1660 } 1661 1662 static int 1663 ahc_aha29160C_setup(struct ahc_softc *ahc) 1664 { 1665 int error; 1666 1667 error = ahc_aic7899_setup(ahc); 1668 if (error != 0) 1669 return (error); 1670 ahc->features |= AHC_REMOVABLE; 1671 return (0); 1672 } 1673 1674 static int 1675 ahc_raid_setup(struct ahc_softc *ahc) 1676 { 1677 printf("RAID functionality unsupported\n"); 1678 return (ENXIO); 1679 } 1680 1681 static int 1682 ahc_aha394XX_setup(struct ahc_softc *ahc) 1683 { 1684 1685 switch (ahc->bd->dev) { 1686 case AHC_394X_SLOT_CHANNEL_A: 1687 ahc->channel = 'A'; 1688 break; 1689 case AHC_394X_SLOT_CHANNEL_B: 1690 ahc->channel = 'B'; 1691 break; 1692 default: 1693 printf("adapter at unexpected slot %d\n" 1694 "unable to map to a channel\n", 1695 ahc->bd->dev); 1696 ahc->channel = 'A'; 1697 } 1698 return (0); 1699 } 1700 1701 static int 1702 ahc_aha398XX_setup(struct ahc_softc *ahc) 1703 { 1704 1705 switch (ahc->bd->dev) { 1706 case AHC_398X_SLOT_CHANNEL_A: 1707 ahc->channel = 'A'; 1708 break; 1709 case AHC_398X_SLOT_CHANNEL_B: 1710 ahc->channel = 'B'; 1711 break; 1712 case AHC_398X_SLOT_CHANNEL_C: 1713 ahc->channel = 'C'; 1714 break; 1715 default: 1716 printf("adapter at unexpected slot %d\n" 1717 "unable to map to a channel\n", 1718 ahc->bd->dev); 1719 ahc->channel = 'A'; 1720 break; 1721 } 1722 ahc->flags |= AHC_LARGE_SEEPROM; 1723 return (0); 1724 } 1725 1726 static int 1727 ahc_aha494XX_setup(struct ahc_softc *ahc) 1728 { 1729 1730 switch (ahc->bd->dev) { 1731 case AHC_494X_SLOT_CHANNEL_A: 1732 ahc->channel = 'A'; 1733 break; 1734 case AHC_494X_SLOT_CHANNEL_B: 1735 ahc->channel = 'B'; 1736 break; 1737 case AHC_494X_SLOT_CHANNEL_C: 1738 ahc->channel = 'C'; 1739 break; 1740 case AHC_494X_SLOT_CHANNEL_D: 1741 ahc->channel = 'D'; 1742 break; 1743 default: 1744 printf("adapter at unexpected slot %d\n" 1745 "unable to map to a channel\n", 1746 ahc->bd->dev); 1747 ahc->channel = 'A'; 1748 } 1749 ahc->flags |= AHC_LARGE_SEEPROM; 1750 return (0); 1751 } 1752
Indexes created Wed Oct 01 19:09:53 GMT 2025