ahc_pci.c revision 1.42
1 /* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1994-2001 Justin T. Gibbs. 7 * Copyright (c) 2000-2001 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: ahc_pci.c,v 1.42 2003/07/14 15:47:22 lukem Exp $ 43 * 44 * //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#57 $ 45 * 46 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.22 2003/01/20 20:44:55 gibbs Exp $ 47 */ 48 /* 49 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: ahc_pci.c,v 1.42 2003/07/14 15:47:22 lukem Exp $"); 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/queue.h> 60 #include <sys/device.h> 61 #include <sys/reboot.h> 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 #define AHC_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 70 #define AHC_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 71 72 #include <dev/ic/aic7xxx_osm.h> 73 #include <dev/ic/aic7xxx_inline.h> 74 75 #include <dev/ic/smc93cx6var.h> 76 77 78 static __inline uint64_t 79 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 80 { 81 uint64_t id; 82 83 id = subvendor 84 | (subdevice << 16) 85 | ((uint64_t)vendor << 32) 86 | ((uint64_t)device << 48); 87 88 return (id); 89 } 90 91 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 92 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 93 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 94 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull 95 #define ID_9005_SISL_ID 0x0005900500000000ull 96 #define ID_AIC7850 0x5078900400000000ull 97 #define ID_AHA_2902_04_10_15_20_30C 0x5078900478509004ull 98 #define ID_AIC7855 0x5578900400000000ull 99 #define ID_AIC7859 0x3860900400000000ull 100 #define ID_AHA_2930CU 0x3860900438699004ull 101 #define ID_AIC7860 0x6078900400000000ull 102 #define ID_AIC7860C 0x6078900478609004ull 103 #define ID_AHA_1480A 0x6075900400000000ull 104 #define ID_AHA_2940AU_0 0x6178900400000000ull 105 #define ID_AHA_2940AU_1 0x6178900478619004ull 106 #define ID_AHA_2940AU_CN 0x2178900478219004ull 107 #define ID_AHA_2930C_VAR 0x6038900438689004ull 108 109 #define ID_AIC7870 0x7078900400000000ull 110 #define ID_AHA_2940 0x7178900400000000ull 111 #define ID_AHA_3940 0x7278900400000000ull 112 #define ID_AHA_398X 0x7378900400000000ull 113 #define ID_AHA_2944 0x7478900400000000ull 114 #define ID_AHA_3944 0x7578900400000000ull 115 #define ID_AHA_4944 0x7678900400000000ull 116 117 #define ID_AIC7880 0x8078900400000000ull 118 #define ID_AIC7880_B 0x8078900478809004ull 119 #define ID_AHA_2940U 0x8178900400000000ull 120 #define ID_AHA_3940U 0x8278900400000000ull 121 #define ID_AHA_2944U 0x8478900400000000ull 122 #define ID_AHA_3944U 0x8578900400000000ull 123 #define ID_AHA_398XU 0x8378900400000000ull 124 #define ID_AHA_4944U 0x8678900400000000ull 125 #define ID_AHA_2940UB 0x8178900478819004ull 126 #define ID_AHA_2930U 0x8878900478889004ull 127 #define ID_AHA_2940U_PRO 0x8778900478879004ull 128 #define ID_AHA_2940U_CN 0x0078900478009004ull 129 130 #define ID_AIC7895 0x7895900478959004ull 131 #define ID_AIC7895_ARO 0x7890900478939004ull 132 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull 133 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 134 #define ID_AHA_3940AU 0x7895900478929004ull 135 #define ID_AHA_3944AU 0x7895900478949004ull 136 137 #define ID_AIC7890 0x001F9005000F9005ull 138 #define ID_AIC7890_ARO 0x00139005000F9005ull 139 #define ID_AAA_131U2 0x0013900500039005ull 140 #define ID_AHA_2930U2 0x0011900501819005ull 141 #define ID_AHA_2940U2B 0x00109005A1009005ull 142 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 143 #define ID_AHA_2940U2 0x00109005A1809005ull 144 #define ID_AHA_2950U2B 0x00109005E1009005ull 145 146 #define ID_AIC7892 0x008F9005FFFF9005ull 147 #define ID_AIC7892_ARO 0x00839005FFFF9005ull 148 #define ID_AHA_29160 0x00809005E2A09005ull 149 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 150 #define ID_AHA_29160N 0x0080900562A09005ull 151 #define ID_AHA_29160C 0x0080900562209005ull 152 #define ID_AHA_29160B 0x00809005E2209005ull 153 #define ID_AHA_19160B 0x0081900562A19005ull 154 155 #define ID_AIC7896 0x005F9005FFFF9005ull 156 #define ID_AIC7896_ARO 0x00539005FFFF9005ull 157 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 158 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 159 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 160 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 161 162 #define ID_AIC7899 0x00CF9005FFFF9005ull 163 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull 164 #define ID_AHA_3960D 0x00C09005F6209005ull 165 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 166 167 #define ID_AIC7810 0x1078900400000000ull 168 #define ID_AIC7815 0x7815900400000000ull 169 170 #define DEVID_9005_TYPE(id) ((id) & 0xF) 171 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 172 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ 173 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */ 174 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 175 176 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 177 #define DEVID_9005_MAXRATE_U160 0x0 178 #define DEVID_9005_MAXRATE_ULTRA2 0x1 179 #define DEVID_9005_MAXRATE_ULTRA 0x2 180 #define DEVID_9005_MAXRATE_FAST 0x3 181 182 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) 183 184 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) 185 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ 186 187 #define SUBID_9005_TYPE(id) ((id) & 0xF) 188 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 189 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 190 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 191 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 192 193 #define SUBID_9005_TYPE_KNOWN(id) \ 194 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ 195 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ 196 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ 197 || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) 198 199 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 200 #define SUBID_9005_MAXRATE_ULTRA2 0x0 201 #define SUBID_9005_MAXRATE_ULTRA 0x1 202 #define SUBID_9005_MAXRATE_U160 0x2 203 #define SUBID_9005_MAXRATE_RESERVED 0x3 204 205 #define SUBID_9005_SEEPTYPE(id) \ 206 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 207 ? ((id) & 0xC0) >> 6 \ 208 : ((id) & 0x300) >> 8) 209 #define SUBID_9005_SEEPTYPE_NONE 0x0 210 #define SUBID_9005_SEEPTYPE_1K 0x1 211 #define SUBID_9005_SEEPTYPE_2K_4K 0x2 212 #define SUBID_9005_SEEPTYPE_RESERVED 0x3 213 #define SUBID_9005_AUTOTERM(id) \ 214 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 215 ? (((id) & 0x400) >> 10) == 0 \ 216 : (((id) & 0x40) >> 6) == 0) 217 218 #define SUBID_9005_NUMCHAN(id) \ 219 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 220 ? ((id) & 0x300) >> 8 \ 221 : ((id) & 0xC00) >> 10) 222 223 #define SUBID_9005_LEGACYCONN(id) \ 224 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 225 ? 0 \ 226 : ((id) & 0x80) >> 7) 227 228 #define SUBID_9005_MFUNCENB(id) \ 229 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 230 ? ((id) & 0x800) >> 11 \ 231 : ((id) & 0x1000) >> 12) 232 /* 233 * Informational only. Should use chip register to be 234 * certain, but may be use in identification strings. 235 */ 236 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 237 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 238 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000 239 240 static ahc_device_setup_t ahc_aic785X_setup; 241 static ahc_device_setup_t ahc_aic7860_setup; 242 static ahc_device_setup_t ahc_apa1480_setup; 243 static ahc_device_setup_t ahc_aic7870_setup; 244 static ahc_device_setup_t ahc_aha394X_setup; 245 static ahc_device_setup_t ahc_aha494X_setup; 246 static ahc_device_setup_t ahc_aha398X_setup; 247 static ahc_device_setup_t ahc_aic7880_setup; 248 static ahc_device_setup_t ahc_aha2940Pro_setup; 249 static ahc_device_setup_t ahc_aha394XU_setup; 250 static ahc_device_setup_t ahc_aha398XU_setup; 251 static ahc_device_setup_t ahc_aic7890_setup; 252 static ahc_device_setup_t ahc_aic7892_setup; 253 static ahc_device_setup_t ahc_aic7895_setup; 254 static ahc_device_setup_t ahc_aic7896_setup; 255 static ahc_device_setup_t ahc_aic7899_setup; 256 static ahc_device_setup_t ahc_aha29160C_setup; 257 static ahc_device_setup_t ahc_raid_setup; 258 static ahc_device_setup_t ahc_aha394XX_setup; 259 static ahc_device_setup_t ahc_aha494XX_setup; 260 static ahc_device_setup_t ahc_aha398XX_setup; 261 262 struct ahc_pci_identity ahc_pci_ident_table [] = 263 { 264 /* aic7850 based controllers */ 265 { 266 ID_AHA_2902_04_10_15_20_30C, 267 ID_ALL_MASK, 268 "Adaptec 2902/04/10/15/20/30C SCSI adapter", 269 ahc_aic785X_setup 270 }, 271 /* aic7860 based controllers */ 272 { 273 ID_AHA_2930CU, 274 ID_ALL_MASK, 275 "Adaptec 2930CU SCSI adapter", 276 ahc_aic7860_setup 277 }, 278 { 279 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 280 ID_DEV_VENDOR_MASK, 281 "Adaptec 1480A Ultra SCSI adapter", 282 ahc_apa1480_setup 283 }, 284 { 285 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 286 ID_DEV_VENDOR_MASK, 287 "Adaptec 2940A Ultra SCSI adapter", 288 ahc_aic7860_setup 289 }, 290 { 291 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 292 ID_DEV_VENDOR_MASK, 293 "Adaptec 2940A/CN Ultra SCSI adapter", 294 ahc_aic7860_setup 295 }, 296 { 297 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 298 ID_DEV_VENDOR_MASK, 299 "Adaptec 2930C Ultra SCSI adapter (VAR)", 300 ahc_aic7860_setup 301 }, 302 /* aic7870 based controllers */ 303 { 304 ID_AHA_2940, 305 ID_ALL_MASK, 306 "Adaptec 2940 SCSI adapter", 307 ahc_aic7870_setup 308 }, 309 { 310 ID_AHA_3940, 311 ID_ALL_MASK, 312 "Adaptec 3940 SCSI adapter", 313 ahc_aha394X_setup 314 }, 315 { 316 ID_AHA_398X, 317 ID_ALL_MASK, 318 "Adaptec 398X SCSI RAID adapter", 319 ahc_aha398X_setup 320 }, 321 { 322 ID_AHA_2944, 323 ID_ALL_MASK, 324 "Adaptec 2944 SCSI adapter", 325 ahc_aic7870_setup 326 }, 327 { 328 ID_AHA_3944, 329 ID_ALL_MASK, 330 "Adaptec 3944 SCSI adapter", 331 ahc_aha394X_setup 332 }, 333 { 334 ID_AHA_4944, 335 ID_ALL_MASK, 336 "Adaptec 4944 SCSI adapter", 337 ahc_aha494X_setup 338 }, 339 /* aic7880 based controllers */ 340 { 341 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 342 ID_DEV_VENDOR_MASK, 343 "Adaptec 2940 Ultra SCSI adapter", 344 ahc_aic7880_setup 345 }, 346 { 347 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 348 ID_DEV_VENDOR_MASK, 349 "Adaptec 3940 Ultra SCSI adapter", 350 ahc_aha394XU_setup 351 }, 352 { 353 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 354 ID_DEV_VENDOR_MASK, 355 "Adaptec 2944 Ultra SCSI adapter", 356 ahc_aic7880_setup 357 }, 358 { 359 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 360 ID_DEV_VENDOR_MASK, 361 "Adaptec 3944 Ultra SCSI adapter", 362 ahc_aha394XU_setup 363 }, 364 { 365 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 366 ID_DEV_VENDOR_MASK, 367 "Adaptec 398X Ultra SCSI RAID adapter", 368 ahc_aha398XU_setup 369 }, 370 { 371 /* 372 * XXX Don't know the slot numbers 373 * so we can't identify channels 374 */ 375 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 376 ID_DEV_VENDOR_MASK, 377 "Adaptec 4944 Ultra SCSI adapter", 378 ahc_aic7880_setup 379 }, 380 { 381 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 382 ID_DEV_VENDOR_MASK, 383 "Adaptec 2930 Ultra SCSI adapter", 384 ahc_aic7880_setup 385 }, 386 { 387 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 388 ID_DEV_VENDOR_MASK, 389 "Adaptec 2940 Pro Ultra SCSI adapter", 390 ahc_aha2940Pro_setup 391 }, 392 { 393 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 394 ID_DEV_VENDOR_MASK, 395 "Adaptec 2940/CN Ultra SCSI adapter", 396 ahc_aic7880_setup 397 }, 398 /* Ignore all SISL (AAC on MB) based controllers. */ 399 { 400 ID_9005_SISL_ID, 401 ID_9005_SISL_MASK, 402 NULL, 403 NULL 404 }, 405 /* aic7890 based controllers */ 406 { 407 ID_AHA_2930U2, 408 ID_ALL_MASK, 409 "Adaptec 2930 Ultra2 SCSI adapter", 410 ahc_aic7890_setup 411 }, 412 { 413 ID_AHA_2940U2B, 414 ID_ALL_MASK, 415 "Adaptec 2940B Ultra2 SCSI adapter", 416 ahc_aic7890_setup 417 }, 418 { 419 ID_AHA_2940U2_OEM, 420 ID_ALL_MASK, 421 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 422 ahc_aic7890_setup 423 }, 424 { 425 ID_AHA_2940U2, 426 ID_ALL_MASK, 427 "Adaptec 2940 Ultra2 SCSI adapter", 428 ahc_aic7890_setup 429 }, 430 { 431 ID_AHA_2950U2B, 432 ID_ALL_MASK, 433 "Adaptec 2950 Ultra2 SCSI adapter", 434 ahc_aic7890_setup 435 }, 436 { 437 ID_AIC7890_ARO, 438 ID_ALL_MASK, 439 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)", 440 ahc_aic7890_setup 441 }, 442 { 443 ID_AAA_131U2, 444 ID_ALL_MASK, 445 "Adaptec AAA-131 Ultra2 RAID adapter", 446 ahc_aic7890_setup 447 }, 448 /* aic7892 based controllers */ 449 { 450 ID_AHA_29160, 451 ID_ALL_MASK, 452 "Adaptec 29160 Ultra160 SCSI adapter", 453 ahc_aic7892_setup 454 }, 455 { 456 ID_AHA_29160_CPQ, 457 ID_ALL_MASK, 458 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 459 ahc_aic7892_setup 460 }, 461 { 462 ID_AHA_29160N, 463 ID_ALL_MASK, 464 "Adaptec 29160N Ultra160 SCSI adapter", 465 ahc_aic7892_setup 466 }, 467 { 468 ID_AHA_29160C, 469 ID_ALL_MASK, 470 "Adaptec 29160C Ultra160 SCSI adapter", 471 ahc_aha29160C_setup 472 }, 473 { 474 ID_AHA_29160B, 475 ID_ALL_MASK, 476 "Adaptec 29160B Ultra160 SCSI adapter", 477 ahc_aic7892_setup 478 }, 479 { 480 ID_AHA_19160B, 481 ID_ALL_MASK, 482 "Adaptec 19160B Ultra160 SCSI adapter", 483 ahc_aic7892_setup 484 }, 485 { 486 ID_AIC7892_ARO, 487 ID_ALL_MASK, 488 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)", 489 ahc_aic7892_setup 490 }, 491 /* aic7895 based controllers */ 492 { 493 ID_AHA_2940U_DUAL, 494 ID_ALL_MASK, 495 "Adaptec 2940/DUAL Ultra SCSI adapter", 496 ahc_aic7895_setup 497 }, 498 { 499 ID_AHA_3940AU, 500 ID_ALL_MASK, 501 "Adaptec 3940A Ultra SCSI adapter", 502 ahc_aic7895_setup 503 }, 504 { 505 ID_AHA_3944AU, 506 ID_ALL_MASK, 507 "Adaptec 3944A Ultra SCSI adapter", 508 ahc_aic7895_setup 509 }, 510 { 511 ID_AIC7895_ARO, 512 ID_AIC7895_ARO_MASK, 513 "Adaptec aic7895 Ultra SCSI adapter (ARO)", 514 ahc_aic7895_setup 515 }, 516 /* aic7896/97 based controllers */ 517 { 518 ID_AHA_3950U2B_0, 519 ID_ALL_MASK, 520 "Adaptec 3950B Ultra2 SCSI adapter", 521 ahc_aic7896_setup 522 }, 523 { 524 ID_AHA_3950U2B_1, 525 ID_ALL_MASK, 526 "Adaptec 3950B Ultra2 SCSI adapter", 527 ahc_aic7896_setup 528 }, 529 { 530 ID_AHA_3950U2D_0, 531 ID_ALL_MASK, 532 "Adaptec 3950D Ultra2 SCSI adapter", 533 ahc_aic7896_setup 534 }, 535 { 536 ID_AHA_3950U2D_1, 537 ID_ALL_MASK, 538 "Adaptec 3950D Ultra2 SCSI adapter", 539 ahc_aic7896_setup 540 }, 541 { 542 ID_AIC7896_ARO, 543 ID_ALL_MASK, 544 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)", 545 ahc_aic7896_setup 546 }, 547 /* aic7899 based controllers */ 548 { 549 ID_AHA_3960D, 550 ID_ALL_MASK, 551 "Adaptec 3960D Ultra160 SCSI adapter", 552 ahc_aic7899_setup 553 }, 554 { 555 ID_AHA_3960D_CPQ, 556 ID_ALL_MASK, 557 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 558 ahc_aic7899_setup 559 }, 560 { 561 ID_AIC7899_ARO, 562 ID_ALL_MASK, 563 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)", 564 ahc_aic7899_setup 565 }, 566 /* Generic chip probes for devices we don't know 'exactly' */ 567 { 568 ID_AIC7850 & ID_DEV_VENDOR_MASK, 569 ID_DEV_VENDOR_MASK, 570 "Adaptec aic7850 SCSI adapter", 571 ahc_aic785X_setup 572 }, 573 { 574 ID_AIC7855 & ID_DEV_VENDOR_MASK, 575 ID_DEV_VENDOR_MASK, 576 "Adaptec aic7855 SCSI adapter", 577 ahc_aic785X_setup 578 }, 579 { 580 ID_AIC7859 & ID_DEV_VENDOR_MASK, 581 ID_DEV_VENDOR_MASK, 582 "Adaptec aic7859 SCSI adapter", 583 ahc_aic7860_setup 584 }, 585 { 586 ID_AIC7860 & ID_DEV_VENDOR_MASK, 587 ID_DEV_VENDOR_MASK, 588 "Adaptec aic7860 Ultra SCSI adapter", 589 ahc_aic7860_setup 590 }, 591 { 592 ID_AIC7870 & ID_DEV_VENDOR_MASK, 593 ID_DEV_VENDOR_MASK, 594 "Adaptec aic7870 SCSI adapter", 595 ahc_aic7870_setup 596 }, 597 { 598 ID_AIC7880 & ID_DEV_VENDOR_MASK, 599 ID_DEV_VENDOR_MASK, 600 "Adaptec aic7880 Ultra SCSI adapter", 601 ahc_aic7880_setup 602 }, 603 { 604 ID_AIC7890 & ID_9005_GENERIC_MASK, 605 ID_9005_GENERIC_MASK, 606 "Adaptec aic7890/91 Ultra2 SCSI adapter", 607 ahc_aic7890_setup 608 }, 609 { 610 ID_AIC7892 & ID_9005_GENERIC_MASK, 611 ID_9005_GENERIC_MASK, 612 "Adaptec aic7892 Ultra160 SCSI adapter", 613 ahc_aic7892_setup 614 }, 615 { 616 ID_AIC7895 & ID_DEV_VENDOR_MASK, 617 ID_DEV_VENDOR_MASK, 618 "Adaptec aic7895 Ultra SCSI adapter", 619 ahc_aic7895_setup 620 }, 621 { 622 ID_AIC7896 & ID_9005_GENERIC_MASK, 623 ID_9005_GENERIC_MASK, 624 "Adaptec aic7896/97 Ultra2 SCSI adapter", 625 ahc_aic7896_setup 626 }, 627 { 628 ID_AIC7899 & ID_9005_GENERIC_MASK, 629 ID_9005_GENERIC_MASK, 630 "Adaptec aic7899 Ultra160 SCSI adapter", 631 ahc_aic7899_setup 632 }, 633 { 634 ID_AIC7810 & ID_DEV_VENDOR_MASK, 635 ID_DEV_VENDOR_MASK, 636 "Adaptec aic7810 RAID memory controller", 637 ahc_raid_setup 638 }, 639 { 640 ID_AIC7815 & ID_DEV_VENDOR_MASK, 641 ID_DEV_VENDOR_MASK, 642 "Adaptec aic7815 RAID memory controller", 643 ahc_raid_setup 644 } 645 }; 646 647 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table); 648 649 #define AHC_394X_SLOT_CHANNEL_A 4 650 #define AHC_394X_SLOT_CHANNEL_B 5 651 652 #define AHC_398X_SLOT_CHANNEL_A 4 653 #define AHC_398X_SLOT_CHANNEL_B 8 654 #define AHC_398X_SLOT_CHANNEL_C 12 655 656 #define AHC_494X_SLOT_CHANNEL_A 4 657 #define AHC_494X_SLOT_CHANNEL_B 5 658 #define AHC_494X_SLOT_CHANNEL_C 6 659 #define AHC_494X_SLOT_CHANNEL_D 7 660 661 #define DEVCONFIG 0x40 662 #define PCIERRGENDIS 0x80000000ul 663 #define SCBSIZE32 0x00010000ul /* aic789X only */ 664 #define REXTVALID 0x00001000ul /* ultra cards only */ 665 #define MPORTMODE 0x00000400ul /* aic7870+ only */ 666 #define RAMPSM 0x00000200ul /* aic7870+ only */ 667 #define VOLSENSE 0x00000100ul 668 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ 669 #define SCBRAMSEL 0x00000080ul 670 #define MRDCEN 0x00000040ul 671 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 672 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 673 #define BERREN 0x00000008ul 674 #define DACEN 0x00000004ul 675 #define STPWLEVEL 0x00000002ul 676 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 677 678 #define CSIZE_LATTIME 0x0c 679 #define CACHESIZE 0x0000003ful /* only 5 bits */ 680 #define LATTIME 0x0000ff00ul 681 682 /* PCI STATUS definitions */ 683 #define DPE 0x80 684 #define SSE 0x40 685 #define RMA 0x20 686 #define RTA 0x10 687 #define STA 0x08 688 #define DPR 0x01 689 690 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device, 691 uint16_t subvendor, uint16_t subdevice); 692 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 693 static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 694 int pcheck, int fast, int large); 695 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 696 697 int ahc_pci_probe __P((struct device *, struct cfdata *, void *)); 698 void ahc_pci_attach __P((struct device *, struct device *, void *)); 699 700 701 CFATTACH_DECL(ahc_pci, sizeof(struct ahc_softc), 702 ahc_pci_probe, ahc_pci_attach, NULL, NULL); 703 704 const struct ahc_pci_identity * 705 ahc_find_pci_device(id, subid, func) 706 pcireg_t id, subid; 707 u_int func; 708 { 709 u_int64_t full_id; 710 const struct ahc_pci_identity *entry; 711 u_int i; 712 713 full_id = ahc_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 714 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 715 716 /* 717 * If the second function is not hooked up, ignore it. 718 * Unfortunately, not all MB vendors implement the 719 * subdevice ID as per the Adaptec spec, so do our best 720 * to sanity check it prior to accepting the subdevice 721 * ID as valid. 722 */ 723 if (func > 0 724 && ahc_9005_subdevinfo_valid(PCI_VENDOR(id), PCI_PRODUCT(id), 725 PCI_VENDOR(subid), PCI_PRODUCT(subid)) 726 && SUBID_9005_MFUNCENB(PCI_PRODUCT(subid)) == 0) 727 return (NULL); 728 729 for (i = 0; i < ahc_num_pci_devs; i++) { 730 entry = &ahc_pci_ident_table[i]; 731 if (entry->full_id == (full_id & entry->id_mask)) 732 return (entry); 733 } 734 return (NULL); 735 } 736 737 int 738 ahc_pci_probe(parent, match, aux) 739 struct device *parent; 740 struct cfdata *match; 741 void *aux; 742 { 743 struct pci_attach_args *pa = aux; 744 const struct ahc_pci_identity *entry; 745 pcireg_t subid; 746 747 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 748 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); 749 return (entry != NULL && entry->setup != NULL) ? 1 : 0; 750 } 751 752 void 753 ahc_pci_attach(parent, self, aux) 754 struct device *parent, *self; 755 void *aux; 756 { 757 struct pci_attach_args *pa = aux; 758 const struct ahc_pci_identity *entry; 759 struct ahc_softc *ahc = (void *)self; 760 pcireg_t command; 761 u_int our_id = 0; 762 u_int sxfrctl1; 763 u_int scsiseq; 764 u_int sblkctl; 765 uint8_t dscommand0; 766 uint32_t devconfig; 767 int error; 768 pcireg_t subid; 769 int ioh_valid, memh_valid; 770 bus_space_tag_t st, iot; 771 bus_space_handle_t sh, ioh; 772 #ifdef AHC_ALLOW_MEMIO 773 bus_space_tag_t memt; 774 bus_space_handle_t memh; 775 pcireg_t memtype; 776 #endif 777 pci_intr_handle_t ih; 778 const char *intrstr; 779 struct ahc_pci_busdata *bd; 780 781 ahc_set_name(ahc, ahc->sc_dev.dv_xname); 782 ahc->parent_dmat = pa->pa_dmat; 783 784 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 785 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 786 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); 787 if (entry == NULL) 788 return; 789 790 /* Keep information about the PCI bus */ 791 bd = malloc(sizeof (struct ahc_pci_busdata), M_DEVBUF, M_NOWAIT); 792 if (bd == NULL) { 793 printf("%s: unable to allocate bus-specific data\n", ahc_name(ahc)); 794 return; 795 } 796 memset(bd, 0, sizeof(struct ahc_pci_busdata)); 797 798 bd->pc = pa->pa_pc; 799 bd->tag = pa->pa_tag; 800 bd->func = pa->pa_function; 801 bd->dev = pa->pa_device; 802 bd->class = pa->pa_class; 803 804 ahc->bd = bd; 805 806 ahc->description = entry->name; 807 808 error = entry->setup(ahc); 809 if (error != 0) 810 return; 811 812 ioh_valid = memh_valid = 0; 813 814 #ifdef AHC_ALLOW_MEMIO 815 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHC_PCI_MEMADDR); 816 switch (memtype) { 817 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 818 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 819 memh_valid = (pci_mapreg_map(pa, AHC_PCI_MEMADDR, 820 memtype, 0, &memt, &memh, NULL, NULL) == 0); 821 break; 822 default: 823 memh_valid = 0; 824 } 825 #endif 826 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_IOADDR, 827 PCI_MAPREG_TYPE_IO, 0, &iot, 828 &ioh, NULL, NULL) == 0); 829 #if 0 830 printf("%s: mem mapping: memt 0x%x, memh 0x%x, iot 0x%x, ioh 0x%lx\n", 831 ahc_name(ahc), memt, (u_int32_t)memh, (u_int32_t)iot, ioh); 832 #endif 833 834 if (ioh_valid) { 835 st = iot; 836 sh = ioh; 837 #ifdef AHC_ALLOW_MEMIO 838 } else if (memh_valid) { 839 st = memt; 840 sh = memh; 841 #endif 842 } else { 843 printf(": unable to map registers\n"); 844 return; 845 } 846 ahc->tag = st; 847 ahc->bsh = sh; 848 849 ahc->chip |= AHC_PCI; 850 /* 851 * Before we continue probing the card, ensure that 852 * its interrupts are *disabled*. We don't want 853 * a misstep to hang the machine in an interrupt 854 * storm. 855 */ 856 ahc_intr_enable(ahc, FALSE); 857 858 /* 859 * XXX somehow reading this once fails on some sparc64 systems. 860 * This may be a problem in the sparc64 PCI code. Doing it 861 * twice works around it. 862 */ 863 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 864 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 865 866 /* 867 * If we need to support high memory, enable dual 868 * address cycles. This bit must be set to enable 869 * high address bit generation even if we are on a 870 * 64bit bus (PCI64BIT set in devconfig). 871 */ 872 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 873 874 if (1/*bootverbose*/) 875 printf("%s: Enabling 39Bit Addressing\n", 876 ahc_name(ahc)); 877 devconfig |= DACEN; 878 } 879 880 /* Ensure that pci error generation, a test feature, is disabled. */ 881 devconfig |= PCIERRGENDIS; 882 883 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); 884 885 /* Ensure busmastering is enabled */ 886 command |= PCI_COMMAND_MASTER_ENABLE;; 887 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 888 889 /* 890 * Disable PCI parity error reporting. Users typically 891 * do this to work around broken PCI chipsets that get 892 * the parity timing wrong and thus generate lots of spurious 893 * errors. 894 */ 895 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0) 896 command &= ~PCI_COMMAND_PARITY_ENABLE; 897 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 898 899 /* On all PCI adapters, we allow SCB paging */ 900 ahc->flags |= AHC_PAGESCBS; 901 error = ahc_softc_init(ahc); 902 if (error != 0) 903 goto error_out; 904 905 ahc->bus_intr = ahc_pci_intr; 906 907 /* Remember how the card was setup in case there is no SEEPROM */ 908 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 909 ahc_pause(ahc); 910 if ((ahc->features & AHC_ULTRA2) != 0) 911 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 912 else 913 our_id = ahc_inb(ahc, SCSIID) & OID; 914 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 915 scsiseq = ahc_inb(ahc, SCSISEQ); 916 } else { 917 sxfrctl1 = STPWEN; 918 our_id = 7; 919 scsiseq = 0; 920 } 921 922 error = ahc_reset(ahc); 923 if (error != 0) 924 goto error_out; 925 926 if ((ahc->features & AHC_DT) != 0) { 927 u_int sfunct; 928 929 /* Perform ALT-Mode Setup */ 930 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 931 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 932 ahc_outb(ahc, OPTIONMODE, 933 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 934 ahc_outb(ahc, SFUNCT, sfunct); 935 936 /* Normal mode setup */ 937 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 938 |TARGCRCENDEN); 939 } 940 941 if (pci_intr_map(pa, &ih)) { 942 printf("%s: couldn't map interrupt\n", ahc_name(ahc)); 943 ahc_free(ahc); 944 return; 945 } 946 intrstr = pci_intr_string(pa->pa_pc, ih); 947 ahc->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahc_intr, ahc); 948 if (ahc->ih == NULL) { 949 printf("%s: couldn't establish interrupt", 950 ahc->sc_dev.dv_xname); 951 if (intrstr != NULL) 952 printf(" at %s", intrstr); 953 printf("\n"); 954 ahc_free(ahc); 955 return; 956 } 957 printf("\n"); 958 if (intrstr != NULL) 959 printf("%s: interrupting at %s\n", ahc_name(ahc), intrstr); 960 961 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 962 dscommand0 |= MPARCKEN|CACHETHEN; 963 if ((ahc->features & AHC_ULTRA2) != 0) { 964 965 /* 966 * DPARCKEN doesn't work correctly on 967 * some MBs so don't use it. 968 */ 969 dscommand0 &= ~DPARCKEN; 970 } 971 972 /* 973 * Handle chips that must have cache line 974 * streaming (dis/en)abled. 975 */ 976 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 977 dscommand0 |= CACHETHEN; 978 979 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 980 dscommand0 &= ~CACHETHEN; 981 982 ahc_outb(ahc, DSCOMMAND0, dscommand0); 983 984 ahc->pci_cachesize = 985 pci_conf_read(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME) & CACHESIZE; 986 ahc->pci_cachesize *= 4; 987 988 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 989 && ahc->pci_cachesize == 4) { 990 pci_conf_write(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME, 0); 991 ahc->pci_cachesize = 0; 992 } 993 994 /* 995 * We cannot perform ULTRA speeds without the presence 996 * of the external precision resistor. 997 */ 998 if ((ahc->features & AHC_ULTRA) != 0) { 999 uint32_t devconfig; 1000 1001 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 1002 if ((devconfig & REXTVALID) == 0) 1003 ahc->features &= ~AHC_ULTRA; 1004 } 1005 1006 ahc->seep_config = malloc(sizeof(*ahc->seep_config), 1007 M_DEVBUF, M_NOWAIT); 1008 if (ahc->seep_config == NULL) 1009 goto error_out; 1010 1011 memset(ahc->seep_config, 0, sizeof(*ahc->seep_config)); 1012 1013 /* See if we have a SEEPROM and perform auto-term */ 1014 ahc_check_extport(ahc, &sxfrctl1); 1015 1016 /* 1017 * Take the LED out of diagnostic mode 1018 */ 1019 sblkctl = ahc_inb(ahc, SBLKCTL); 1020 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 1021 1022 if ((ahc->features & AHC_ULTRA2) != 0) { 1023 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 1024 } else { 1025 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 1026 } 1027 1028 if (ahc->flags & AHC_USEDEFAULTS) { 1029 /* 1030 * PCI Adapter default setup 1031 * Should only be used if the adapter does not have 1032 * a SEEPROM. 1033 */ 1034 /* See if someone else set us up already */ 1035 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0 1036 && scsiseq != 0) { 1037 printf("%s: Using left over BIOS settings\n", 1038 ahc_name(ahc)); 1039 ahc->flags &= ~AHC_USEDEFAULTS; 1040 ahc->flags |= AHC_BIOS_ENABLED; 1041 } else { 1042 /* 1043 * Assume only one connector and always turn 1044 * on termination. 1045 */ 1046 our_id = 0x07; 1047 sxfrctl1 = STPWEN; 1048 } 1049 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 1050 1051 ahc->our_id = our_id; 1052 } 1053 1054 /* 1055 * Take a look to see if we have external SRAM. 1056 * We currently do not attempt to use SRAM that is 1057 * shared among multiple controllers. 1058 */ 1059 ahc_probe_ext_scbram(ahc); 1060 1061 /* 1062 * Record our termination setting for the 1063 * generic initialization routine. 1064 */ 1065 if ((sxfrctl1 & STPWEN) != 0) 1066 ahc->flags |= AHC_TERM_ENB_A; 1067 1068 if (ahc_init(ahc)) 1069 goto error_out; 1070 1071 ahc_attach(ahc); 1072 1073 return; 1074 1075 error_out: 1076 ahc_free(ahc); 1077 return; 1078 } 1079 1080 static int 1081 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, 1082 uint16_t subdevice, uint16_t subvendor) 1083 { 1084 int result; 1085 1086 /* Default to invalid. */ 1087 result = 0; 1088 if (vendor == 0x9005 1089 && subvendor == 0x9005 1090 && subdevice != device 1091 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) { 1092 1093 switch (SUBID_9005_TYPE(subdevice)) { 1094 case SUBID_9005_TYPE_MB: 1095 break; 1096 case SUBID_9005_TYPE_CARD: 1097 case SUBID_9005_TYPE_LCCARD: 1098 /* 1099 * Currently only trust Adaptec cards to 1100 * get the sub device info correct. 1101 */ 1102 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA) 1103 result = 1; 1104 break; 1105 case SUBID_9005_TYPE_RAID: 1106 break; 1107 default: 1108 break; 1109 } 1110 } 1111 return (result); 1112 } 1113 1114 1115 /* 1116 * Test for the presense of external sram in an 1117 * "unshared" configuration. 1118 */ 1119 static int 1120 ahc_ext_scbram_present(struct ahc_softc *ahc) 1121 { 1122 u_int chip; 1123 int ramps; 1124 int single_user; 1125 uint32_t devconfig; 1126 1127 chip = ahc->chip & AHC_CHIPID_MASK; 1128 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1129 single_user = (devconfig & MPORTMODE) != 0; 1130 1131 if ((ahc->features & AHC_ULTRA2) != 0) 1132 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 1133 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C) 1134 /* 1135 * External SCBRAM arbitration is flakey 1136 * on these chips. Unfortunately this means 1137 * we don't use the extra SCB ram space on the 1138 * 3940AUW. 1139 */ 1140 ramps = 0; 1141 else if (chip >= AHC_AIC7870) 1142 ramps = (devconfig & RAMPSM) != 0; 1143 else 1144 ramps = 0; 1145 1146 if (ramps && single_user) 1147 return (1); 1148 return (0); 1149 } 1150 1151 /* 1152 * Enable external scbram. 1153 */ 1154 static void 1155 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 1156 int fast, int large) 1157 { 1158 uint32_t devconfig; 1159 1160 if (ahc->features & AHC_MULTI_FUNC) { 1161 /* 1162 * Set the SCB Base addr (highest address bit) 1163 * depending on which channel we are. 1164 */ 1165 ahc_outb(ahc, SCBBADDR, ahc->bd->func); 1166 } 1167 1168 ahc->flags &= ~AHC_LSCBS_ENABLED; 1169 if (large) 1170 ahc->flags |= AHC_LSCBS_ENABLED; 1171 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1172 if ((ahc->features & AHC_ULTRA2) != 0) { 1173 u_int dscommand0; 1174 1175 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1176 if (enable) 1177 dscommand0 &= ~INTSCBRAMSEL; 1178 else 1179 dscommand0 |= INTSCBRAMSEL; 1180 if (large) 1181 dscommand0 &= ~USCBSIZE32; 1182 else 1183 dscommand0 |= USCBSIZE32; 1184 ahc_outb(ahc, DSCOMMAND0, dscommand0); 1185 } else { 1186 if (fast) 1187 devconfig &= ~EXTSCBTIME; 1188 else 1189 devconfig |= EXTSCBTIME; 1190 if (enable) 1191 devconfig &= ~SCBRAMSEL; 1192 else 1193 devconfig |= SCBRAMSEL; 1194 if (large) 1195 devconfig &= ~SCBSIZE32; 1196 else 1197 devconfig |= SCBSIZE32; 1198 } 1199 if (pcheck) 1200 devconfig |= EXTSCBPEN; 1201 else 1202 devconfig &= ~EXTSCBPEN; 1203 1204 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig); 1205 } 1206 1207 /* 1208 * Take a look to see if we have external SRAM. 1209 * We currently do not attempt to use SRAM that is 1210 * shared among multiple controllers. 1211 */ 1212 static void 1213 ahc_probe_ext_scbram(struct ahc_softc *ahc) 1214 { 1215 int num_scbs; 1216 int test_num_scbs; 1217 int enable; 1218 int pcheck; 1219 int fast; 1220 int large; 1221 1222 enable = FALSE; 1223 pcheck = FALSE; 1224 fast = FALSE; 1225 large = FALSE; 1226 num_scbs = 0; 1227 1228 if (ahc_ext_scbram_present(ahc) == 0) 1229 goto done; 1230 1231 /* 1232 * Probe for the best parameters to use. 1233 */ 1234 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 1235 num_scbs = ahc_probe_scbs(ahc); 1236 if (num_scbs == 0) { 1237 /* The SRAM wasn't really present. */ 1238 goto done; 1239 } 1240 enable = TRUE; 1241 1242 /* 1243 * Clear any outstanding parity error 1244 * and ensure that parity error reporting 1245 * is enabled. 1246 */ 1247 ahc_outb(ahc, SEQCTL, 0); 1248 ahc_outb(ahc, CLRINT, CLRPARERR); 1249 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1250 1251 /* Now see if we can do parity */ 1252 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1253 num_scbs = ahc_probe_scbs(ahc); 1254 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1255 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1256 pcheck = TRUE; 1257 1258 /* Clear any resulting parity error */ 1259 ahc_outb(ahc, CLRINT, CLRPARERR); 1260 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1261 1262 /* Now see if we can do fast timing */ 1263 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1264 test_num_scbs = ahc_probe_scbs(ahc); 1265 if (test_num_scbs == num_scbs 1266 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1267 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1268 fast = TRUE; 1269 1270 /* 1271 * See if we can use large SCBs and still maintain 1272 * the same overall count of SCBs. 1273 */ 1274 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1275 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1276 test_num_scbs = ahc_probe_scbs(ahc); 1277 if (test_num_scbs >= num_scbs) { 1278 large = TRUE; 1279 num_scbs = test_num_scbs; 1280 if (num_scbs >= 64) { 1281 /* 1282 * We have enough space to move the 1283 * "busy targets table" into SCB space 1284 * and make it qualify all the way to the 1285 * lun level. 1286 */ 1287 ahc->flags |= AHC_SCB_BTT; 1288 } 1289 } 1290 } 1291 done: 1292 /* 1293 * Disable parity error reporting until we 1294 * can load instruction ram. 1295 */ 1296 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1297 /* Clear any latched parity error */ 1298 ahc_outb(ahc, CLRINT, CLRPARERR); 1299 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1300 if (1/*bootverbose*/ && enable) { 1301 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1302 ahc_name(ahc), fast ? "fast" : "slow", 1303 pcheck ? ", parity checking enabled" : "", 1304 large ? 64 : 32); 1305 } 1306 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1307 } 1308 1309 #if 0 1310 /* 1311 * Perform some simple tests that should catch situations where 1312 * our registers are invalidly mapped. 1313 */ 1314 int 1315 ahc_pci_test_register_access(struct ahc_softc *ahc) 1316 { 1317 int error; 1318 u_int status1; 1319 uint32_t cmd; 1320 uint8_t hcntrl; 1321 1322 error = EIO; 1323 1324 /* 1325 * Enable PCI error interrupt status, but suppress NMIs 1326 * generated by SERR raised due to target aborts. 1327 */ 1328 cmd = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND); 1329 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND, 1330 cmd & ~PCIM_CMD_SERRESPEN); 1331 1332 /* 1333 * First a simple test to see if any 1334 * registers can be read. Reading 1335 * HCNTRL has no side effects and has 1336 * at least one bit that is guaranteed to 1337 * be zero so it is a good register to 1338 * use for this test. 1339 */ 1340 hcntrl = ahc_inb(ahc, HCNTRL); 1341 if (hcntrl == 0xFF) 1342 goto fail; 1343 1344 /* 1345 * Next create a situation where write combining 1346 * or read prefetching could be initiated by the 1347 * CPU or host bridge. Our device does not support 1348 * either, so look for data corruption and/or flagged 1349 * PCI errors. 1350 */ 1351 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE); 1352 while (ahc_is_paused(ahc) == 0) 1353 ; 1354 ahc_outb(ahc, SEQCTL, PERRORDIS); 1355 ahc_outb(ahc, SCBPTR, 0); 1356 ahc_outl(ahc, SCB_BASE, 0x5aa555aa); 1357 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa) 1358 goto fail; 1359 1360 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1361 PCI_COMMAND_STATUS_REG + 1); 1362 if ((status1 & STA) != 0) 1363 goto fail; 1364 1365 error = 0; 1366 1367 fail: 1368 /* Silently clear any latched errors. */ 1369 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG + 1); 1370 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1371 status1, /*bytes*/1); 1372 ahc_outb(ahc, CLRINT, CLRPARERR); 1373 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1374 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 1375 return (error); 1376 } 1377 #endif 1378 1379 void 1380 ahc_pci_intr(struct ahc_softc *ahc) 1381 { 1382 u_int error; 1383 u_int status1; 1384 1385 error = ahc_inb(ahc, ERROR); 1386 if ((error & PCIERRSTAT) == 0) 1387 return; 1388 1389 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG); 1390 1391 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1392 ahc_name(ahc), 1393 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1394 1395 if (status1 & DPE) { 1396 printf("%s: Data Parity Error Detected during address " 1397 "or write data phase\n", ahc_name(ahc)); 1398 } 1399 if (status1 & SSE) { 1400 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1401 } 1402 if (status1 & RMA) { 1403 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1404 } 1405 if (status1 & RTA) { 1406 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1407 } 1408 if (status1 & STA) { 1409 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1410 } 1411 if (status1 & DPR) { 1412 printf("%s: Data Parity Error has been reported via PERR#\n", 1413 ahc_name(ahc)); 1414 } 1415 1416 /* Clear latched errors. */ 1417 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG, status1); 1418 1419 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1420 printf("%s: Latched PCIERR interrupt with " 1421 "no status bits set\n", ahc_name(ahc)); 1422 } else { 1423 ahc_outb(ahc, CLRINT, CLRPARERR); 1424 } 1425 1426 ahc_unpause(ahc); 1427 } 1428 1429 static int 1430 ahc_aic785X_setup(struct ahc_softc *ahc) 1431 { 1432 uint8_t rev; 1433 1434 ahc->channel = 'A'; 1435 ahc->chip = AHC_AIC7850; 1436 ahc->features = AHC_AIC7850_FE; 1437 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1438 rev = PCI_REVISION(ahc->bd->class); 1439 if (rev >= 1) 1440 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1441 return (0); 1442 } 1443 1444 static int 1445 ahc_aic7860_setup(struct ahc_softc *ahc) 1446 { 1447 uint8_t rev; 1448 1449 ahc->channel = 'A'; 1450 ahc->chip = AHC_AIC7860; 1451 ahc->features = AHC_AIC7860_FE; 1452 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1453 rev = PCI_REVISION(ahc->bd->class); 1454 if (rev >= 1) 1455 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1456 return (0); 1457 } 1458 1459 static int 1460 ahc_apa1480_setup(struct ahc_softc *ahc) 1461 { 1462 int error; 1463 1464 error = ahc_aic7860_setup(ahc); 1465 if (error != 0) 1466 return (error); 1467 ahc->features |= AHC_REMOVABLE; 1468 return (0); 1469 } 1470 1471 static int 1472 ahc_aic7870_setup(struct ahc_softc *ahc) 1473 { 1474 1475 ahc->channel = 'A'; 1476 ahc->chip = AHC_AIC7870; 1477 ahc->features = AHC_AIC7870_FE; 1478 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1479 return (0); 1480 } 1481 1482 static int 1483 ahc_aha394X_setup(struct ahc_softc *ahc) 1484 { 1485 int error; 1486 1487 error = ahc_aic7870_setup(ahc); 1488 if (error == 0) 1489 error = ahc_aha394XX_setup(ahc); 1490 return (error); 1491 } 1492 1493 static int 1494 ahc_aha398X_setup(struct ahc_softc *ahc) 1495 { 1496 int error; 1497 1498 error = ahc_aic7870_setup(ahc); 1499 if (error == 0) 1500 error = ahc_aha398XX_setup(ahc); 1501 return (error); 1502 } 1503 1504 static int 1505 ahc_aha494X_setup(struct ahc_softc *ahc) 1506 { 1507 int error; 1508 1509 error = ahc_aic7870_setup(ahc); 1510 if (error == 0) 1511 error = ahc_aha494XX_setup(ahc); 1512 return (error); 1513 } 1514 1515 static int 1516 ahc_aic7880_setup(struct ahc_softc *ahc) 1517 { 1518 uint8_t rev; 1519 1520 ahc->channel = 'A'; 1521 ahc->chip = AHC_AIC7880; 1522 ahc->features = AHC_AIC7880_FE; 1523 ahc->bugs |= AHC_TMODE_WIDEODD_BUG; 1524 rev = PCI_REVISION(ahc->bd->class); 1525 if (rev >= 1) { 1526 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1527 } else { 1528 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1529 } 1530 return (0); 1531 } 1532 1533 static int 1534 ahc_aha2940Pro_setup(struct ahc_softc *ahc) 1535 { 1536 1537 ahc->flags |= AHC_INT50_SPEEDFLEX; 1538 return (ahc_aic7880_setup(ahc)); 1539 } 1540 1541 static int 1542 ahc_aha394XU_setup(struct ahc_softc *ahc) 1543 { 1544 int error; 1545 1546 error = ahc_aic7880_setup(ahc); 1547 if (error == 0) 1548 error = ahc_aha394XX_setup(ahc); 1549 return (error); 1550 } 1551 1552 static int 1553 ahc_aha398XU_setup(struct ahc_softc *ahc) 1554 { 1555 int error; 1556 1557 error = ahc_aic7880_setup(ahc); 1558 if (error == 0) 1559 error = ahc_aha398XX_setup(ahc); 1560 return (error); 1561 } 1562 1563 static int 1564 ahc_aic7890_setup(struct ahc_softc *ahc) 1565 { 1566 uint8_t rev; 1567 1568 ahc->channel = 'A'; 1569 ahc->chip = AHC_AIC7890; 1570 ahc->features = AHC_AIC7890_FE; 1571 ahc->flags |= AHC_NEWEEPROM_FMT; 1572 rev = PCI_REVISION(ahc->bd->class); 1573 if (rev == 0) 1574 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 1575 return (0); 1576 } 1577 1578 static int 1579 ahc_aic7892_setup(struct ahc_softc *ahc) 1580 { 1581 1582 ahc->channel = 'A'; 1583 ahc->chip = AHC_AIC7892; 1584 ahc->features = AHC_AIC7892_FE; 1585 ahc->flags |= AHC_NEWEEPROM_FMT; 1586 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1587 return (0); 1588 } 1589 1590 static int 1591 ahc_aic7895_setup(struct ahc_softc *ahc) 1592 { 1593 uint8_t rev; 1594 1595 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1596 /* 1597 * The 'C' revision of the aic7895 has a few additional features. 1598 */ 1599 rev = PCI_REVISION(ahc->bd->class); 1600 if (rev >= 4) { 1601 ahc->chip = AHC_AIC7895C; 1602 ahc->features = AHC_AIC7895C_FE; 1603 } else { 1604 u_int command; 1605 1606 ahc->chip = AHC_AIC7895; 1607 ahc->features = AHC_AIC7895_FE; 1608 1609 /* 1610 * The BIOS disables the use of MWI transactions 1611 * since it does not have the MWI bug work around 1612 * we have. Disabling MWI reduces performance, so 1613 * turn it on again. 1614 */ 1615 command = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG); 1616 command |= PCI_COMMAND_INVALIDATE_ENABLE; 1617 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG, command); 1618 ahc->bugs |= AHC_PCI_MWI_BUG; 1619 } 1620 /* 1621 * XXX Does CACHETHEN really not work??? What about PCI retry? 1622 * on C level chips. Need to test, but for now, play it safe. 1623 */ 1624 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 1625 | AHC_CACHETHEN_BUG; 1626 1627 #if 0 1628 uint32_t devconfig; 1629 1630 /* 1631 * Cachesize must also be zero due to stray DAC 1632 * problem when sitting behind some bridges. 1633 */ 1634 pci_conf_write(ahc->bd->pc, ahc->bd->tag, CSIZE_LATTIME, 0); 1635 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1636 devconfig |= MRDCEN; 1637 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig); 1638 #endif 1639 ahc->flags |= AHC_NEWEEPROM_FMT; 1640 return (0); 1641 } 1642 1643 static int 1644 ahc_aic7896_setup(struct ahc_softc *ahc) 1645 { 1646 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1647 ahc->chip = AHC_AIC7896; 1648 ahc->features = AHC_AIC7896_FE; 1649 ahc->flags |= AHC_NEWEEPROM_FMT; 1650 ahc->bugs |= AHC_CACHETHEN_DIS_BUG; 1651 return (0); 1652 } 1653 1654 static int 1655 ahc_aic7899_setup(struct ahc_softc *ahc) 1656 { 1657 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1658 ahc->chip = AHC_AIC7899; 1659 ahc->features = AHC_AIC7899_FE; 1660 ahc->flags |= AHC_NEWEEPROM_FMT; 1661 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1662 return (0); 1663 } 1664 1665 static int 1666 ahc_aha29160C_setup(struct ahc_softc *ahc) 1667 { 1668 int error; 1669 1670 error = ahc_aic7899_setup(ahc); 1671 if (error != 0) 1672 return (error); 1673 ahc->features |= AHC_REMOVABLE; 1674 return (0); 1675 } 1676 1677 static int 1678 ahc_raid_setup(struct ahc_softc *ahc) 1679 { 1680 printf("RAID functionality unsupported\n"); 1681 return (ENXIO); 1682 } 1683 1684 static int 1685 ahc_aha394XX_setup(struct ahc_softc *ahc) 1686 { 1687 1688 switch (ahc->bd->dev) { 1689 case AHC_394X_SLOT_CHANNEL_A: 1690 ahc->channel = 'A'; 1691 break; 1692 case AHC_394X_SLOT_CHANNEL_B: 1693 ahc->channel = 'B'; 1694 break; 1695 default: 1696 printf("adapter at unexpected slot %d\n" 1697 "unable to map to a channel\n", 1698 ahc->bd->dev); 1699 ahc->channel = 'A'; 1700 } 1701 return (0); 1702 } 1703 1704 static int 1705 ahc_aha398XX_setup(struct ahc_softc *ahc) 1706 { 1707 1708 switch (ahc->bd->dev) { 1709 case AHC_398X_SLOT_CHANNEL_A: 1710 ahc->channel = 'A'; 1711 break; 1712 case AHC_398X_SLOT_CHANNEL_B: 1713 ahc->channel = 'B'; 1714 break; 1715 case AHC_398X_SLOT_CHANNEL_C: 1716 ahc->channel = 'C'; 1717 break; 1718 default: 1719 printf("adapter at unexpected slot %d\n" 1720 "unable to map to a channel\n", 1721 ahc->bd->dev); 1722 ahc->channel = 'A'; 1723 break; 1724 } 1725 ahc->flags |= AHC_LARGE_SEEPROM; 1726 return (0); 1727 } 1728 1729 static int 1730 ahc_aha494XX_setup(struct ahc_softc *ahc) 1731 { 1732 1733 switch (ahc->bd->dev) { 1734 case AHC_494X_SLOT_CHANNEL_A: 1735 ahc->channel = 'A'; 1736 break; 1737 case AHC_494X_SLOT_CHANNEL_B: 1738 ahc->channel = 'B'; 1739 break; 1740 case AHC_494X_SLOT_CHANNEL_C: 1741 ahc->channel = 'C'; 1742 break; 1743 case AHC_494X_SLOT_CHANNEL_D: 1744 ahc->channel = 'D'; 1745 break; 1746 default: 1747 printf("adapter at unexpected slot %d\n" 1748 "unable to map to a channel\n", 1749 ahc->bd->dev); 1750 ahc->channel = 'A'; 1751 } 1752 ahc->flags |= AHC_LARGE_SEEPROM; 1753 return (0); 1754 } 1755
Indexes created Wed Oct 01 19:09:53 GMT 2025