ahc_pci.c revision 1.46
1 /* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1994-2001 Justin T. Gibbs. 7 * Copyright (c) 2000-2001 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: ahc_pci.c,v 1.46 2004/10/16 22:52:37 christos Exp $ 43 * 44 * //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#57 $ 45 * 46 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.22 2003/01/20 20:44:55 gibbs Exp $ 47 */ 48 /* 49 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: ahc_pci.c,v 1.46 2004/10/16 22:52:37 christos Exp $"); 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/queue.h> 60 #include <sys/device.h> 61 #include <sys/reboot.h> 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 #define AHC_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 70 #define AHC_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 71 72 #include <dev/ic/aic7xxx_osm.h> 73 #include <dev/ic/aic7xxx_inline.h> 74 75 #include <dev/ic/smc93cx6var.h> 76 77 78 static __inline uint64_t 79 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 80 { 81 uint64_t id; 82 83 id = subvendor 84 | (subdevice << 16) 85 | ((uint64_t)vendor << 32) 86 | ((uint64_t)device << 48); 87 88 return (id); 89 } 90 91 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 92 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 93 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 94 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull 95 #define ID_9005_SISL_ID 0x0005900500000000ull 96 #define ID_AIC7850 0x5078900400000000ull 97 #define ID_AHA_2902_04_10_15_20_30C 0x5078900478509004ull 98 #define ID_AIC7855 0x5578900400000000ull 99 #define ID_AIC7859 0x3860900400000000ull 100 #define ID_AHA_2930CU 0x3860900438699004ull 101 #define ID_AIC7860 0x6078900400000000ull 102 #define ID_AIC7860C 0x6078900478609004ull 103 #define ID_AHA_1480A 0x6075900400000000ull 104 #define ID_AHA_2940AU_0 0x6178900400000000ull 105 #define ID_AHA_2940AU_1 0x6178900478619004ull 106 #define ID_AHA_2940AU_CN 0x2178900478219004ull 107 #define ID_AHA_2930C_VAR 0x6038900438689004ull 108 109 #define ID_AIC7870 0x7078900400000000ull 110 #define ID_AHA_2940 0x7178900400000000ull 111 #define ID_AHA_3940 0x7278900400000000ull 112 #define ID_AHA_398X 0x7378900400000000ull 113 #define ID_AHA_2944 0x7478900400000000ull 114 #define ID_AHA_3944 0x7578900400000000ull 115 #define ID_AHA_4944 0x7678900400000000ull 116 117 #define ID_AIC7880 0x8078900400000000ull 118 #define ID_AIC7880_B 0x8078900478809004ull 119 #define ID_AHA_2940U 0x8178900400000000ull 120 #define ID_AHA_3940U 0x8278900400000000ull 121 #define ID_AHA_2944U 0x8478900400000000ull 122 #define ID_AHA_3944U 0x8578900400000000ull 123 #define ID_AHA_398XU 0x8378900400000000ull 124 #define ID_AHA_4944U 0x8678900400000000ull 125 #define ID_AHA_2940UB 0x8178900478819004ull 126 #define ID_AHA_2930U 0x8878900478889004ull 127 #define ID_AHA_2940U_PRO 0x8778900478879004ull 128 #define ID_AHA_2940U_CN 0x0078900478009004ull 129 130 #define ID_AIC7895 0x7895900478959004ull 131 #define ID_AIC7895_ARO 0x7890900478939004ull 132 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull 133 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 134 #define ID_AHA_3940AU 0x7895900478929004ull 135 #define ID_AHA_3944AU 0x7895900478949004ull 136 137 #define ID_AIC7890 0x001F9005000F9005ull 138 #define ID_AIC7890_ARO 0x00139005000F9005ull 139 #define ID_AAA_131U2 0x0013900500039005ull 140 #define ID_AHA_2930U2 0x0011900501819005ull 141 #define ID_AHA_2940U2B 0x00109005A1009005ull 142 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 143 #define ID_AHA_2940U2 0x00109005A1809005ull 144 #define ID_AHA_2950U2B 0x00109005E1009005ull 145 146 #define ID_AIC7892 0x008F9005FFFF9005ull 147 #define ID_AIC7892_ARO 0x00839005FFFF9005ull 148 #define ID_AHA_2915LP 0x0082900502109005ull 149 #define ID_AHA_29160 0x00809005E2A09005ull 150 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 151 #define ID_AHA_29160N 0x0080900562A09005ull 152 #define ID_AHA_29160C 0x0080900562209005ull 153 #define ID_AHA_29160B 0x00809005E2209005ull 154 #define ID_AHA_19160B 0x0081900562A19005ull 155 156 #define ID_AIC7896 0x005F9005FFFF9005ull 157 #define ID_AIC7896_ARO 0x00539005FFFF9005ull 158 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 159 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 160 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 161 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 162 163 #define ID_AIC7899 0x00CF9005FFFF9005ull 164 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull 165 #define ID_AHA_3960D 0x00C09005F6209005ull 166 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 167 168 #define ID_AIC7810 0x1078900400000000ull 169 #define ID_AIC7815 0x7815900400000000ull 170 171 #define DEVID_9005_TYPE(id) ((id) & 0xF) 172 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 173 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ 174 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */ 175 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 176 177 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 178 #define DEVID_9005_MAXRATE_U160 0x0 179 #define DEVID_9005_MAXRATE_ULTRA2 0x1 180 #define DEVID_9005_MAXRATE_ULTRA 0x2 181 #define DEVID_9005_MAXRATE_FAST 0x3 182 183 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) 184 185 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) 186 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ 187 188 #define SUBID_9005_TYPE(id) ((id) & 0xF) 189 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 190 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 191 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 192 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 193 194 #define SUBID_9005_TYPE_KNOWN(id) \ 195 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ 196 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ 197 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ 198 || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) 199 200 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 201 #define SUBID_9005_MAXRATE_ULTRA2 0x0 202 #define SUBID_9005_MAXRATE_ULTRA 0x1 203 #define SUBID_9005_MAXRATE_U160 0x2 204 #define SUBID_9005_MAXRATE_RESERVED 0x3 205 206 #define SUBID_9005_SEEPTYPE(id) \ 207 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 208 ? ((id) & 0xC0) >> 6 \ 209 : ((id) & 0x300) >> 8) 210 #define SUBID_9005_SEEPTYPE_NONE 0x0 211 #define SUBID_9005_SEEPTYPE_1K 0x1 212 #define SUBID_9005_SEEPTYPE_2K_4K 0x2 213 #define SUBID_9005_SEEPTYPE_RESERVED 0x3 214 #define SUBID_9005_AUTOTERM(id) \ 215 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 216 ? (((id) & 0x400) >> 10) == 0 \ 217 : (((id) & 0x40) >> 6) == 0) 218 219 #define SUBID_9005_NUMCHAN(id) \ 220 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 221 ? ((id) & 0x300) >> 8 \ 222 : ((id) & 0xC00) >> 10) 223 224 #define SUBID_9005_LEGACYCONN(id) \ 225 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 226 ? 0 \ 227 : ((id) & 0x80) >> 7) 228 229 #define SUBID_9005_MFUNCENB(id) \ 230 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 231 ? ((id) & 0x800) >> 11 \ 232 : ((id) & 0x1000) >> 12) 233 /* 234 * Informational only. Should use chip register to be 235 * certain, but may be use in identification strings. 236 */ 237 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 238 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 239 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000 240 241 static ahc_device_setup_t ahc_aic785X_setup; 242 static ahc_device_setup_t ahc_aic7860_setup; 243 static ahc_device_setup_t ahc_apa1480_setup; 244 static ahc_device_setup_t ahc_aic7870_setup; 245 static ahc_device_setup_t ahc_aha394X_setup; 246 static ahc_device_setup_t ahc_aha494X_setup; 247 static ahc_device_setup_t ahc_aha398X_setup; 248 static ahc_device_setup_t ahc_aic7880_setup; 249 static ahc_device_setup_t ahc_aha2940Pro_setup; 250 static ahc_device_setup_t ahc_aha394XU_setup; 251 static ahc_device_setup_t ahc_aha398XU_setup; 252 static ahc_device_setup_t ahc_aic7890_setup; 253 static ahc_device_setup_t ahc_aic7892_setup; 254 static ahc_device_setup_t ahc_aic7895_setup; 255 static ahc_device_setup_t ahc_aic7896_setup; 256 static ahc_device_setup_t ahc_aic7899_setup; 257 static ahc_device_setup_t ahc_aha29160C_setup; 258 static ahc_device_setup_t ahc_raid_setup; 259 static ahc_device_setup_t ahc_aha394XX_setup; 260 static ahc_device_setup_t ahc_aha494XX_setup; 261 static ahc_device_setup_t ahc_aha398XX_setup; 262 263 struct ahc_pci_identity ahc_pci_ident_table [] = 264 { 265 /* aic7850 based controllers */ 266 { 267 ID_AHA_2902_04_10_15_20_30C, 268 ID_ALL_MASK, 269 "Adaptec 2902/04/10/15/20/30C SCSI adapter", 270 ahc_aic785X_setup 271 }, 272 /* aic7860 based controllers */ 273 { 274 ID_AHA_2930CU, 275 ID_ALL_MASK, 276 "Adaptec 2930CU SCSI adapter", 277 ahc_aic7860_setup 278 }, 279 { 280 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 281 ID_DEV_VENDOR_MASK, 282 "Adaptec 1480A Ultra SCSI adapter", 283 ahc_apa1480_setup 284 }, 285 { 286 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 287 ID_DEV_VENDOR_MASK, 288 "Adaptec 2940A Ultra SCSI adapter", 289 ahc_aic7860_setup 290 }, 291 { 292 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 293 ID_DEV_VENDOR_MASK, 294 "Adaptec 2940A/CN Ultra SCSI adapter", 295 ahc_aic7860_setup 296 }, 297 { 298 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 299 ID_DEV_VENDOR_MASK, 300 "Adaptec 2930C Ultra SCSI adapter (VAR)", 301 ahc_aic7860_setup 302 }, 303 /* aic7870 based controllers */ 304 { 305 ID_AHA_2940, 306 ID_ALL_MASK, 307 "Adaptec 2940 SCSI adapter", 308 ahc_aic7870_setup 309 }, 310 { 311 ID_AHA_3940, 312 ID_ALL_MASK, 313 "Adaptec 3940 SCSI adapter", 314 ahc_aha394X_setup 315 }, 316 { 317 ID_AHA_398X, 318 ID_ALL_MASK, 319 "Adaptec 398X SCSI RAID adapter", 320 ahc_aha398X_setup 321 }, 322 { 323 ID_AHA_2944, 324 ID_ALL_MASK, 325 "Adaptec 2944 SCSI adapter", 326 ahc_aic7870_setup 327 }, 328 { 329 ID_AHA_3944, 330 ID_ALL_MASK, 331 "Adaptec 3944 SCSI adapter", 332 ahc_aha394X_setup 333 }, 334 { 335 ID_AHA_4944, 336 ID_ALL_MASK, 337 "Adaptec 4944 SCSI adapter", 338 ahc_aha494X_setup 339 }, 340 /* aic7880 based controllers */ 341 { 342 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 343 ID_DEV_VENDOR_MASK, 344 "Adaptec 2940 Ultra SCSI adapter", 345 ahc_aic7880_setup 346 }, 347 { 348 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 349 ID_DEV_VENDOR_MASK, 350 "Adaptec 3940 Ultra SCSI adapter", 351 ahc_aha394XU_setup 352 }, 353 { 354 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 355 ID_DEV_VENDOR_MASK, 356 "Adaptec 2944 Ultra SCSI adapter", 357 ahc_aic7880_setup 358 }, 359 { 360 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 361 ID_DEV_VENDOR_MASK, 362 "Adaptec 3944 Ultra SCSI adapter", 363 ahc_aha394XU_setup 364 }, 365 { 366 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 367 ID_DEV_VENDOR_MASK, 368 "Adaptec 398X Ultra SCSI RAID adapter", 369 ahc_aha398XU_setup 370 }, 371 { 372 /* 373 * XXX Don't know the slot numbers 374 * so we can't identify channels 375 */ 376 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 377 ID_DEV_VENDOR_MASK, 378 "Adaptec 4944 Ultra SCSI adapter", 379 ahc_aic7880_setup 380 }, 381 { 382 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 383 ID_DEV_VENDOR_MASK, 384 "Adaptec 2930 Ultra SCSI adapter", 385 ahc_aic7880_setup 386 }, 387 { 388 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 389 ID_DEV_VENDOR_MASK, 390 "Adaptec 2940 Pro Ultra SCSI adapter", 391 ahc_aha2940Pro_setup 392 }, 393 { 394 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 395 ID_DEV_VENDOR_MASK, 396 "Adaptec 2940/CN Ultra SCSI adapter", 397 ahc_aic7880_setup 398 }, 399 /* Ignore all SISL (AAC on MB) based controllers. */ 400 { 401 ID_9005_SISL_ID, 402 ID_9005_SISL_MASK, 403 NULL, 404 NULL 405 }, 406 /* aic7890 based controllers */ 407 { 408 ID_AHA_2930U2, 409 ID_ALL_MASK, 410 "Adaptec 2930 Ultra2 SCSI adapter", 411 ahc_aic7890_setup 412 }, 413 { 414 ID_AHA_2940U2B, 415 ID_ALL_MASK, 416 "Adaptec 2940B Ultra2 SCSI adapter", 417 ahc_aic7890_setup 418 }, 419 { 420 ID_AHA_2940U2_OEM, 421 ID_ALL_MASK, 422 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 423 ahc_aic7890_setup 424 }, 425 { 426 ID_AHA_2940U2, 427 ID_ALL_MASK, 428 "Adaptec 2940 Ultra2 SCSI adapter", 429 ahc_aic7890_setup 430 }, 431 { 432 ID_AHA_2950U2B, 433 ID_ALL_MASK, 434 "Adaptec 2950 Ultra2 SCSI adapter", 435 ahc_aic7890_setup 436 }, 437 { 438 ID_AIC7890_ARO, 439 ID_ALL_MASK, 440 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)", 441 ahc_aic7890_setup 442 }, 443 { 444 ID_AAA_131U2, 445 ID_ALL_MASK, 446 "Adaptec AAA-131 Ultra2 RAID adapter", 447 ahc_aic7890_setup 448 }, 449 /* aic7892 based controllers */ 450 { 451 ID_AHA_29160, 452 ID_ALL_MASK, 453 "Adaptec 29160 Ultra160 SCSI adapter", 454 ahc_aic7892_setup 455 }, 456 { 457 ID_AHA_29160_CPQ, 458 ID_ALL_MASK, 459 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 460 ahc_aic7892_setup 461 }, 462 { 463 ID_AHA_29160N, 464 ID_ALL_MASK, 465 "Adaptec 29160N Ultra160 SCSI adapter", 466 ahc_aic7892_setup 467 }, 468 { 469 ID_AHA_29160C, 470 ID_ALL_MASK, 471 "Adaptec 29160C Ultra160 SCSI adapter", 472 ahc_aha29160C_setup 473 }, 474 { 475 ID_AHA_29160B, 476 ID_ALL_MASK, 477 "Adaptec 29160B Ultra160 SCSI adapter", 478 ahc_aic7892_setup 479 }, 480 { 481 ID_AHA_19160B, 482 ID_ALL_MASK, 483 "Adaptec 19160B Ultra160 SCSI adapter", 484 ahc_aic7892_setup 485 }, 486 { 487 ID_AIC7892_ARO, 488 ID_ALL_MASK, 489 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)", 490 ahc_aic7892_setup 491 }, 492 { 493 ID_AHA_2915LP, 494 ID_ALL_MASK, 495 "Adaptec 2915LP Ultra160 SCSI adapter", 496 ahc_aic7892_setup 497 }, 498 /* aic7895 based controllers */ 499 { 500 ID_AHA_2940U_DUAL, 501 ID_ALL_MASK, 502 "Adaptec 2940/DUAL Ultra SCSI adapter", 503 ahc_aic7895_setup 504 }, 505 { 506 ID_AHA_3940AU, 507 ID_ALL_MASK, 508 "Adaptec 3940A Ultra SCSI adapter", 509 ahc_aic7895_setup 510 }, 511 { 512 ID_AHA_3944AU, 513 ID_ALL_MASK, 514 "Adaptec 3944A Ultra SCSI adapter", 515 ahc_aic7895_setup 516 }, 517 { 518 ID_AIC7895_ARO, 519 ID_AIC7895_ARO_MASK, 520 "Adaptec aic7895 Ultra SCSI adapter (ARO)", 521 ahc_aic7895_setup 522 }, 523 /* aic7896/97 based controllers */ 524 { 525 ID_AHA_3950U2B_0, 526 ID_ALL_MASK, 527 "Adaptec 3950B Ultra2 SCSI adapter", 528 ahc_aic7896_setup 529 }, 530 { 531 ID_AHA_3950U2B_1, 532 ID_ALL_MASK, 533 "Adaptec 3950B Ultra2 SCSI adapter", 534 ahc_aic7896_setup 535 }, 536 { 537 ID_AHA_3950U2D_0, 538 ID_ALL_MASK, 539 "Adaptec 3950D Ultra2 SCSI adapter", 540 ahc_aic7896_setup 541 }, 542 { 543 ID_AHA_3950U2D_1, 544 ID_ALL_MASK, 545 "Adaptec 3950D Ultra2 SCSI adapter", 546 ahc_aic7896_setup 547 }, 548 { 549 ID_AIC7896_ARO, 550 ID_ALL_MASK, 551 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)", 552 ahc_aic7896_setup 553 }, 554 /* aic7899 based controllers */ 555 { 556 ID_AHA_3960D, 557 ID_ALL_MASK, 558 "Adaptec 3960D Ultra160 SCSI adapter", 559 ahc_aic7899_setup 560 }, 561 { 562 ID_AHA_3960D_CPQ, 563 ID_ALL_MASK, 564 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 565 ahc_aic7899_setup 566 }, 567 { 568 ID_AIC7899_ARO, 569 ID_ALL_MASK, 570 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)", 571 ahc_aic7899_setup 572 }, 573 /* Generic chip probes for devices we don't know 'exactly' */ 574 { 575 ID_AIC7850 & ID_DEV_VENDOR_MASK, 576 ID_DEV_VENDOR_MASK, 577 "Adaptec aic7850 SCSI adapter", 578 ahc_aic785X_setup 579 }, 580 { 581 ID_AIC7855 & ID_DEV_VENDOR_MASK, 582 ID_DEV_VENDOR_MASK, 583 "Adaptec aic7855 SCSI adapter", 584 ahc_aic785X_setup 585 }, 586 { 587 ID_AIC7859 & ID_DEV_VENDOR_MASK, 588 ID_DEV_VENDOR_MASK, 589 "Adaptec aic7859 SCSI adapter", 590 ahc_aic7860_setup 591 }, 592 { 593 ID_AIC7860 & ID_DEV_VENDOR_MASK, 594 ID_DEV_VENDOR_MASK, 595 "Adaptec aic7860 Ultra SCSI adapter", 596 ahc_aic7860_setup 597 }, 598 { 599 ID_AIC7870 & ID_DEV_VENDOR_MASK, 600 ID_DEV_VENDOR_MASK, 601 "Adaptec aic7870 SCSI adapter", 602 ahc_aic7870_setup 603 }, 604 { 605 ID_AIC7880 & ID_DEV_VENDOR_MASK, 606 ID_DEV_VENDOR_MASK, 607 "Adaptec aic7880 Ultra SCSI adapter", 608 ahc_aic7880_setup 609 }, 610 { 611 ID_AIC7890 & ID_9005_GENERIC_MASK, 612 ID_9005_GENERIC_MASK, 613 "Adaptec aic7890/91 Ultra2 SCSI adapter", 614 ahc_aic7890_setup 615 }, 616 { 617 ID_AIC7892 & ID_9005_GENERIC_MASK, 618 ID_9005_GENERIC_MASK, 619 "Adaptec aic7892 Ultra160 SCSI adapter", 620 ahc_aic7892_setup 621 }, 622 { 623 ID_AIC7895 & ID_DEV_VENDOR_MASK, 624 ID_DEV_VENDOR_MASK, 625 "Adaptec aic7895 Ultra SCSI adapter", 626 ahc_aic7895_setup 627 }, 628 { 629 ID_AIC7896 & ID_9005_GENERIC_MASK, 630 ID_9005_GENERIC_MASK, 631 "Adaptec aic7896/97 Ultra2 SCSI adapter", 632 ahc_aic7896_setup 633 }, 634 { 635 ID_AIC7899 & ID_9005_GENERIC_MASK, 636 ID_9005_GENERIC_MASK, 637 "Adaptec aic7899 Ultra160 SCSI adapter", 638 ahc_aic7899_setup 639 }, 640 { 641 ID_AIC7810 & ID_DEV_VENDOR_MASK, 642 ID_DEV_VENDOR_MASK, 643 "Adaptec aic7810 RAID memory controller", 644 ahc_raid_setup 645 }, 646 { 647 ID_AIC7815 & ID_DEV_VENDOR_MASK, 648 ID_DEV_VENDOR_MASK, 649 "Adaptec aic7815 RAID memory controller", 650 ahc_raid_setup 651 } 652 }; 653 654 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table); 655 656 #define AHC_394X_SLOT_CHANNEL_A 4 657 #define AHC_394X_SLOT_CHANNEL_B 5 658 659 #define AHC_398X_SLOT_CHANNEL_A 4 660 #define AHC_398X_SLOT_CHANNEL_B 8 661 #define AHC_398X_SLOT_CHANNEL_C 12 662 663 #define AHC_494X_SLOT_CHANNEL_A 4 664 #define AHC_494X_SLOT_CHANNEL_B 5 665 #define AHC_494X_SLOT_CHANNEL_C 6 666 #define AHC_494X_SLOT_CHANNEL_D 7 667 668 #define DEVCONFIG 0x40 669 #define PCIERRGENDIS 0x80000000ul 670 #define SCBSIZE32 0x00010000ul /* aic789X only */ 671 #define REXTVALID 0x00001000ul /* ultra cards only */ 672 #define MPORTMODE 0x00000400ul /* aic7870+ only */ 673 #define RAMPSM 0x00000200ul /* aic7870+ only */ 674 #define VOLSENSE 0x00000100ul 675 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ 676 #define SCBRAMSEL 0x00000080ul 677 #define MRDCEN 0x00000040ul 678 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 679 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 680 #define BERREN 0x00000008ul 681 #define DACEN 0x00000004ul 682 #define STPWLEVEL 0x00000002ul 683 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 684 685 #define CSIZE_LATTIME 0x0c 686 #define CACHESIZE 0x0000003ful /* only 5 bits */ 687 #define LATTIME 0x0000ff00ul 688 689 /* PCI STATUS definitions */ 690 #define DPE 0x80 691 #define SSE 0x40 692 #define RMA 0x20 693 #define RTA 0x10 694 #define STA 0x08 695 #define DPR 0x01 696 697 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device, 698 uint16_t subvendor, uint16_t subdevice); 699 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 700 static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 701 int pcheck, int fast, int large); 702 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 703 704 int ahc_pci_probe __P((struct device *, struct cfdata *, void *)); 705 void ahc_pci_attach __P((struct device *, struct device *, void *)); 706 707 708 CFATTACH_DECL(ahc_pci, sizeof(struct ahc_softc), 709 ahc_pci_probe, ahc_pci_attach, NULL, NULL); 710 711 const struct ahc_pci_identity * 712 ahc_find_pci_device(id, subid, func) 713 pcireg_t id, subid; 714 u_int func; 715 { 716 u_int64_t full_id; 717 const struct ahc_pci_identity *entry; 718 u_int i; 719 720 full_id = ahc_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 721 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 722 723 /* 724 * If the second function is not hooked up, ignore it. 725 * Unfortunately, not all MB vendors implement the 726 * subdevice ID as per the Adaptec spec, so do our best 727 * to sanity check it prior to accepting the subdevice 728 * ID as valid. 729 */ 730 if (func > 0 731 && ahc_9005_subdevinfo_valid(PCI_VENDOR(id), PCI_PRODUCT(id), 732 PCI_VENDOR(subid), PCI_PRODUCT(subid)) 733 && SUBID_9005_MFUNCENB(PCI_PRODUCT(subid)) == 0) 734 return (NULL); 735 736 for (i = 0; i < ahc_num_pci_devs; i++) { 737 entry = &ahc_pci_ident_table[i]; 738 if (entry->full_id == (full_id & entry->id_mask)) 739 return (entry); 740 } 741 return (NULL); 742 } 743 744 int 745 ahc_pci_probe(parent, match, aux) 746 struct device *parent; 747 struct cfdata *match; 748 void *aux; 749 { 750 struct pci_attach_args *pa = aux; 751 const struct ahc_pci_identity *entry; 752 pcireg_t subid; 753 754 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 755 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); 756 return (entry != NULL && entry->setup != NULL) ? 1 : 0; 757 } 758 759 void 760 ahc_pci_attach(parent, self, aux) 761 struct device *parent, *self; 762 void *aux; 763 { 764 struct pci_attach_args *pa = aux; 765 const struct ahc_pci_identity *entry; 766 struct ahc_softc *ahc = (void *)self; 767 pcireg_t command; 768 u_int our_id = 0; 769 u_int sxfrctl1; 770 u_int scsiseq; 771 u_int sblkctl; 772 uint8_t dscommand0; 773 uint32_t devconfig; 774 int error; 775 pcireg_t subid; 776 int ioh_valid; 777 bus_space_tag_t st, iot; 778 bus_space_handle_t sh, ioh; 779 #ifdef AHC_ALLOW_MEMIO 780 int memh_valid; 781 bus_space_tag_t memt; 782 bus_space_handle_t memh; 783 pcireg_t memtype; 784 #endif 785 pci_intr_handle_t ih; 786 const char *intrstr; 787 struct ahc_pci_busdata *bd; 788 789 ahc_set_name(ahc, ahc->sc_dev.dv_xname); 790 ahc->parent_dmat = pa->pa_dmat; 791 792 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 793 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 794 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); 795 if (entry == NULL) 796 return; 797 printf(": %s\n", entry->name); 798 799 /* Keep information about the PCI bus */ 800 bd = malloc(sizeof (struct ahc_pci_busdata), M_DEVBUF, M_NOWAIT); 801 if (bd == NULL) { 802 printf("%s: unable to allocate bus-specific data\n", 803 ahc_name(ahc)); 804 return; 805 } 806 memset(bd, 0, sizeof(struct ahc_pci_busdata)); 807 808 bd->pc = pa->pa_pc; 809 bd->tag = pa->pa_tag; 810 bd->func = pa->pa_function; 811 bd->dev = pa->pa_device; 812 bd->class = pa->pa_class; 813 814 ahc->bd = bd; 815 816 ahc->description = entry->name; 817 818 error = entry->setup(ahc); 819 if (error != 0) 820 return; 821 822 ioh_valid = 0; 823 824 #ifdef AHC_ALLOW_MEMIO 825 memh_valid = 0; 826 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHC_PCI_MEMADDR); 827 switch (memtype) { 828 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 829 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 830 memh_valid = (pci_mapreg_map(pa, AHC_PCI_MEMADDR, 831 memtype, 0, &memt, &memh, NULL, NULL) == 0); 832 break; 833 default: 834 memh_valid = 0; 835 } 836 #endif 837 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_IOADDR, 838 PCI_MAPREG_TYPE_IO, 0, &iot, 839 &ioh, NULL, NULL) == 0); 840 #if 0 841 printf("%s: bus info: memt 0x%lx, memh 0x%lx, iot 0x%lx, ioh 0x%lx\n", 842 ahc_name(ahc), (u_long)memt, (u_long)memh, (u_long)iot, 843 (u_long)ioh); 844 #endif 845 846 if (ioh_valid) { 847 st = iot; 848 sh = ioh; 849 #ifdef AHC_ALLOW_MEMIO 850 } else if (memh_valid) { 851 st = memt; 852 sh = memh; 853 #endif 854 } else { 855 printf(": unable to map registers\n"); 856 return; 857 } 858 ahc->tag = st; 859 ahc->bsh = sh; 860 861 ahc->chip |= AHC_PCI; 862 /* 863 * Before we continue probing the card, ensure that 864 * its interrupts are *disabled*. We don't want 865 * a misstep to hang the machine in an interrupt 866 * storm. 867 */ 868 ahc_intr_enable(ahc, FALSE); 869 870 /* 871 * XXX somehow reading this once fails on some sparc64 systems. 872 * This may be a problem in the sparc64 PCI code. Doing it 873 * twice works around it. 874 */ 875 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 876 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 877 878 /* 879 * If we need to support high memory, enable dual 880 * address cycles. This bit must be set to enable 881 * high address bit generation even if we are on a 882 * 64bit bus (PCI64BIT set in devconfig). 883 */ 884 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 885 886 if (1/*bootverbose*/) 887 printf("%s: Enabling 39Bit Addressing\n", 888 ahc_name(ahc)); 889 devconfig |= DACEN; 890 } 891 892 /* Ensure that pci error generation, a test feature, is disabled. */ 893 devconfig |= PCIERRGENDIS; 894 895 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); 896 897 /* Ensure busmastering is enabled */ 898 command |= PCI_COMMAND_MASTER_ENABLE;; 899 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 900 901 /* 902 * Disable PCI parity error reporting. Users typically 903 * do this to work around broken PCI chipsets that get 904 * the parity timing wrong and thus generate lots of spurious 905 * errors. 906 */ 907 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0) 908 command &= ~PCI_COMMAND_PARITY_ENABLE; 909 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 910 911 /* On all PCI adapters, we allow SCB paging */ 912 ahc->flags |= AHC_PAGESCBS; 913 error = ahc_softc_init(ahc); 914 if (error != 0) 915 goto error_out; 916 917 ahc->bus_intr = ahc_pci_intr; 918 919 /* Remember how the card was setup in case there is no SEEPROM */ 920 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 921 ahc_pause(ahc); 922 if ((ahc->features & AHC_ULTRA2) != 0) 923 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 924 else 925 our_id = ahc_inb(ahc, SCSIID) & OID; 926 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 927 scsiseq = ahc_inb(ahc, SCSISEQ); 928 } else { 929 sxfrctl1 = STPWEN; 930 our_id = 7; 931 scsiseq = 0; 932 } 933 934 error = ahc_reset(ahc); 935 if (error != 0) 936 goto error_out; 937 938 if ((ahc->features & AHC_DT) != 0) { 939 u_int sfunct; 940 941 /* Perform ALT-Mode Setup */ 942 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 943 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 944 ahc_outb(ahc, OPTIONMODE, 945 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 946 ahc_outb(ahc, SFUNCT, sfunct); 947 948 /* Normal mode setup */ 949 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 950 |TARGCRCENDEN); 951 } 952 953 if (pci_intr_map(pa, &ih)) { 954 printf("%s: couldn't map interrupt\n", ahc_name(ahc)); 955 ahc_free(ahc); 956 return; 957 } 958 intrstr = pci_intr_string(pa->pa_pc, ih); 959 ahc->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahc_intr, ahc); 960 if (ahc->ih == NULL) { 961 printf("%s: couldn't establish interrupt", 962 ahc->sc_dev.dv_xname); 963 if (intrstr != NULL) 964 printf(" at %s", intrstr); 965 printf("\n"); 966 ahc_free(ahc); 967 return; 968 } 969 if (intrstr != NULL) 970 printf("%s: interrupting at %s\n", ahc_name(ahc), intrstr); 971 972 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 973 dscommand0 |= MPARCKEN|CACHETHEN; 974 if ((ahc->features & AHC_ULTRA2) != 0) { 975 976 /* 977 * DPARCKEN doesn't work correctly on 978 * some MBs so don't use it. 979 */ 980 dscommand0 &= ~DPARCKEN; 981 } 982 983 /* 984 * Handle chips that must have cache line 985 * streaming (dis/en)abled. 986 */ 987 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 988 dscommand0 |= CACHETHEN; 989 990 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 991 dscommand0 &= ~CACHETHEN; 992 993 ahc_outb(ahc, DSCOMMAND0, dscommand0); 994 995 ahc->pci_cachesize = 996 pci_conf_read(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME) & CACHESIZE; 997 ahc->pci_cachesize *= 4; 998 999 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 1000 && ahc->pci_cachesize == 4) { 1001 pci_conf_write(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME, 0); 1002 ahc->pci_cachesize = 0; 1003 } 1004 1005 /* 1006 * We cannot perform ULTRA speeds without the presence 1007 * of the external precision resistor. 1008 */ 1009 if ((ahc->features & AHC_ULTRA) != 0) { 1010 uint32_t devconfig; 1011 1012 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 1013 if ((devconfig & REXTVALID) == 0) 1014 ahc->features &= ~AHC_ULTRA; 1015 } 1016 1017 ahc->seep_config = malloc(sizeof(*ahc->seep_config), 1018 M_DEVBUF, M_NOWAIT); 1019 if (ahc->seep_config == NULL) 1020 goto error_out; 1021 1022 memset(ahc->seep_config, 0, sizeof(*ahc->seep_config)); 1023 1024 /* See if we have a SEEPROM and perform auto-term */ 1025 ahc_check_extport(ahc, &sxfrctl1); 1026 1027 /* 1028 * Take the LED out of diagnostic mode 1029 */ 1030 sblkctl = ahc_inb(ahc, SBLKCTL); 1031 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 1032 1033 if ((ahc->features & AHC_ULTRA2) != 0) { 1034 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 1035 } else { 1036 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 1037 } 1038 1039 if (ahc->flags & AHC_USEDEFAULTS) { 1040 /* 1041 * PCI Adapter default setup 1042 * Should only be used if the adapter does not have 1043 * a SEEPROM. 1044 */ 1045 /* See if someone else set us up already */ 1046 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0 1047 && scsiseq != 0) { 1048 printf("%s: Using left over BIOS settings\n", 1049 ahc_name(ahc)); 1050 ahc->flags &= ~AHC_USEDEFAULTS; 1051 ahc->flags |= AHC_BIOS_ENABLED; 1052 } else { 1053 /* 1054 * Assume only one connector and always turn 1055 * on termination. 1056 */ 1057 our_id = 0x07; 1058 sxfrctl1 = STPWEN; 1059 } 1060 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 1061 1062 ahc->our_id = our_id; 1063 } 1064 1065 /* 1066 * Take a look to see if we have external SRAM. 1067 * We currently do not attempt to use SRAM that is 1068 * shared among multiple controllers. 1069 */ 1070 ahc_probe_ext_scbram(ahc); 1071 1072 /* 1073 * Record our termination setting for the 1074 * generic initialization routine. 1075 */ 1076 if ((sxfrctl1 & STPWEN) != 0) 1077 ahc->flags |= AHC_TERM_ENB_A; 1078 1079 if (ahc_init(ahc)) 1080 goto error_out; 1081 1082 ahc_attach(ahc); 1083 1084 return; 1085 1086 error_out: 1087 ahc_free(ahc); 1088 return; 1089 } 1090 1091 static int 1092 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, 1093 uint16_t subdevice, uint16_t subvendor) 1094 { 1095 int result; 1096 1097 /* Default to invalid. */ 1098 result = 0; 1099 if (vendor == 0x9005 1100 && subvendor == 0x9005 1101 && subdevice != device 1102 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) { 1103 1104 switch (SUBID_9005_TYPE(subdevice)) { 1105 case SUBID_9005_TYPE_MB: 1106 break; 1107 case SUBID_9005_TYPE_CARD: 1108 case SUBID_9005_TYPE_LCCARD: 1109 /* 1110 * Currently only trust Adaptec cards to 1111 * get the sub device info correct. 1112 */ 1113 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA) 1114 result = 1; 1115 break; 1116 case SUBID_9005_TYPE_RAID: 1117 break; 1118 default: 1119 break; 1120 } 1121 } 1122 return (result); 1123 } 1124 1125 1126 /* 1127 * Test for the presense of external sram in an 1128 * "unshared" configuration. 1129 */ 1130 static int 1131 ahc_ext_scbram_present(struct ahc_softc *ahc) 1132 { 1133 u_int chip; 1134 int ramps; 1135 int single_user; 1136 uint32_t devconfig; 1137 1138 chip = ahc->chip & AHC_CHIPID_MASK; 1139 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1140 single_user = (devconfig & MPORTMODE) != 0; 1141 1142 if ((ahc->features & AHC_ULTRA2) != 0) 1143 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 1144 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C) 1145 /* 1146 * External SCBRAM arbitration is flakey 1147 * on these chips. Unfortunately this means 1148 * we don't use the extra SCB ram space on the 1149 * 3940AUW. 1150 */ 1151 ramps = 0; 1152 else if (chip >= AHC_AIC7870) 1153 ramps = (devconfig & RAMPSM) != 0; 1154 else 1155 ramps = 0; 1156 1157 if (ramps && single_user) 1158 return (1); 1159 return (0); 1160 } 1161 1162 /* 1163 * Enable external scbram. 1164 */ 1165 static void 1166 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 1167 int fast, int large) 1168 { 1169 uint32_t devconfig; 1170 1171 if (ahc->features & AHC_MULTI_FUNC) { 1172 /* 1173 * Set the SCB Base addr (highest address bit) 1174 * depending on which channel we are. 1175 */ 1176 ahc_outb(ahc, SCBBADDR, ahc->bd->func); 1177 } 1178 1179 ahc->flags &= ~AHC_LSCBS_ENABLED; 1180 if (large) 1181 ahc->flags |= AHC_LSCBS_ENABLED; 1182 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1183 if ((ahc->features & AHC_ULTRA2) != 0) { 1184 u_int dscommand0; 1185 1186 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1187 if (enable) 1188 dscommand0 &= ~INTSCBRAMSEL; 1189 else 1190 dscommand0 |= INTSCBRAMSEL; 1191 if (large) 1192 dscommand0 &= ~USCBSIZE32; 1193 else 1194 dscommand0 |= USCBSIZE32; 1195 ahc_outb(ahc, DSCOMMAND0, dscommand0); 1196 } else { 1197 if (fast) 1198 devconfig &= ~EXTSCBTIME; 1199 else 1200 devconfig |= EXTSCBTIME; 1201 if (enable) 1202 devconfig &= ~SCBRAMSEL; 1203 else 1204 devconfig |= SCBRAMSEL; 1205 if (large) 1206 devconfig &= ~SCBSIZE32; 1207 else 1208 devconfig |= SCBSIZE32; 1209 } 1210 if (pcheck) 1211 devconfig |= EXTSCBPEN; 1212 else 1213 devconfig &= ~EXTSCBPEN; 1214 1215 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig); 1216 } 1217 1218 /* 1219 * Take a look to see if we have external SRAM. 1220 * We currently do not attempt to use SRAM that is 1221 * shared among multiple controllers. 1222 */ 1223 static void 1224 ahc_probe_ext_scbram(struct ahc_softc *ahc) 1225 { 1226 int num_scbs; 1227 int test_num_scbs; 1228 int enable; 1229 int pcheck; 1230 int fast; 1231 int large; 1232 1233 enable = FALSE; 1234 pcheck = FALSE; 1235 fast = FALSE; 1236 large = FALSE; 1237 num_scbs = 0; 1238 1239 if (ahc_ext_scbram_present(ahc) == 0) 1240 goto done; 1241 1242 /* 1243 * Probe for the best parameters to use. 1244 */ 1245 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 1246 num_scbs = ahc_probe_scbs(ahc); 1247 if (num_scbs == 0) { 1248 /* The SRAM wasn't really present. */ 1249 goto done; 1250 } 1251 enable = TRUE; 1252 1253 /* 1254 * Clear any outstanding parity error 1255 * and ensure that parity error reporting 1256 * is enabled. 1257 */ 1258 ahc_outb(ahc, SEQCTL, 0); 1259 ahc_outb(ahc, CLRINT, CLRPARERR); 1260 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1261 1262 /* Now see if we can do parity */ 1263 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1264 num_scbs = ahc_probe_scbs(ahc); 1265 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1266 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1267 pcheck = TRUE; 1268 1269 /* Clear any resulting parity error */ 1270 ahc_outb(ahc, CLRINT, CLRPARERR); 1271 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1272 1273 /* Now see if we can do fast timing */ 1274 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1275 test_num_scbs = ahc_probe_scbs(ahc); 1276 if (test_num_scbs == num_scbs 1277 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1278 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1279 fast = TRUE; 1280 1281 /* 1282 * See if we can use large SCBs and still maintain 1283 * the same overall count of SCBs. 1284 */ 1285 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1286 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1287 test_num_scbs = ahc_probe_scbs(ahc); 1288 if (test_num_scbs >= num_scbs) { 1289 large = TRUE; 1290 num_scbs = test_num_scbs; 1291 if (num_scbs >= 64) { 1292 /* 1293 * We have enough space to move the 1294 * "busy targets table" into SCB space 1295 * and make it qualify all the way to the 1296 * lun level. 1297 */ 1298 ahc->flags |= AHC_SCB_BTT; 1299 } 1300 } 1301 } 1302 done: 1303 /* 1304 * Disable parity error reporting until we 1305 * can load instruction ram. 1306 */ 1307 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1308 /* Clear any latched parity error */ 1309 ahc_outb(ahc, CLRINT, CLRPARERR); 1310 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1311 if (1/*bootverbose*/ && enable) { 1312 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1313 ahc_name(ahc), fast ? "fast" : "slow", 1314 pcheck ? ", parity checking enabled" : "", 1315 large ? 64 : 32); 1316 } 1317 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1318 } 1319 1320 #if 0 1321 /* 1322 * Perform some simple tests that should catch situations where 1323 * our registers are invalidly mapped. 1324 */ 1325 int 1326 ahc_pci_test_register_access(struct ahc_softc *ahc) 1327 { 1328 int error; 1329 u_int status1; 1330 uint32_t cmd; 1331 uint8_t hcntrl; 1332 1333 error = EIO; 1334 1335 /* 1336 * Enable PCI error interrupt status, but suppress NMIs 1337 * generated by SERR raised due to target aborts. 1338 */ 1339 cmd = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND); 1340 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND, 1341 cmd & ~PCIM_CMD_SERRESPEN); 1342 1343 /* 1344 * First a simple test to see if any 1345 * registers can be read. Reading 1346 * HCNTRL has no side effects and has 1347 * at least one bit that is guaranteed to 1348 * be zero so it is a good register to 1349 * use for this test. 1350 */ 1351 hcntrl = ahc_inb(ahc, HCNTRL); 1352 if (hcntrl == 0xFF) 1353 goto fail; 1354 1355 /* 1356 * Next create a situation where write combining 1357 * or read prefetching could be initiated by the 1358 * CPU or host bridge. Our device does not support 1359 * either, so look for data corruption and/or flagged 1360 * PCI errors. 1361 */ 1362 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE); 1363 while (ahc_is_paused(ahc) == 0) 1364 ; 1365 ahc_outb(ahc, SEQCTL, PERRORDIS); 1366 ahc_outb(ahc, SCBPTR, 0); 1367 ahc_outl(ahc, SCB_BASE, 0x5aa555aa); 1368 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa) 1369 goto fail; 1370 1371 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1372 PCI_COMMAND_STATUS_REG + 1); 1373 if ((status1 & STA) != 0) 1374 goto fail; 1375 1376 error = 0; 1377 1378 fail: 1379 /* Silently clear any latched errors. */ 1380 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1381 PCI_COMMAND_STATUS_REG + 1); 1382 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1383 status1, /*bytes*/1); 1384 ahc_outb(ahc, CLRINT, CLRPARERR); 1385 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1386 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 1387 return (error); 1388 } 1389 #endif 1390 1391 void 1392 ahc_pci_intr(struct ahc_softc *ahc) 1393 { 1394 u_int error; 1395 u_int status1; 1396 1397 error = ahc_inb(ahc, ERROR); 1398 if ((error & PCIERRSTAT) == 0) 1399 return; 1400 1401 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1402 PCI_COMMAND_STATUS_REG); 1403 1404 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1405 ahc_name(ahc), 1406 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1407 1408 if (status1 & DPE) { 1409 printf("%s: Data Parity Error Detected during address " 1410 "or write data phase\n", ahc_name(ahc)); 1411 } 1412 if (status1 & SSE) { 1413 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1414 } 1415 if (status1 & RMA) { 1416 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1417 } 1418 if (status1 & RTA) { 1419 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1420 } 1421 if (status1 & STA) { 1422 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1423 } 1424 if (status1 & DPR) { 1425 printf("%s: Data Parity Error has been reported via PERR#\n", 1426 ahc_name(ahc)); 1427 } 1428 1429 /* Clear latched errors. */ 1430 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG, 1431 status1); 1432 1433 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1434 printf("%s: Latched PCIERR interrupt with " 1435 "no status bits set\n", ahc_name(ahc)); 1436 } else { 1437 ahc_outb(ahc, CLRINT, CLRPARERR); 1438 } 1439 1440 ahc_unpause(ahc); 1441 } 1442 1443 static int 1444 ahc_aic785X_setup(struct ahc_softc *ahc) 1445 { 1446 uint8_t rev; 1447 1448 ahc->channel = 'A'; 1449 ahc->chip = AHC_AIC7850; 1450 ahc->features = AHC_AIC7850_FE; 1451 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1452 rev = PCI_REVISION(ahc->bd->class); 1453 if (rev >= 1) 1454 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1455 return (0); 1456 } 1457 1458 static int 1459 ahc_aic7860_setup(struct ahc_softc *ahc) 1460 { 1461 uint8_t rev; 1462 1463 ahc->channel = 'A'; 1464 ahc->chip = AHC_AIC7860; 1465 ahc->features = AHC_AIC7860_FE; 1466 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1467 rev = PCI_REVISION(ahc->bd->class); 1468 if (rev >= 1) 1469 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1470 return (0); 1471 } 1472 1473 static int 1474 ahc_apa1480_setup(struct ahc_softc *ahc) 1475 { 1476 int error; 1477 1478 error = ahc_aic7860_setup(ahc); 1479 if (error != 0) 1480 return (error); 1481 ahc->features |= AHC_REMOVABLE; 1482 return (0); 1483 } 1484 1485 static int 1486 ahc_aic7870_setup(struct ahc_softc *ahc) 1487 { 1488 1489 ahc->channel = 'A'; 1490 ahc->chip = AHC_AIC7870; 1491 ahc->features = AHC_AIC7870_FE; 1492 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1493 return (0); 1494 } 1495 1496 static int 1497 ahc_aha394X_setup(struct ahc_softc *ahc) 1498 { 1499 int error; 1500 1501 error = ahc_aic7870_setup(ahc); 1502 if (error == 0) 1503 error = ahc_aha394XX_setup(ahc); 1504 return (error); 1505 } 1506 1507 static int 1508 ahc_aha398X_setup(struct ahc_softc *ahc) 1509 { 1510 int error; 1511 1512 error = ahc_aic7870_setup(ahc); 1513 if (error == 0) 1514 error = ahc_aha398XX_setup(ahc); 1515 return (error); 1516 } 1517 1518 static int 1519 ahc_aha494X_setup(struct ahc_softc *ahc) 1520 { 1521 int error; 1522 1523 error = ahc_aic7870_setup(ahc); 1524 if (error == 0) 1525 error = ahc_aha494XX_setup(ahc); 1526 return (error); 1527 } 1528 1529 static int 1530 ahc_aic7880_setup(struct ahc_softc *ahc) 1531 { 1532 uint8_t rev; 1533 1534 ahc->channel = 'A'; 1535 ahc->chip = AHC_AIC7880; 1536 ahc->features = AHC_AIC7880_FE; 1537 ahc->bugs |= AHC_TMODE_WIDEODD_BUG; 1538 rev = PCI_REVISION(ahc->bd->class); 1539 if (rev >= 1) { 1540 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1541 } else { 1542 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1543 } 1544 return (0); 1545 } 1546 1547 static int 1548 ahc_aha2940Pro_setup(struct ahc_softc *ahc) 1549 { 1550 1551 ahc->flags |= AHC_INT50_SPEEDFLEX; 1552 return (ahc_aic7880_setup(ahc)); 1553 } 1554 1555 static int 1556 ahc_aha394XU_setup(struct ahc_softc *ahc) 1557 { 1558 int error; 1559 1560 error = ahc_aic7880_setup(ahc); 1561 if (error == 0) 1562 error = ahc_aha394XX_setup(ahc); 1563 return (error); 1564 } 1565 1566 static int 1567 ahc_aha398XU_setup(struct ahc_softc *ahc) 1568 { 1569 int error; 1570 1571 error = ahc_aic7880_setup(ahc); 1572 if (error == 0) 1573 error = ahc_aha398XX_setup(ahc); 1574 return (error); 1575 } 1576 1577 static int 1578 ahc_aic7890_setup(struct ahc_softc *ahc) 1579 { 1580 uint8_t rev; 1581 1582 ahc->channel = 'A'; 1583 ahc->chip = AHC_AIC7890; 1584 ahc->features = AHC_AIC7890_FE; 1585 ahc->flags |= AHC_NEWEEPROM_FMT; 1586 rev = PCI_REVISION(ahc->bd->class); 1587 if (rev == 0) 1588 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 1589 return (0); 1590 } 1591 1592 static int 1593 ahc_aic7892_setup(struct ahc_softc *ahc) 1594 { 1595 1596 ahc->channel = 'A'; 1597 ahc->chip = AHC_AIC7892; 1598 ahc->features = AHC_AIC7892_FE; 1599 ahc->flags |= AHC_NEWEEPROM_FMT; 1600 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1601 return (0); 1602 } 1603 1604 static int 1605 ahc_aic7895_setup(struct ahc_softc *ahc) 1606 { 1607 uint8_t rev; 1608 1609 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1610 /* 1611 * The 'C' revision of the aic7895 has a few additional features. 1612 */ 1613 rev = PCI_REVISION(ahc->bd->class); 1614 if (rev >= 4) { 1615 ahc->chip = AHC_AIC7895C; 1616 ahc->features = AHC_AIC7895C_FE; 1617 } else { 1618 u_int command; 1619 1620 ahc->chip = AHC_AIC7895; 1621 ahc->features = AHC_AIC7895_FE; 1622 1623 /* 1624 * The BIOS disables the use of MWI transactions 1625 * since it does not have the MWI bug work around 1626 * we have. Disabling MWI reduces performance, so 1627 * turn it on again. 1628 */ 1629 command = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1630 PCI_COMMAND_STATUS_REG); 1631 command |= PCI_COMMAND_INVALIDATE_ENABLE; 1632 pci_conf_write(ahc->bd->pc, ahc->bd->tag, 1633 PCI_COMMAND_STATUS_REG, command); 1634 ahc->bugs |= AHC_PCI_MWI_BUG; 1635 } 1636 /* 1637 * XXX Does CACHETHEN really not work??? What about PCI retry? 1638 * on C level chips. Need to test, but for now, play it safe. 1639 */ 1640 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 1641 | AHC_CACHETHEN_BUG; 1642 1643 #if 0 1644 uint32_t devconfig; 1645 1646 /* 1647 * Cachesize must also be zero due to stray DAC 1648 * problem when sitting behind some bridges. 1649 */ 1650 pci_conf_write(ahc->bd->pc, ahc->bd->tag, CSIZE_LATTIME, 0); 1651 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1652 devconfig |= MRDCEN; 1653 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig); 1654 #endif 1655 ahc->flags |= AHC_NEWEEPROM_FMT; 1656 return (0); 1657 } 1658 1659 static int 1660 ahc_aic7896_setup(struct ahc_softc *ahc) 1661 { 1662 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1663 ahc->chip = AHC_AIC7896; 1664 ahc->features = AHC_AIC7896_FE; 1665 ahc->flags |= AHC_NEWEEPROM_FMT; 1666 ahc->bugs |= AHC_CACHETHEN_DIS_BUG; 1667 return (0); 1668 } 1669 1670 static int 1671 ahc_aic7899_setup(struct ahc_softc *ahc) 1672 { 1673 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1674 ahc->chip = AHC_AIC7899; 1675 ahc->features = AHC_AIC7899_FE; 1676 ahc->flags |= AHC_NEWEEPROM_FMT; 1677 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1678 return (0); 1679 } 1680 1681 static int 1682 ahc_aha29160C_setup(struct ahc_softc *ahc) 1683 { 1684 int error; 1685 1686 error = ahc_aic7899_setup(ahc); 1687 if (error != 0) 1688 return (error); 1689 ahc->features |= AHC_REMOVABLE; 1690 return (0); 1691 } 1692 1693 static int 1694 ahc_raid_setup(struct ahc_softc *ahc) 1695 { 1696 printf("RAID functionality unsupported\n"); 1697 return (ENXIO); 1698 } 1699 1700 static int 1701 ahc_aha394XX_setup(struct ahc_softc *ahc) 1702 { 1703 1704 switch (ahc->bd->dev) { 1705 case AHC_394X_SLOT_CHANNEL_A: 1706 ahc->channel = 'A'; 1707 break; 1708 case AHC_394X_SLOT_CHANNEL_B: 1709 ahc->channel = 'B'; 1710 break; 1711 default: 1712 printf("adapter at unexpected slot %d\n" 1713 "unable to map to a channel\n", 1714 ahc->bd->dev); 1715 ahc->channel = 'A'; 1716 } 1717 return (0); 1718 } 1719 1720 static int 1721 ahc_aha398XX_setup(struct ahc_softc *ahc) 1722 { 1723 1724 switch (ahc->bd->dev) { 1725 case AHC_398X_SLOT_CHANNEL_A: 1726 ahc->channel = 'A'; 1727 break; 1728 case AHC_398X_SLOT_CHANNEL_B: 1729 ahc->channel = 'B'; 1730 break; 1731 case AHC_398X_SLOT_CHANNEL_C: 1732 ahc->channel = 'C'; 1733 break; 1734 default: 1735 printf("adapter at unexpected slot %d\n" 1736 "unable to map to a channel\n", 1737 ahc->bd->dev); 1738 ahc->channel = 'A'; 1739 break; 1740 } 1741 ahc->flags |= AHC_LARGE_SEEPROM; 1742 return (0); 1743 } 1744 1745 static int 1746 ahc_aha494XX_setup(struct ahc_softc *ahc) 1747 { 1748 1749 switch (ahc->bd->dev) { 1750 case AHC_494X_SLOT_CHANNEL_A: 1751 ahc->channel = 'A'; 1752 break; 1753 case AHC_494X_SLOT_CHANNEL_B: 1754 ahc->channel = 'B'; 1755 break; 1756 case AHC_494X_SLOT_CHANNEL_C: 1757 ahc->channel = 'C'; 1758 break; 1759 case AHC_494X_SLOT_CHANNEL_D: 1760 ahc->channel = 'D'; 1761 break; 1762 default: 1763 printf("adapter at unexpected slot %d\n" 1764 "unable to map to a channel\n", 1765 ahc->bd->dev); 1766 ahc->channel = 'A'; 1767 } 1768 ahc->flags |= AHC_LARGE_SEEPROM; 1769 return (0); 1770 } 1771
Indexes created Wed Oct 01 19:09:53 GMT 2025