ahc_pci.c revision 1.56.6.2
1 /* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1994-2001 Justin T. Gibbs. 7 * Copyright (c) 2000-2001 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: ahc_pci.c,v 1.56.6.2 2006/12/10 07:17:41 yamt Exp $ 43 * 44 * //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#57 $ 45 * 46 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.22 2003/01/20 20:44:55 gibbs Exp $ 47 */ 48 /* 49 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: ahc_pci.c,v 1.56.6.2 2006/12/10 07:17:41 yamt Exp $"); 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/queue.h> 60 #include <sys/device.h> 61 #include <sys/reboot.h> 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 70 /* XXXX some i386 on-board chips act weird when memory-mapped */ 71 #ifndef __i386__ 72 #define AHC_ALLOW_MEMIO 73 #endif 74 75 #define AHC_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 76 #define AHC_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 77 78 #include <dev/ic/aic7xxx_osm.h> 79 #include <dev/ic/aic7xxx_inline.h> 80 81 #include <dev/ic/smc93cx6var.h> 82 83 84 static inline uint64_t 85 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 86 { 87 uint64_t id; 88 89 id = subvendor 90 | (subdevice << 16) 91 | ((uint64_t)vendor << 32) 92 | ((uint64_t)device << 48); 93 94 return (id); 95 } 96 97 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 98 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 99 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 100 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull 101 #define ID_9005_SISL_ID 0x0005900500000000ull 102 #define ID_AIC7850 0x5078900400000000ull 103 #define ID_AHA_2902_04_10_15_20_30C 0x5078900478509004ull 104 #define ID_AIC7855 0x5578900400000000ull 105 #define ID_AIC7859 0x3860900400000000ull 106 #define ID_AHA_2930CU 0x3860900438699004ull 107 #define ID_AIC7860 0x6078900400000000ull 108 #define ID_AIC7860C 0x6078900478609004ull 109 #define ID_AHA_1480A 0x6075900400000000ull 110 #define ID_AHA_2940AU_0 0x6178900400000000ull 111 #define ID_AHA_2940AU_1 0x6178900478619004ull 112 #define ID_AHA_2940AU_CN 0x2178900478219004ull 113 #define ID_AHA_2930C_VAR 0x6038900438689004ull 114 115 #define ID_AIC7870 0x7078900400000000ull 116 #define ID_AHA_2940 0x7178900400000000ull 117 #define ID_AHA_3940 0x7278900400000000ull 118 #define ID_AHA_398X 0x7378900400000000ull 119 #define ID_AHA_2944 0x7478900400000000ull 120 #define ID_AHA_3944 0x7578900400000000ull 121 #define ID_AHA_4944 0x7678900400000000ull 122 123 #define ID_AIC7880 0x8078900400000000ull 124 #define ID_AIC7880_B 0x8078900478809004ull 125 #define ID_AHA_2940U 0x8178900400000000ull 126 #define ID_AHA_3940U 0x8278900400000000ull 127 #define ID_AHA_2944U 0x8478900400000000ull 128 #define ID_AHA_3944U 0x8578900400000000ull 129 #define ID_AHA_398XU 0x8378900400000000ull 130 #define ID_AHA_4944U 0x8678900400000000ull 131 #define ID_AHA_2940UB 0x8178900478819004ull 132 #define ID_AHA_2930U 0x8878900478889004ull 133 #define ID_AHA_2940U_PRO 0x8778900478879004ull 134 #define ID_AHA_2940U_CN 0x0078900478009004ull 135 136 #define ID_AIC7895 0x7895900478959004ull 137 #define ID_AIC7895_ARO 0x7890900478939004ull 138 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull 139 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 140 #define ID_AHA_3940AU 0x7895900478929004ull 141 #define ID_AHA_3944AU 0x7895900478949004ull 142 143 #define ID_AIC7890 0x001F9005000F9005ull 144 #define ID_AIC7890_ARO 0x00139005000F9005ull 145 #define ID_AAA_131U2 0x0013900500039005ull 146 #define ID_AHA_2930U2 0x0011900501819005ull 147 #define ID_AHA_2940U2B 0x00109005A1009005ull 148 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 149 #define ID_AHA_2940U2 0x00109005A1809005ull 150 #define ID_AHA_2950U2B 0x00109005E1009005ull 151 152 #define ID_AIC7892 0x008F9005FFFF9005ull 153 #define ID_AIC7892_ARO 0x00839005FFFF9005ull 154 #define ID_AHA_2915LP 0x0082900502109005ull 155 #define ID_AHA_29160 0x00809005E2A09005ull 156 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 157 #define ID_AHA_29160N 0x0080900562A09005ull 158 #define ID_AHA_29160C 0x0080900562209005ull 159 #define ID_AHA_29160B 0x00809005E2209005ull 160 #define ID_AHA_19160B 0x0081900562A19005ull 161 162 #define ID_AIC7896 0x005F9005FFFF9005ull 163 #define ID_AIC7896_ARO 0x00539005FFFF9005ull 164 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 165 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 166 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 167 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 168 169 #define ID_AIC7899 0x00CF9005FFFF9005ull 170 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull 171 #define ID_AHA_3960D 0x00C09005F6209005ull 172 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 173 174 #define ID_AIC7810 0x1078900400000000ull 175 #define ID_AIC7815 0x7815900400000000ull 176 177 #define DEVID_9005_TYPE(id) ((id) & 0xF) 178 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 179 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ 180 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */ 181 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 182 183 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 184 #define DEVID_9005_MAXRATE_U160 0x0 185 #define DEVID_9005_MAXRATE_ULTRA2 0x1 186 #define DEVID_9005_MAXRATE_ULTRA 0x2 187 #define DEVID_9005_MAXRATE_FAST 0x3 188 189 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) 190 191 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) 192 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ 193 194 #define SUBID_9005_TYPE(id) ((id) & 0xF) 195 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 196 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 197 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 198 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 199 200 #define SUBID_9005_TYPE_KNOWN(id) \ 201 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ 202 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ 203 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ 204 || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) 205 206 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 207 #define SUBID_9005_MAXRATE_ULTRA2 0x0 208 #define SUBID_9005_MAXRATE_ULTRA 0x1 209 #define SUBID_9005_MAXRATE_U160 0x2 210 #define SUBID_9005_MAXRATE_RESERVED 0x3 211 212 #define SUBID_9005_SEEPTYPE(id) \ 213 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 214 ? ((id) & 0xC0) >> 6 \ 215 : ((id) & 0x300) >> 8) 216 #define SUBID_9005_SEEPTYPE_NONE 0x0 217 #define SUBID_9005_SEEPTYPE_1K 0x1 218 #define SUBID_9005_SEEPTYPE_2K_4K 0x2 219 #define SUBID_9005_SEEPTYPE_RESERVED 0x3 220 #define SUBID_9005_AUTOTERM(id) \ 221 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 222 ? (((id) & 0x400) >> 10) == 0 \ 223 : (((id) & 0x40) >> 6) == 0) 224 225 #define SUBID_9005_NUMCHAN(id) \ 226 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 227 ? ((id) & 0x300) >> 8 \ 228 : ((id) & 0xC00) >> 10) 229 230 #define SUBID_9005_LEGACYCONN(id) \ 231 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 232 ? 0 \ 233 : ((id) & 0x80) >> 7) 234 235 #define SUBID_9005_MFUNCENB(id) \ 236 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 237 ? ((id) & 0x800) >> 11 \ 238 : ((id) & 0x1000) >> 12) 239 /* 240 * Informational only. Should use chip register to be 241 * certain, but may be use in identification strings. 242 */ 243 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 244 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 245 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000 246 247 static ahc_device_setup_t ahc_aic785X_setup; 248 static ahc_device_setup_t ahc_aic7860_setup; 249 static ahc_device_setup_t ahc_apa1480_setup; 250 static ahc_device_setup_t ahc_aic7870_setup; 251 static ahc_device_setup_t ahc_aha394X_setup; 252 static ahc_device_setup_t ahc_aha494X_setup; 253 static ahc_device_setup_t ahc_aha398X_setup; 254 static ahc_device_setup_t ahc_aic7880_setup; 255 static ahc_device_setup_t ahc_aha2940Pro_setup; 256 static ahc_device_setup_t ahc_aha394XU_setup; 257 static ahc_device_setup_t ahc_aha398XU_setup; 258 static ahc_device_setup_t ahc_aic7890_setup; 259 static ahc_device_setup_t ahc_aic7892_setup; 260 static ahc_device_setup_t ahc_aic7895_setup; 261 static ahc_device_setup_t ahc_aic7896_setup; 262 static ahc_device_setup_t ahc_aic7899_setup; 263 static ahc_device_setup_t ahc_aha29160C_setup; 264 static ahc_device_setup_t ahc_raid_setup; 265 static ahc_device_setup_t ahc_aha394XX_setup; 266 static ahc_device_setup_t ahc_aha494XX_setup; 267 static ahc_device_setup_t ahc_aha398XX_setup; 268 269 static struct ahc_pci_identity ahc_pci_ident_table [] = 270 { 271 /* aic7850 based controllers */ 272 { 273 ID_AHA_2902_04_10_15_20_30C, 274 ID_ALL_MASK, 275 "Adaptec 2902/04/10/15/20/30C SCSI adapter", 276 ahc_aic785X_setup 277 }, 278 /* aic7860 based controllers */ 279 { 280 ID_AHA_2930CU, 281 ID_ALL_MASK, 282 "Adaptec 2930CU SCSI adapter", 283 ahc_aic7860_setup 284 }, 285 { 286 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 287 ID_DEV_VENDOR_MASK, 288 "Adaptec 1480A Ultra SCSI adapter", 289 ahc_apa1480_setup 290 }, 291 { 292 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 293 ID_DEV_VENDOR_MASK, 294 "Adaptec 2940A Ultra SCSI adapter", 295 ahc_aic7860_setup 296 }, 297 { 298 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 299 ID_DEV_VENDOR_MASK, 300 "Adaptec 2940A/CN Ultra SCSI adapter", 301 ahc_aic7860_setup 302 }, 303 { 304 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 305 ID_DEV_VENDOR_MASK, 306 "Adaptec 2930C Ultra SCSI adapter (VAR)", 307 ahc_aic7860_setup 308 }, 309 /* aic7870 based controllers */ 310 { 311 ID_AHA_2940, 312 ID_ALL_MASK, 313 "Adaptec 2940 SCSI adapter", 314 ahc_aic7870_setup 315 }, 316 { 317 ID_AHA_3940, 318 ID_ALL_MASK, 319 "Adaptec 3940 SCSI adapter", 320 ahc_aha394X_setup 321 }, 322 { 323 ID_AHA_398X, 324 ID_ALL_MASK, 325 "Adaptec 398X SCSI RAID adapter", 326 ahc_aha398X_setup 327 }, 328 { 329 ID_AHA_2944, 330 ID_ALL_MASK, 331 "Adaptec 2944 SCSI adapter", 332 ahc_aic7870_setup 333 }, 334 { 335 ID_AHA_3944, 336 ID_ALL_MASK, 337 "Adaptec 3944 SCSI adapter", 338 ahc_aha394X_setup 339 }, 340 { 341 ID_AHA_4944, 342 ID_ALL_MASK, 343 "Adaptec 4944 SCSI adapter", 344 ahc_aha494X_setup 345 }, 346 /* aic7880 based controllers */ 347 { 348 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 349 ID_DEV_VENDOR_MASK, 350 "Adaptec 2940 Ultra SCSI adapter", 351 ahc_aic7880_setup 352 }, 353 { 354 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 355 ID_DEV_VENDOR_MASK, 356 "Adaptec 3940 Ultra SCSI adapter", 357 ahc_aha394XU_setup 358 }, 359 { 360 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 361 ID_DEV_VENDOR_MASK, 362 "Adaptec 2944 Ultra SCSI adapter", 363 ahc_aic7880_setup 364 }, 365 { 366 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 367 ID_DEV_VENDOR_MASK, 368 "Adaptec 3944 Ultra SCSI adapter", 369 ahc_aha394XU_setup 370 }, 371 { 372 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 373 ID_DEV_VENDOR_MASK, 374 "Adaptec 398X Ultra SCSI RAID adapter", 375 ahc_aha398XU_setup 376 }, 377 { 378 /* 379 * XXX Don't know the slot numbers 380 * so we can't identify channels 381 */ 382 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 383 ID_DEV_VENDOR_MASK, 384 "Adaptec 4944 Ultra SCSI adapter", 385 ahc_aic7880_setup 386 }, 387 { 388 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 389 ID_DEV_VENDOR_MASK, 390 "Adaptec 2930 Ultra SCSI adapter", 391 ahc_aic7880_setup 392 }, 393 { 394 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 395 ID_DEV_VENDOR_MASK, 396 "Adaptec 2940 Pro Ultra SCSI adapter", 397 ahc_aha2940Pro_setup 398 }, 399 { 400 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 401 ID_DEV_VENDOR_MASK, 402 "Adaptec 2940/CN Ultra SCSI adapter", 403 ahc_aic7880_setup 404 }, 405 /* Ignore all SISL (AAC on MB) based controllers. */ 406 { 407 ID_9005_SISL_ID, 408 ID_9005_SISL_MASK, 409 NULL, 410 NULL 411 }, 412 /* aic7890 based controllers */ 413 { 414 ID_AHA_2930U2, 415 ID_ALL_MASK, 416 "Adaptec 2930 Ultra2 SCSI adapter", 417 ahc_aic7890_setup 418 }, 419 { 420 ID_AHA_2940U2B, 421 ID_ALL_MASK, 422 "Adaptec 2940B Ultra2 SCSI adapter", 423 ahc_aic7890_setup 424 }, 425 { 426 ID_AHA_2940U2_OEM, 427 ID_ALL_MASK, 428 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 429 ahc_aic7890_setup 430 }, 431 { 432 ID_AHA_2940U2, 433 ID_ALL_MASK, 434 "Adaptec 2940 Ultra2 SCSI adapter", 435 ahc_aic7890_setup 436 }, 437 { 438 ID_AHA_2950U2B, 439 ID_ALL_MASK, 440 "Adaptec 2950 Ultra2 SCSI adapter", 441 ahc_aic7890_setup 442 }, 443 { 444 ID_AIC7890_ARO, 445 ID_ALL_MASK, 446 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)", 447 ahc_aic7890_setup 448 }, 449 { 450 ID_AAA_131U2, 451 ID_ALL_MASK, 452 "Adaptec AAA-131 Ultra2 RAID adapter", 453 ahc_aic7890_setup 454 }, 455 /* aic7892 based controllers */ 456 { 457 ID_AHA_29160, 458 ID_ALL_MASK, 459 "Adaptec 29160 Ultra160 SCSI adapter", 460 ahc_aic7892_setup 461 }, 462 { 463 ID_AHA_29160_CPQ, 464 ID_ALL_MASK, 465 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 466 ahc_aic7892_setup 467 }, 468 { 469 ID_AHA_29160N, 470 ID_ALL_MASK, 471 "Adaptec 29160N Ultra160 SCSI adapter", 472 ahc_aic7892_setup 473 }, 474 { 475 ID_AHA_29160C, 476 ID_ALL_MASK, 477 "Adaptec 29160C Ultra160 SCSI adapter", 478 ahc_aha29160C_setup 479 }, 480 { 481 ID_AHA_29160B, 482 ID_ALL_MASK, 483 "Adaptec 29160B Ultra160 SCSI adapter", 484 ahc_aic7892_setup 485 }, 486 { 487 ID_AHA_19160B, 488 ID_ALL_MASK, 489 "Adaptec 19160B Ultra160 SCSI adapter", 490 ahc_aic7892_setup 491 }, 492 { 493 ID_AIC7892_ARO, 494 ID_ALL_MASK, 495 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)", 496 ahc_aic7892_setup 497 }, 498 { 499 ID_AHA_2915LP, 500 ID_ALL_MASK, 501 "Adaptec 2915LP Ultra160 SCSI adapter", 502 ahc_aic7892_setup 503 }, 504 /* aic7895 based controllers */ 505 { 506 ID_AHA_2940U_DUAL, 507 ID_ALL_MASK, 508 "Adaptec 2940/DUAL Ultra SCSI adapter", 509 ahc_aic7895_setup 510 }, 511 { 512 ID_AHA_3940AU, 513 ID_ALL_MASK, 514 "Adaptec 3940A Ultra SCSI adapter", 515 ahc_aic7895_setup 516 }, 517 { 518 ID_AHA_3944AU, 519 ID_ALL_MASK, 520 "Adaptec 3944A Ultra SCSI adapter", 521 ahc_aic7895_setup 522 }, 523 { 524 ID_AIC7895_ARO, 525 ID_AIC7895_ARO_MASK, 526 "Adaptec aic7895 Ultra SCSI adapter (ARO)", 527 ahc_aic7895_setup 528 }, 529 /* aic7896/97 based controllers */ 530 { 531 ID_AHA_3950U2B_0, 532 ID_ALL_MASK, 533 "Adaptec 3950B Ultra2 SCSI adapter", 534 ahc_aic7896_setup 535 }, 536 { 537 ID_AHA_3950U2B_1, 538 ID_ALL_MASK, 539 "Adaptec 3950B Ultra2 SCSI adapter", 540 ahc_aic7896_setup 541 }, 542 { 543 ID_AHA_3950U2D_0, 544 ID_ALL_MASK, 545 "Adaptec 3950D Ultra2 SCSI adapter", 546 ahc_aic7896_setup 547 }, 548 { 549 ID_AHA_3950U2D_1, 550 ID_ALL_MASK, 551 "Adaptec 3950D Ultra2 SCSI adapter", 552 ahc_aic7896_setup 553 }, 554 { 555 ID_AIC7896_ARO, 556 ID_ALL_MASK, 557 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)", 558 ahc_aic7896_setup 559 }, 560 /* aic7899 based controllers */ 561 { 562 ID_AHA_3960D, 563 ID_ALL_MASK, 564 "Adaptec 3960D Ultra160 SCSI adapter", 565 ahc_aic7899_setup 566 }, 567 { 568 ID_AHA_3960D_CPQ, 569 ID_ALL_MASK, 570 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 571 ahc_aic7899_setup 572 }, 573 { 574 ID_AIC7899_ARO, 575 ID_ALL_MASK, 576 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)", 577 ahc_aic7899_setup 578 }, 579 /* Generic chip probes for devices we don't know 'exactly' */ 580 { 581 ID_AIC7850 & ID_DEV_VENDOR_MASK, 582 ID_DEV_VENDOR_MASK, 583 "Adaptec aic7850 SCSI adapter", 584 ahc_aic785X_setup 585 }, 586 { 587 ID_AIC7855 & ID_DEV_VENDOR_MASK, 588 ID_DEV_VENDOR_MASK, 589 "Adaptec aic7855 SCSI adapter", 590 ahc_aic785X_setup 591 }, 592 { 593 ID_AIC7859 & ID_DEV_VENDOR_MASK, 594 ID_DEV_VENDOR_MASK, 595 "Adaptec aic7859 SCSI adapter", 596 ahc_aic7860_setup 597 }, 598 { 599 ID_AIC7860 & ID_DEV_VENDOR_MASK, 600 ID_DEV_VENDOR_MASK, 601 "Adaptec aic7860 Ultra SCSI adapter", 602 ahc_aic7860_setup 603 }, 604 { 605 ID_AIC7870 & ID_DEV_VENDOR_MASK, 606 ID_DEV_VENDOR_MASK, 607 "Adaptec aic7870 SCSI adapter", 608 ahc_aic7870_setup 609 }, 610 { 611 ID_AIC7880 & ID_DEV_VENDOR_MASK, 612 ID_DEV_VENDOR_MASK, 613 "Adaptec aic7880 Ultra SCSI adapter", 614 ahc_aic7880_setup 615 }, 616 { 617 ID_AIC7890 & ID_9005_GENERIC_MASK, 618 ID_9005_GENERIC_MASK, 619 "Adaptec aic7890/91 Ultra2 SCSI adapter", 620 ahc_aic7890_setup 621 }, 622 { 623 ID_AIC7892 & ID_9005_GENERIC_MASK, 624 ID_9005_GENERIC_MASK, 625 "Adaptec aic7892 Ultra160 SCSI adapter", 626 ahc_aic7892_setup 627 }, 628 { 629 ID_AIC7895 & ID_DEV_VENDOR_MASK, 630 ID_DEV_VENDOR_MASK, 631 "Adaptec aic7895 Ultra SCSI adapter", 632 ahc_aic7895_setup 633 }, 634 { 635 ID_AIC7896 & ID_9005_GENERIC_MASK, 636 ID_9005_GENERIC_MASK, 637 "Adaptec aic7896/97 Ultra2 SCSI adapter", 638 ahc_aic7896_setup 639 }, 640 { 641 ID_AIC7899 & ID_9005_GENERIC_MASK, 642 ID_9005_GENERIC_MASK, 643 "Adaptec aic7899 Ultra160 SCSI adapter", 644 ahc_aic7899_setup 645 }, 646 { 647 ID_AIC7810 & ID_DEV_VENDOR_MASK, 648 ID_DEV_VENDOR_MASK, 649 "Adaptec aic7810 RAID memory controller", 650 ahc_raid_setup 651 }, 652 { 653 ID_AIC7815 & ID_DEV_VENDOR_MASK, 654 ID_DEV_VENDOR_MASK, 655 "Adaptec aic7815 RAID memory controller", 656 ahc_raid_setup 657 } 658 }; 659 660 static const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table); 661 662 #define AHC_394X_SLOT_CHANNEL_A 4 663 #define AHC_394X_SLOT_CHANNEL_B 5 664 665 #define AHC_398X_SLOT_CHANNEL_A 4 666 #define AHC_398X_SLOT_CHANNEL_B 8 667 #define AHC_398X_SLOT_CHANNEL_C 12 668 669 #define AHC_494X_SLOT_CHANNEL_A 4 670 #define AHC_494X_SLOT_CHANNEL_B 5 671 #define AHC_494X_SLOT_CHANNEL_C 6 672 #define AHC_494X_SLOT_CHANNEL_D 7 673 674 #define DEVCONFIG 0x40 675 #define PCIERRGENDIS 0x80000000ul 676 #define SCBSIZE32 0x00010000ul /* aic789X only */ 677 #define REXTVALID 0x00001000ul /* ultra cards only */ 678 #define MPORTMODE 0x00000400ul /* aic7870+ only */ 679 #define RAMPSM 0x00000200ul /* aic7870+ only */ 680 #define VOLSENSE 0x00000100ul 681 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ 682 #define SCBRAMSEL 0x00000080ul 683 #define MRDCEN 0x00000040ul 684 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 685 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 686 #define BERREN 0x00000008ul 687 #define DACEN 0x00000004ul 688 #define STPWLEVEL 0x00000002ul 689 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 690 691 #define CSIZE_LATTIME 0x0c 692 #define CACHESIZE 0x0000003ful /* only 5 bits */ 693 #define LATTIME 0x0000ff00ul 694 695 /* PCI STATUS definitions */ 696 #define DPE 0x80 697 #define SSE 0x40 698 #define RMA 0x20 699 #define RTA 0x10 700 #define STA 0x08 701 #define DPR 0x01 702 703 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device, 704 uint16_t subvendor, uint16_t subdevice); 705 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 706 static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 707 int pcheck, int fast, int large); 708 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 709 710 static void ahc_pci_intr(struct ahc_softc *); 711 712 static const struct ahc_pci_identity * 713 ahc_find_pci_device(pcireg_t id, pcireg_t subid, u_int func) 714 { 715 u_int64_t full_id; 716 const struct ahc_pci_identity *entry; 717 u_int i; 718 719 full_id = ahc_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 720 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 721 722 /* 723 * If the second function is not hooked up, ignore it. 724 * Unfortunately, not all MB vendors implement the 725 * subdevice ID as per the Adaptec spec, so do our best 726 * to sanity check it prior to accepting the subdevice 727 * ID as valid. 728 */ 729 if (func > 0 730 && ahc_9005_subdevinfo_valid(PCI_VENDOR(id), PCI_PRODUCT(id), 731 PCI_VENDOR(subid), PCI_PRODUCT(subid)) 732 && SUBID_9005_MFUNCENB(PCI_PRODUCT(subid)) == 0) 733 return (NULL); 734 735 for (i = 0; i < ahc_num_pci_devs; i++) { 736 entry = &ahc_pci_ident_table[i]; 737 if (entry->full_id == (full_id & entry->id_mask)) 738 return (entry); 739 } 740 return (NULL); 741 } 742 743 static int 744 ahc_pci_probe(struct device *parent, struct cfdata *match, 745 void *aux) 746 { 747 struct pci_attach_args *pa = aux; 748 const struct ahc_pci_identity *entry; 749 pcireg_t subid; 750 751 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 752 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); 753 return (entry != NULL && entry->setup != NULL) ? 1 : 0; 754 } 755 756 static void 757 ahc_pci_attach(struct device *parent, struct device *self, void *aux) 758 { 759 struct pci_attach_args *pa = aux; 760 const struct ahc_pci_identity *entry; 761 struct ahc_softc *ahc = (void *)self; 762 pcireg_t command; 763 u_int our_id = 0; 764 u_int sxfrctl1; 765 u_int scsiseq; 766 u_int sblkctl; 767 uint8_t dscommand0; 768 uint32_t devconfig; 769 int error; 770 pcireg_t subid; 771 int ioh_valid; 772 bus_space_tag_t st, iot; 773 bus_space_handle_t sh, ioh; 774 #ifdef AHC_ALLOW_MEMIO 775 int memh_valid; 776 bus_space_tag_t memt; 777 bus_space_handle_t memh; 778 pcireg_t memtype; 779 #endif 780 pci_intr_handle_t ih; 781 const char *intrstr; 782 struct ahc_pci_busdata *bd; 783 784 ahc_set_name(ahc, ahc->sc_dev.dv_xname); 785 ahc->parent_dmat = pa->pa_dmat; 786 787 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 788 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 789 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); 790 if (entry == NULL) 791 return; 792 printf(": %s\n", entry->name); 793 794 /* Keep information about the PCI bus */ 795 bd = malloc(sizeof (struct ahc_pci_busdata), M_DEVBUF, M_NOWAIT); 796 if (bd == NULL) { 797 printf("%s: unable to allocate bus-specific data\n", 798 ahc_name(ahc)); 799 return; 800 } 801 memset(bd, 0, sizeof(struct ahc_pci_busdata)); 802 803 bd->pc = pa->pa_pc; 804 bd->tag = pa->pa_tag; 805 bd->func = pa->pa_function; 806 bd->dev = pa->pa_device; 807 bd->class = pa->pa_class; 808 809 ahc->bd = bd; 810 811 ahc->description = entry->name; 812 813 error = entry->setup(ahc); 814 if (error != 0) 815 return; 816 817 ioh_valid = 0; 818 819 #ifdef AHC_ALLOW_MEMIO 820 memh_valid = 0; 821 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHC_PCI_MEMADDR); 822 switch (memtype) { 823 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 824 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 825 memh_valid = (pci_mapreg_map(pa, AHC_PCI_MEMADDR, 826 memtype, 0, &memt, &memh, NULL, NULL) == 0); 827 break; 828 default: 829 memh_valid = 0; 830 } 831 #endif 832 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_IOADDR, 833 PCI_MAPREG_TYPE_IO, 0, &iot, 834 &ioh, NULL, NULL) == 0); 835 #if 0 836 printf("%s: bus info: memt 0x%lx, memh 0x%lx, iot 0x%lx, ioh 0x%lx\n", 837 ahc_name(ahc), (u_long)memt, (u_long)memh, (u_long)iot, 838 (u_long)ioh); 839 #endif 840 841 if (ioh_valid) { 842 st = iot; 843 sh = ioh; 844 #ifdef AHC_ALLOW_MEMIO 845 } else if (memh_valid) { 846 st = memt; 847 sh = memh; 848 #endif 849 } else { 850 printf(": unable to map registers\n"); 851 return; 852 } 853 ahc->tag = st; 854 ahc->bsh = sh; 855 856 ahc->chip |= AHC_PCI; 857 /* 858 * Before we continue probing the card, ensure that 859 * its interrupts are *disabled*. We don't want 860 * a misstep to hang the machine in an interrupt 861 * storm. 862 */ 863 ahc_intr_enable(ahc, FALSE); 864 865 /* 866 * XXX somehow reading this once fails on some sparc64 systems. 867 * This may be a problem in the sparc64 PCI code. Doing it 868 * twice works around it. 869 */ 870 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 871 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 872 873 /* 874 * If we need to support high memory, enable dual 875 * address cycles. This bit must be set to enable 876 * high address bit generation even if we are on a 877 * 64bit bus (PCI64BIT set in devconfig). 878 */ 879 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 880 881 if (1/*bootverbose*/) 882 printf("%s: Enabling 39Bit Addressing\n", 883 ahc_name(ahc)); 884 devconfig |= DACEN; 885 } 886 887 /* Ensure that pci error generation, a test feature, is disabled. */ 888 devconfig |= PCIERRGENDIS; 889 890 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); 891 892 /* Ensure busmastering is enabled */ 893 command |= PCI_COMMAND_MASTER_ENABLE;; 894 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 895 896 /* 897 * Disable PCI parity error reporting. Users typically 898 * do this to work around broken PCI chipsets that get 899 * the parity timing wrong and thus generate lots of spurious 900 * errors. 901 */ 902 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0) 903 command &= ~PCI_COMMAND_PARITY_ENABLE; 904 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 905 906 /* On all PCI adapters, we allow SCB paging */ 907 ahc->flags |= AHC_PAGESCBS; 908 error = ahc_softc_init(ahc); 909 if (error != 0) 910 goto error_out; 911 912 ahc->bus_intr = ahc_pci_intr; 913 914 /* Remember how the card was setup in case there is no SEEPROM */ 915 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 916 ahc_pause(ahc); 917 if ((ahc->features & AHC_ULTRA2) != 0) 918 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 919 else 920 our_id = ahc_inb(ahc, SCSIID) & OID; 921 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 922 scsiseq = ahc_inb(ahc, SCSISEQ); 923 } else { 924 sxfrctl1 = STPWEN; 925 our_id = 7; 926 scsiseq = 0; 927 } 928 929 error = ahc_reset(ahc); 930 if (error != 0) 931 goto error_out; 932 933 if ((ahc->features & AHC_DT) != 0) { 934 u_int sfunct; 935 936 /* Perform ALT-Mode Setup */ 937 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 938 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 939 ahc_outb(ahc, OPTIONMODE, 940 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 941 ahc_outb(ahc, SFUNCT, sfunct); 942 943 /* Normal mode setup */ 944 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 945 |TARGCRCENDEN); 946 } 947 948 if (pci_intr_map(pa, &ih)) { 949 printf("%s: couldn't map interrupt\n", ahc_name(ahc)); 950 ahc_free(ahc); 951 return; 952 } 953 intrstr = pci_intr_string(pa->pa_pc, ih); 954 ahc->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahc_intr, ahc); 955 if (ahc->ih == NULL) { 956 printf("%s: couldn't establish interrupt", 957 ahc->sc_dev.dv_xname); 958 if (intrstr != NULL) 959 printf(" at %s", intrstr); 960 printf("\n"); 961 ahc_free(ahc); 962 return; 963 } 964 if (intrstr != NULL) 965 printf("%s: interrupting at %s\n", ahc_name(ahc), intrstr); 966 967 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 968 dscommand0 |= MPARCKEN|CACHETHEN; 969 if ((ahc->features & AHC_ULTRA2) != 0) { 970 971 /* 972 * DPARCKEN doesn't work correctly on 973 * some MBs so don't use it. 974 */ 975 dscommand0 &= ~DPARCKEN; 976 } 977 978 /* 979 * Handle chips that must have cache line 980 * streaming (dis/en)abled. 981 */ 982 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 983 dscommand0 |= CACHETHEN; 984 985 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 986 dscommand0 &= ~CACHETHEN; 987 988 ahc_outb(ahc, DSCOMMAND0, dscommand0); 989 990 ahc->pci_cachesize = 991 pci_conf_read(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME) & CACHESIZE; 992 ahc->pci_cachesize *= 4; 993 994 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 995 && ahc->pci_cachesize == 4) { 996 pci_conf_write(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME, 0); 997 ahc->pci_cachesize = 0; 998 } 999 1000 /* 1001 * We cannot perform ULTRA speeds without the presence 1002 * of the external precision resistor. 1003 */ 1004 if ((ahc->features & AHC_ULTRA) != 0) { 1005 uint32_t dvconfig; 1006 1007 dvconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 1008 if ((dvconfig & REXTVALID) == 0) 1009 ahc->features &= ~AHC_ULTRA; 1010 } 1011 1012 ahc->seep_config = malloc(sizeof(*ahc->seep_config), 1013 M_DEVBUF, M_NOWAIT); 1014 if (ahc->seep_config == NULL) 1015 goto error_out; 1016 1017 memset(ahc->seep_config, 0, sizeof(*ahc->seep_config)); 1018 1019 /* See if we have a SEEPROM and perform auto-term */ 1020 ahc_check_extport(ahc, &sxfrctl1); 1021 1022 /* 1023 * Take the LED out of diagnostic mode 1024 */ 1025 sblkctl = ahc_inb(ahc, SBLKCTL); 1026 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 1027 1028 if ((ahc->features & AHC_ULTRA2) != 0) { 1029 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 1030 } else { 1031 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 1032 } 1033 1034 if (ahc->flags & AHC_USEDEFAULTS) { 1035 /* 1036 * PCI Adapter default setup 1037 * Should only be used if the adapter does not have 1038 * a SEEPROM. 1039 */ 1040 /* See if someone else set us up already */ 1041 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0 1042 && scsiseq != 0) { 1043 prop_bool_t usetd; 1044 1045 printf("%s: Using left over BIOS settings\n", 1046 ahc_name(ahc)); 1047 ahc->flags &= ~AHC_USEDEFAULTS; 1048 /* 1049 * Ignore target device settings and use default 1050 * if BIOS initializes chip's SRAM with some 1051 * conservative settings (async, no tagged 1052 * queuing etc.) and machine dependent device 1053 * property is set. 1054 */ 1055 usetd = prop_dictionary_get( 1056 device_properties(&ahc->sc_dev), 1057 "aic7xxx-use-target-defaults"); 1058 if (usetd != NULL) { 1059 KASSERT(prop_object_type(usetd) == 1060 PROP_TYPE_BOOL); 1061 if (prop_bool_true(usetd)) 1062 ahc->flags |= AHC_USETARGETDEFAULTS; 1063 } 1064 ahc->flags |= AHC_BIOS_ENABLED; 1065 } else { 1066 /* 1067 * Assume only one connector and always turn 1068 * on termination. 1069 */ 1070 our_id = 0x07; 1071 sxfrctl1 = STPWEN; 1072 } 1073 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 1074 1075 ahc->our_id = our_id; 1076 } 1077 1078 /* 1079 * Take a look to see if we have external SRAM. 1080 * We currently do not attempt to use SRAM that is 1081 * shared among multiple controllers. 1082 */ 1083 ahc_probe_ext_scbram(ahc); 1084 1085 /* 1086 * Record our termination setting for the 1087 * generic initialization routine. 1088 */ 1089 if ((sxfrctl1 & STPWEN) != 0) 1090 ahc->flags |= AHC_TERM_ENB_A; 1091 1092 if (ahc_init(ahc)) 1093 goto error_out; 1094 1095 ahc_attach(ahc); 1096 1097 return; 1098 1099 error_out: 1100 ahc_free(ahc); 1101 return; 1102 } 1103 1104 CFATTACH_DECL(ahc_pci, sizeof(struct ahc_softc), 1105 ahc_pci_probe, ahc_pci_attach, NULL, NULL); 1106 1107 static int 1108 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, 1109 uint16_t subdevice, uint16_t subvendor) 1110 { 1111 int result; 1112 1113 /* Default to invalid. */ 1114 result = 0; 1115 if (vendor == 0x9005 1116 && subvendor == 0x9005 1117 && subdevice != device 1118 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) { 1119 1120 switch (SUBID_9005_TYPE(subdevice)) { 1121 case SUBID_9005_TYPE_MB: 1122 break; 1123 case SUBID_9005_TYPE_CARD: 1124 case SUBID_9005_TYPE_LCCARD: 1125 /* 1126 * Currently only trust Adaptec cards to 1127 * get the sub device info correct. 1128 */ 1129 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA) 1130 result = 1; 1131 break; 1132 case SUBID_9005_TYPE_RAID: 1133 break; 1134 default: 1135 break; 1136 } 1137 } 1138 return (result); 1139 } 1140 1141 1142 /* 1143 * Test for the presense of external sram in an 1144 * "unshared" configuration. 1145 */ 1146 static int 1147 ahc_ext_scbram_present(struct ahc_softc *ahc) 1148 { 1149 u_int chip; 1150 int ramps; 1151 int single_user; 1152 uint32_t devconfig; 1153 1154 chip = ahc->chip & AHC_CHIPID_MASK; 1155 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1156 single_user = (devconfig & MPORTMODE) != 0; 1157 1158 if ((ahc->features & AHC_ULTRA2) != 0) 1159 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 1160 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C) 1161 /* 1162 * External SCBRAM arbitration is flakey 1163 * on these chips. Unfortunately this means 1164 * we don't use the extra SCB ram space on the 1165 * 3940AUW. 1166 */ 1167 ramps = 0; 1168 else if (chip >= AHC_AIC7870) 1169 ramps = (devconfig & RAMPSM) != 0; 1170 else 1171 ramps = 0; 1172 1173 if (ramps && single_user) 1174 return (1); 1175 return (0); 1176 } 1177 1178 /* 1179 * Enable external scbram. 1180 */ 1181 static void 1182 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 1183 int fast, int large) 1184 { 1185 uint32_t devconfig; 1186 1187 if (ahc->features & AHC_MULTI_FUNC) { 1188 /* 1189 * Set the SCB Base addr (highest address bit) 1190 * depending on which channel we are. 1191 */ 1192 ahc_outb(ahc, SCBBADDR, ahc->bd->func); 1193 } 1194 1195 ahc->flags &= ~AHC_LSCBS_ENABLED; 1196 if (large) 1197 ahc->flags |= AHC_LSCBS_ENABLED; 1198 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1199 if ((ahc->features & AHC_ULTRA2) != 0) { 1200 u_int dscommand0; 1201 1202 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1203 if (enable) 1204 dscommand0 &= ~INTSCBRAMSEL; 1205 else 1206 dscommand0 |= INTSCBRAMSEL; 1207 if (large) 1208 dscommand0 &= ~USCBSIZE32; 1209 else 1210 dscommand0 |= USCBSIZE32; 1211 ahc_outb(ahc, DSCOMMAND0, dscommand0); 1212 } else { 1213 if (fast) 1214 devconfig &= ~EXTSCBTIME; 1215 else 1216 devconfig |= EXTSCBTIME; 1217 if (enable) 1218 devconfig &= ~SCBRAMSEL; 1219 else 1220 devconfig |= SCBRAMSEL; 1221 if (large) 1222 devconfig &= ~SCBSIZE32; 1223 else 1224 devconfig |= SCBSIZE32; 1225 } 1226 if (pcheck) 1227 devconfig |= EXTSCBPEN; 1228 else 1229 devconfig &= ~EXTSCBPEN; 1230 1231 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig); 1232 } 1233 1234 /* 1235 * Take a look to see if we have external SRAM. 1236 * We currently do not attempt to use SRAM that is 1237 * shared among multiple controllers. 1238 */ 1239 static void 1240 ahc_probe_ext_scbram(struct ahc_softc *ahc) 1241 { 1242 int num_scbs; 1243 int test_num_scbs; 1244 int enable; 1245 int pcheck; 1246 int fast; 1247 int large; 1248 1249 enable = FALSE; 1250 pcheck = FALSE; 1251 fast = FALSE; 1252 large = FALSE; 1253 num_scbs = 0; 1254 1255 if (ahc_ext_scbram_present(ahc) == 0) 1256 goto done; 1257 1258 /* 1259 * Probe for the best parameters to use. 1260 */ 1261 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 1262 num_scbs = ahc_probe_scbs(ahc); 1263 if (num_scbs == 0) { 1264 /* The SRAM wasn't really present. */ 1265 goto done; 1266 } 1267 enable = TRUE; 1268 1269 /* 1270 * Clear any outstanding parity error 1271 * and ensure that parity error reporting 1272 * is enabled. 1273 */ 1274 ahc_outb(ahc, SEQCTL, 0); 1275 ahc_outb(ahc, CLRINT, CLRPARERR); 1276 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1277 1278 /* Now see if we can do parity */ 1279 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1280 num_scbs = ahc_probe_scbs(ahc); 1281 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1282 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1283 pcheck = TRUE; 1284 1285 /* Clear any resulting parity error */ 1286 ahc_outb(ahc, CLRINT, CLRPARERR); 1287 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1288 1289 /* Now see if we can do fast timing */ 1290 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1291 test_num_scbs = ahc_probe_scbs(ahc); 1292 if (test_num_scbs == num_scbs 1293 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1294 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1295 fast = TRUE; 1296 1297 /* 1298 * See if we can use large SCBs and still maintain 1299 * the same overall count of SCBs. 1300 */ 1301 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1302 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1303 test_num_scbs = ahc_probe_scbs(ahc); 1304 if (test_num_scbs >= num_scbs) { 1305 large = TRUE; 1306 num_scbs = test_num_scbs; 1307 if (num_scbs >= 64) { 1308 /* 1309 * We have enough space to move the 1310 * "busy targets table" into SCB space 1311 * and make it qualify all the way to the 1312 * lun level. 1313 */ 1314 ahc->flags |= AHC_SCB_BTT; 1315 } 1316 } 1317 } 1318 done: 1319 /* 1320 * Disable parity error reporting until we 1321 * can load instruction ram. 1322 */ 1323 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1324 /* Clear any latched parity error */ 1325 ahc_outb(ahc, CLRINT, CLRPARERR); 1326 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1327 if (1/*bootverbose*/ && enable) { 1328 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1329 ahc_name(ahc), fast ? "fast" : "slow", 1330 pcheck ? ", parity checking enabled" : "", 1331 large ? 64 : 32); 1332 } 1333 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1334 } 1335 1336 #if 0 1337 /* 1338 * Perform some simple tests that should catch situations where 1339 * our registers are invalidly mapped. 1340 */ 1341 static int 1342 ahc_pci_test_register_access(struct ahc_softc *ahc) 1343 { 1344 int error; 1345 u_int status1; 1346 uint32_t cmd; 1347 uint8_t hcntrl; 1348 1349 error = EIO; 1350 1351 /* 1352 * Enable PCI error interrupt status, but suppress NMIs 1353 * generated by SERR raised due to target aborts. 1354 */ 1355 cmd = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND); 1356 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND, 1357 cmd & ~PCIM_CMD_SERRESPEN); 1358 1359 /* 1360 * First a simple test to see if any 1361 * registers can be read. Reading 1362 * HCNTRL has no side effects and has 1363 * at least one bit that is guaranteed to 1364 * be zero so it is a good register to 1365 * use for this test. 1366 */ 1367 hcntrl = ahc_inb(ahc, HCNTRL); 1368 if (hcntrl == 0xFF) 1369 goto fail; 1370 1371 /* 1372 * Next create a situation where write combining 1373 * or read prefetching could be initiated by the 1374 * CPU or host bridge. Our device does not support 1375 * either, so look for data corruption and/or flagged 1376 * PCI errors. 1377 */ 1378 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE); 1379 while (ahc_is_paused(ahc) == 0) 1380 ; 1381 ahc_outb(ahc, SEQCTL, PERRORDIS); 1382 ahc_outb(ahc, SCBPTR, 0); 1383 ahc_outl(ahc, SCB_BASE, 0x5aa555aa); 1384 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa) 1385 goto fail; 1386 1387 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1388 PCI_COMMAND_STATUS_REG + 1); 1389 if ((status1 & STA) != 0) 1390 goto fail; 1391 1392 error = 0; 1393 1394 fail: 1395 /* Silently clear any latched errors. */ 1396 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1397 PCI_COMMAND_STATUS_REG + 1); 1398 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1399 status1, /*bytes*/1); 1400 ahc_outb(ahc, CLRINT, CLRPARERR); 1401 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1402 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 1403 return (error); 1404 } 1405 #endif 1406 1407 static void 1408 ahc_pci_intr(struct ahc_softc *ahc) 1409 { 1410 u_int error; 1411 u_int status1; 1412 1413 error = ahc_inb(ahc, ERROR); 1414 if ((error & PCIERRSTAT) == 0) 1415 return; 1416 1417 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1418 PCI_COMMAND_STATUS_REG); 1419 1420 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1421 ahc_name(ahc), 1422 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1423 1424 if (status1 & DPE) { 1425 printf("%s: Data Parity Error Detected during address " 1426 "or write data phase\n", ahc_name(ahc)); 1427 } 1428 if (status1 & SSE) { 1429 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1430 } 1431 if (status1 & RMA) { 1432 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1433 } 1434 if (status1 & RTA) { 1435 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1436 } 1437 if (status1 & STA) { 1438 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1439 } 1440 if (status1 & DPR) { 1441 printf("%s: Data Parity Error has been reported via PERR#\n", 1442 ahc_name(ahc)); 1443 } 1444 1445 /* Clear latched errors. */ 1446 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG, 1447 status1); 1448 1449 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1450 printf("%s: Latched PCIERR interrupt with " 1451 "no status bits set\n", ahc_name(ahc)); 1452 } else { 1453 ahc_outb(ahc, CLRINT, CLRPARERR); 1454 } 1455 1456 ahc_unpause(ahc); 1457 } 1458 1459 static int 1460 ahc_aic785X_setup(struct ahc_softc *ahc) 1461 { 1462 uint8_t rev; 1463 1464 ahc->channel = 'A'; 1465 ahc->chip = AHC_AIC7850; 1466 ahc->features = AHC_AIC7850_FE; 1467 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1468 rev = PCI_REVISION(ahc->bd->class); 1469 if (rev >= 1) 1470 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1471 return (0); 1472 } 1473 1474 static int 1475 ahc_aic7860_setup(struct ahc_softc *ahc) 1476 { 1477 uint8_t rev; 1478 1479 ahc->channel = 'A'; 1480 ahc->chip = AHC_AIC7860; 1481 ahc->features = AHC_AIC7860_FE; 1482 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1483 rev = PCI_REVISION(ahc->bd->class); 1484 if (rev >= 1) 1485 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1486 return (0); 1487 } 1488 1489 static int 1490 ahc_apa1480_setup(struct ahc_softc *ahc) 1491 { 1492 int error; 1493 1494 error = ahc_aic7860_setup(ahc); 1495 if (error != 0) 1496 return (error); 1497 ahc->features |= AHC_REMOVABLE; 1498 return (0); 1499 } 1500 1501 static int 1502 ahc_aic7870_setup(struct ahc_softc *ahc) 1503 { 1504 1505 ahc->channel = 'A'; 1506 ahc->chip = AHC_AIC7870; 1507 ahc->features = AHC_AIC7870_FE; 1508 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1509 return (0); 1510 } 1511 1512 static int 1513 ahc_aha394X_setup(struct ahc_softc *ahc) 1514 { 1515 int error; 1516 1517 error = ahc_aic7870_setup(ahc); 1518 if (error == 0) 1519 error = ahc_aha394XX_setup(ahc); 1520 return (error); 1521 } 1522 1523 static int 1524 ahc_aha398X_setup(struct ahc_softc *ahc) 1525 { 1526 int error; 1527 1528 error = ahc_aic7870_setup(ahc); 1529 if (error == 0) 1530 error = ahc_aha398XX_setup(ahc); 1531 return (error); 1532 } 1533 1534 static int 1535 ahc_aha494X_setup(struct ahc_softc *ahc) 1536 { 1537 int error; 1538 1539 error = ahc_aic7870_setup(ahc); 1540 if (error == 0) 1541 error = ahc_aha494XX_setup(ahc); 1542 return (error); 1543 } 1544 1545 static int 1546 ahc_aic7880_setup(struct ahc_softc *ahc) 1547 { 1548 uint8_t rev; 1549 1550 ahc->channel = 'A'; 1551 ahc->chip = AHC_AIC7880; 1552 ahc->features = AHC_AIC7880_FE; 1553 ahc->bugs |= AHC_TMODE_WIDEODD_BUG; 1554 rev = PCI_REVISION(ahc->bd->class); 1555 if (rev >= 1) { 1556 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1557 } else { 1558 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1559 } 1560 return (0); 1561 } 1562 1563 static int 1564 ahc_aha2940Pro_setup(struct ahc_softc *ahc) 1565 { 1566 1567 ahc->flags |= AHC_INT50_SPEEDFLEX; 1568 return (ahc_aic7880_setup(ahc)); 1569 } 1570 1571 static int 1572 ahc_aha394XU_setup(struct ahc_softc *ahc) 1573 { 1574 int error; 1575 1576 error = ahc_aic7880_setup(ahc); 1577 if (error == 0) 1578 error = ahc_aha394XX_setup(ahc); 1579 return (error); 1580 } 1581 1582 static int 1583 ahc_aha398XU_setup(struct ahc_softc *ahc) 1584 { 1585 int error; 1586 1587 error = ahc_aic7880_setup(ahc); 1588 if (error == 0) 1589 error = ahc_aha398XX_setup(ahc); 1590 return (error); 1591 } 1592 1593 static int 1594 ahc_aic7890_setup(struct ahc_softc *ahc) 1595 { 1596 uint8_t rev; 1597 1598 ahc->channel = 'A'; 1599 ahc->chip = AHC_AIC7890; 1600 ahc->features = AHC_AIC7890_FE; 1601 ahc->flags |= AHC_NEWEEPROM_FMT; 1602 rev = PCI_REVISION(ahc->bd->class); 1603 if (rev == 0) 1604 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 1605 return (0); 1606 } 1607 1608 static int 1609 ahc_aic7892_setup(struct ahc_softc *ahc) 1610 { 1611 1612 ahc->channel = 'A'; 1613 ahc->chip = AHC_AIC7892; 1614 ahc->features = AHC_AIC7892_FE; 1615 ahc->flags |= AHC_NEWEEPROM_FMT; 1616 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1617 return (0); 1618 } 1619 1620 static int 1621 ahc_aic7895_setup(struct ahc_softc *ahc) 1622 { 1623 uint8_t rev; 1624 1625 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1626 /* 1627 * The 'C' revision of the aic7895 has a few additional features. 1628 */ 1629 rev = PCI_REVISION(ahc->bd->class); 1630 if (rev >= 4) { 1631 ahc->chip = AHC_AIC7895C; 1632 ahc->features = AHC_AIC7895C_FE; 1633 } else { 1634 u_int command; 1635 1636 ahc->chip = AHC_AIC7895; 1637 ahc->features = AHC_AIC7895_FE; 1638 1639 /* 1640 * The BIOS disables the use of MWI transactions 1641 * since it does not have the MWI bug work around 1642 * we have. Disabling MWI reduces performance, so 1643 * turn it on again. 1644 */ 1645 command = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1646 PCI_COMMAND_STATUS_REG); 1647 command |= PCI_COMMAND_INVALIDATE_ENABLE; 1648 pci_conf_write(ahc->bd->pc, ahc->bd->tag, 1649 PCI_COMMAND_STATUS_REG, command); 1650 ahc->bugs |= AHC_PCI_MWI_BUG; 1651 } 1652 /* 1653 * XXX Does CACHETHEN really not work??? What about PCI retry? 1654 * on C level chips. Need to test, but for now, play it safe. 1655 */ 1656 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 1657 | AHC_CACHETHEN_BUG; 1658 1659 #if 0 1660 uint32_t devconfig; 1661 1662 /* 1663 * Cachesize must also be zero due to stray DAC 1664 * problem when sitting behind some bridges. 1665 */ 1666 pci_conf_write(ahc->bd->pc, ahc->bd->tag, CSIZE_LATTIME, 0); 1667 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1668 devconfig |= MRDCEN; 1669 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig); 1670 #endif 1671 ahc->flags |= AHC_NEWEEPROM_FMT; 1672 return (0); 1673 } 1674 1675 static int 1676 ahc_aic7896_setup(struct ahc_softc *ahc) 1677 { 1678 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1679 ahc->chip = AHC_AIC7896; 1680 ahc->features = AHC_AIC7896_FE; 1681 ahc->flags |= AHC_NEWEEPROM_FMT; 1682 ahc->bugs |= AHC_CACHETHEN_DIS_BUG; 1683 return (0); 1684 } 1685 1686 static int 1687 ahc_aic7899_setup(struct ahc_softc *ahc) 1688 { 1689 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1690 ahc->chip = AHC_AIC7899; 1691 ahc->features = AHC_AIC7899_FE; 1692 ahc->flags |= AHC_NEWEEPROM_FMT; 1693 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1694 return (0); 1695 } 1696 1697 static int 1698 ahc_aha29160C_setup(struct ahc_softc *ahc) 1699 { 1700 int error; 1701 1702 error = ahc_aic7899_setup(ahc); 1703 if (error != 0) 1704 return (error); 1705 ahc->features |= AHC_REMOVABLE; 1706 return (0); 1707 } 1708 1709 static int 1710 ahc_raid_setup(struct ahc_softc *ahc) 1711 { 1712 printf("%s: RAID functionality unsupported\n", ahc->sc_dev.dv_xname); 1713 return (ENXIO); 1714 } 1715 1716 static int 1717 ahc_aha394XX_setup(struct ahc_softc *ahc) 1718 { 1719 1720 switch (ahc->bd->dev) { 1721 case AHC_394X_SLOT_CHANNEL_A: 1722 ahc->channel = 'A'; 1723 break; 1724 case AHC_394X_SLOT_CHANNEL_B: 1725 ahc->channel = 'B'; 1726 break; 1727 default: 1728 printf("adapter at unexpected slot %d\n" 1729 "unable to map to a channel\n", 1730 ahc->bd->dev); 1731 ahc->channel = 'A'; 1732 } 1733 return (0); 1734 } 1735 1736 static int 1737 ahc_aha398XX_setup(struct ahc_softc *ahc) 1738 { 1739 1740 switch (ahc->bd->dev) { 1741 case AHC_398X_SLOT_CHANNEL_A: 1742 ahc->channel = 'A'; 1743 break; 1744 case AHC_398X_SLOT_CHANNEL_B: 1745 ahc->channel = 'B'; 1746 break; 1747 case AHC_398X_SLOT_CHANNEL_C: 1748 ahc->channel = 'C'; 1749 break; 1750 default: 1751 printf("adapter at unexpected slot %d\n" 1752 "unable to map to a channel\n", 1753 ahc->bd->dev); 1754 ahc->channel = 'A'; 1755 break; 1756 } 1757 ahc->flags |= AHC_LARGE_SEEPROM; 1758 return (0); 1759 } 1760 1761 static int 1762 ahc_aha494XX_setup(struct ahc_softc *ahc) 1763 { 1764 1765 switch (ahc->bd->dev) { 1766 case AHC_494X_SLOT_CHANNEL_A: 1767 ahc->channel = 'A'; 1768 break; 1769 case AHC_494X_SLOT_CHANNEL_B: 1770 ahc->channel = 'B'; 1771 break; 1772 case AHC_494X_SLOT_CHANNEL_C: 1773 ahc->channel = 'C'; 1774 break; 1775 case AHC_494X_SLOT_CHANNEL_D: 1776 ahc->channel = 'D'; 1777 break; 1778 default: 1779 printf("adapter at unexpected slot %d\n" 1780 "unable to map to a channel\n", 1781 ahc->bd->dev); 1782 ahc->channel = 'A'; 1783 } 1784 ahc->flags |= AHC_LARGE_SEEPROM; 1785 return (0); 1786 } 1787
Indexes created Wed Oct 01 19:09:53 GMT 2025