ahc_pci.c revision 1.63.12.1
1 /* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1994-2001 Justin T. Gibbs. 7 * Copyright (c) 2000-2001 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: ahc_pci.c,v 1.63.12.1 2009/01/19 13:18:24 skrll Exp $ 43 * 44 * //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#57 $ 45 * 46 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.22 2003/01/20 20:44:55 gibbs Exp $ 47 */ 48 /* 49 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: ahc_pci.c,v 1.63.12.1 2009/01/19 13:18:24 skrll Exp $"); 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/queue.h> 60 #include <sys/device.h> 61 #include <sys/reboot.h> 62 63 #include <sys/bus.h> 64 #include <sys/intr.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 70 /* XXXX some i386 on-board chips act weird when memory-mapped */ 71 #ifndef __i386__ 72 #define AHC_ALLOW_MEMIO 73 #endif 74 75 #define AHC_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 76 #define AHC_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 77 78 #include <dev/ic/aic7xxx_osm.h> 79 #include <dev/ic/aic7xxx_inline.h> 80 81 #include <dev/ic/smc93cx6var.h> 82 83 84 static inline uint64_t 85 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 86 { 87 uint64_t id; 88 89 id = subvendor 90 | (subdevice << 16) 91 | ((uint64_t)vendor << 32) 92 | ((uint64_t)device << 48); 93 94 return (id); 95 } 96 97 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 98 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 99 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 100 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull 101 #define ID_9005_SISL_ID 0x0005900500000000ull 102 #define ID_AIC7850 0x5078900400000000ull 103 #define ID_AHA_2902_04_10_15_20_30C 0x5078900478509004ull 104 #define ID_AIC7855 0x5578900400000000ull 105 #define ID_AIC7859 0x3860900400000000ull 106 #define ID_AHA_2930CU 0x3860900438699004ull 107 #define ID_AIC7860 0x6078900400000000ull 108 #define ID_AIC7860C 0x6078900478609004ull 109 #define ID_AHA_1480A 0x6075900400000000ull 110 #define ID_AHA_2940AU_0 0x6178900400000000ull 111 #define ID_AHA_2940AU_1 0x6178900478619004ull 112 #define ID_AHA_2940AU_CN 0x2178900478219004ull 113 #define ID_AHA_2930C_VAR 0x6038900438689004ull 114 115 #define ID_AIC7870 0x7078900400000000ull 116 #define ID_AHA_2940 0x7178900400000000ull 117 #define ID_AHA_3940 0x7278900400000000ull 118 #define ID_AHA_398X 0x7378900400000000ull 119 #define ID_AHA_2944 0x7478900400000000ull 120 #define ID_AHA_3944 0x7578900400000000ull 121 #define ID_AHA_4944 0x7678900400000000ull 122 123 #define ID_AIC7880 0x8078900400000000ull 124 #define ID_AIC7880_B 0x8078900478809004ull 125 #define ID_AHA_2940U 0x8178900400000000ull 126 #define ID_AHA_3940U 0x8278900400000000ull 127 #define ID_AHA_2944U 0x8478900400000000ull 128 #define ID_AHA_3944U 0x8578900400000000ull 129 #define ID_AHA_398XU 0x8378900400000000ull 130 #define ID_AHA_4944U 0x8678900400000000ull 131 #define ID_AHA_2940UB 0x8178900478819004ull 132 #define ID_AHA_2930U 0x8878900478889004ull 133 #define ID_AHA_2940U_PRO 0x8778900478879004ull 134 #define ID_AHA_2940U_CN 0x0078900478009004ull 135 136 #define ID_AIC7895 0x7895900478959004ull 137 #define ID_AIC7895_ARO 0x7890900478939004ull 138 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull 139 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 140 #define ID_AHA_3940AU 0x7895900478929004ull 141 #define ID_AHA_3944AU 0x7895900478949004ull 142 143 #define ID_AIC7890 0x001F9005000F9005ull 144 #define ID_AIC7890_ARO 0x00139005000F9005ull 145 #define ID_AAA_131U2 0x0013900500039005ull 146 #define ID_AHA_2930U2 0x0011900501819005ull 147 #define ID_AHA_2940U2B 0x00109005A1009005ull 148 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 149 #define ID_AHA_2940U2 0x00109005A1809005ull 150 #define ID_AHA_2950U2B 0x00109005E1009005ull 151 152 #define ID_AIC7892 0x008F9005FFFF9005ull 153 #define ID_AIC7892_ARO 0x00839005FFFF9005ull 154 #define ID_AHA_2915LP 0x0082900502109005ull 155 #define ID_AHA_29160 0x00809005E2A09005ull 156 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 157 #define ID_AHA_29160N 0x0080900562A09005ull 158 #define ID_AHA_29160C 0x0080900562209005ull 159 #define ID_AHA_29160B 0x00809005E2209005ull 160 #define ID_AHA_19160B 0x0081900562A19005ull 161 162 #define ID_AIC7896 0x005F9005FFFF9005ull 163 #define ID_AIC7896_ARO 0x00539005FFFF9005ull 164 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 165 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 166 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 167 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 168 169 #define ID_AIC7899 0x00CF9005FFFF9005ull 170 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull 171 #define ID_AHA_3960D 0x00C09005F6209005ull 172 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 173 174 #define ID_AIC7810 0x1078900400000000ull 175 #define ID_AIC7815 0x7815900400000000ull 176 177 #define DEVID_9005_TYPE(id) ((id) & 0xF) 178 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 179 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ 180 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */ 181 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 182 183 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 184 #define DEVID_9005_MAXRATE_U160 0x0 185 #define DEVID_9005_MAXRATE_ULTRA2 0x1 186 #define DEVID_9005_MAXRATE_ULTRA 0x2 187 #define DEVID_9005_MAXRATE_FAST 0x3 188 189 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) 190 191 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) 192 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ 193 194 #define SUBID_9005_TYPE(id) ((id) & 0xF) 195 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 196 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 197 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 198 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 199 200 #define SUBID_9005_TYPE_KNOWN(id) \ 201 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ 202 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ 203 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ 204 || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) 205 206 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 207 #define SUBID_9005_MAXRATE_ULTRA2 0x0 208 #define SUBID_9005_MAXRATE_ULTRA 0x1 209 #define SUBID_9005_MAXRATE_U160 0x2 210 #define SUBID_9005_MAXRATE_RESERVED 0x3 211 212 #define SUBID_9005_SEEPTYPE(id) \ 213 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 214 ? ((id) & 0xC0) >> 6 \ 215 : ((id) & 0x300) >> 8) 216 #define SUBID_9005_SEEPTYPE_NONE 0x0 217 #define SUBID_9005_SEEPTYPE_1K 0x1 218 #define SUBID_9005_SEEPTYPE_2K_4K 0x2 219 #define SUBID_9005_SEEPTYPE_RESERVED 0x3 220 #define SUBID_9005_AUTOTERM(id) \ 221 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 222 ? (((id) & 0x400) >> 10) == 0 \ 223 : (((id) & 0x40) >> 6) == 0) 224 225 #define SUBID_9005_NUMCHAN(id) \ 226 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 227 ? ((id) & 0x300) >> 8 \ 228 : ((id) & 0xC00) >> 10) 229 230 #define SUBID_9005_LEGACYCONN(id) \ 231 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 232 ? 0 \ 233 : ((id) & 0x80) >> 7) 234 235 #define SUBID_9005_MFUNCENB(id) \ 236 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 237 ? ((id) & 0x800) >> 11 \ 238 : ((id) & 0x1000) >> 12) 239 /* 240 * Informational only. Should use chip register to be 241 * certain, but may be use in identification strings. 242 */ 243 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 244 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 245 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000 246 247 static ahc_device_setup_t ahc_aic785X_setup; 248 static ahc_device_setup_t ahc_aic7860_setup; 249 static ahc_device_setup_t ahc_apa1480_setup; 250 static ahc_device_setup_t ahc_aic7870_setup; 251 static ahc_device_setup_t ahc_aha394X_setup; 252 static ahc_device_setup_t ahc_aha494X_setup; 253 static ahc_device_setup_t ahc_aha398X_setup; 254 static ahc_device_setup_t ahc_aic7880_setup; 255 static ahc_device_setup_t ahc_aha2940Pro_setup; 256 static ahc_device_setup_t ahc_aha394XU_setup; 257 static ahc_device_setup_t ahc_aha398XU_setup; 258 static ahc_device_setup_t ahc_aic7890_setup; 259 static ahc_device_setup_t ahc_aic7892_setup; 260 static ahc_device_setup_t ahc_aic7895_setup; 261 static ahc_device_setup_t ahc_aic7896_setup; 262 static ahc_device_setup_t ahc_aic7899_setup; 263 static ahc_device_setup_t ahc_aha29160C_setup; 264 static ahc_device_setup_t ahc_raid_setup; 265 static ahc_device_setup_t ahc_aha394XX_setup; 266 static ahc_device_setup_t ahc_aha494XX_setup; 267 static ahc_device_setup_t ahc_aha398XX_setup; 268 269 static struct ahc_pci_identity ahc_pci_ident_table [] = 270 { 271 /* aic7850 based controllers */ 272 { 273 ID_AHA_2902_04_10_15_20_30C, 274 ID_ALL_MASK, 275 "Adaptec 2902/04/10/15/20/30C SCSI adapter", 276 ahc_aic785X_setup 277 }, 278 /* aic7860 based controllers */ 279 { 280 ID_AHA_2930CU, 281 ID_ALL_MASK, 282 "Adaptec 2930CU SCSI adapter", 283 ahc_aic7860_setup 284 }, 285 { 286 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 287 ID_DEV_VENDOR_MASK, 288 "Adaptec 1480A Ultra SCSI adapter", 289 ahc_apa1480_setup 290 }, 291 { 292 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 293 ID_DEV_VENDOR_MASK, 294 "Adaptec 2940A Ultra SCSI adapter", 295 ahc_aic7860_setup 296 }, 297 { 298 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 299 ID_DEV_VENDOR_MASK, 300 "Adaptec 2940A/CN Ultra SCSI adapter", 301 ahc_aic7860_setup 302 }, 303 { 304 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 305 ID_DEV_VENDOR_MASK, 306 "Adaptec 2930C Ultra SCSI adapter (VAR)", 307 ahc_aic7860_setup 308 }, 309 /* aic7870 based controllers */ 310 { 311 ID_AHA_2940, 312 ID_ALL_MASK, 313 "Adaptec 2940 SCSI adapter", 314 ahc_aic7870_setup 315 }, 316 { 317 ID_AHA_3940, 318 ID_ALL_MASK, 319 "Adaptec 3940 SCSI adapter", 320 ahc_aha394X_setup 321 }, 322 { 323 ID_AHA_398X, 324 ID_ALL_MASK, 325 "Adaptec 398X SCSI RAID adapter", 326 ahc_aha398X_setup 327 }, 328 { 329 ID_AHA_2944, 330 ID_ALL_MASK, 331 "Adaptec 2944 SCSI adapter", 332 ahc_aic7870_setup 333 }, 334 { 335 ID_AHA_3944, 336 ID_ALL_MASK, 337 "Adaptec 3944 SCSI adapter", 338 ahc_aha394X_setup 339 }, 340 { 341 ID_AHA_4944, 342 ID_ALL_MASK, 343 "Adaptec 4944 SCSI adapter", 344 ahc_aha494X_setup 345 }, 346 /* aic7880 based controllers */ 347 { 348 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 349 ID_DEV_VENDOR_MASK, 350 "Adaptec 2940 Ultra SCSI adapter", 351 ahc_aic7880_setup 352 }, 353 { 354 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 355 ID_DEV_VENDOR_MASK, 356 "Adaptec 3940 Ultra SCSI adapter", 357 ahc_aha394XU_setup 358 }, 359 { 360 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 361 ID_DEV_VENDOR_MASK, 362 "Adaptec 2944 Ultra SCSI adapter", 363 ahc_aic7880_setup 364 }, 365 { 366 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 367 ID_DEV_VENDOR_MASK, 368 "Adaptec 3944 Ultra SCSI adapter", 369 ahc_aha394XU_setup 370 }, 371 { 372 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 373 ID_DEV_VENDOR_MASK, 374 "Adaptec 398X Ultra SCSI RAID adapter", 375 ahc_aha398XU_setup 376 }, 377 { 378 /* 379 * XXX Don't know the slot numbers 380 * so we can't identify channels 381 */ 382 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 383 ID_DEV_VENDOR_MASK, 384 "Adaptec 4944 Ultra SCSI adapter", 385 ahc_aic7880_setup 386 }, 387 { 388 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 389 ID_DEV_VENDOR_MASK, 390 "Adaptec 2930 Ultra SCSI adapter", 391 ahc_aic7880_setup 392 }, 393 { 394 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 395 ID_DEV_VENDOR_MASK, 396 "Adaptec 2940 Pro Ultra SCSI adapter", 397 ahc_aha2940Pro_setup 398 }, 399 { 400 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 401 ID_DEV_VENDOR_MASK, 402 "Adaptec 2940/CN Ultra SCSI adapter", 403 ahc_aic7880_setup 404 }, 405 /* Ignore all SISL (AAC on MB) based controllers. */ 406 { 407 ID_9005_SISL_ID, 408 ID_9005_SISL_MASK, 409 NULL, 410 NULL 411 }, 412 /* aic7890 based controllers */ 413 { 414 ID_AHA_2930U2, 415 ID_ALL_MASK, 416 "Adaptec 2930 Ultra2 SCSI adapter", 417 ahc_aic7890_setup 418 }, 419 { 420 ID_AHA_2940U2B, 421 ID_ALL_MASK, 422 "Adaptec 2940B Ultra2 SCSI adapter", 423 ahc_aic7890_setup 424 }, 425 { 426 ID_AHA_2940U2_OEM, 427 ID_ALL_MASK, 428 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 429 ahc_aic7890_setup 430 }, 431 { 432 ID_AHA_2940U2, 433 ID_ALL_MASK, 434 "Adaptec 2940 Ultra2 SCSI adapter", 435 ahc_aic7890_setup 436 }, 437 { 438 ID_AHA_2950U2B, 439 ID_ALL_MASK, 440 "Adaptec 2950 Ultra2 SCSI adapter", 441 ahc_aic7890_setup 442 }, 443 { 444 ID_AIC7890_ARO, 445 ID_ALL_MASK, 446 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)", 447 ahc_aic7890_setup 448 }, 449 { 450 ID_AAA_131U2, 451 ID_ALL_MASK, 452 "Adaptec AAA-131 Ultra2 RAID adapter", 453 ahc_aic7890_setup 454 }, 455 /* aic7892 based controllers */ 456 { 457 ID_AHA_29160, 458 ID_ALL_MASK, 459 "Adaptec 29160 Ultra160 SCSI adapter", 460 ahc_aic7892_setup 461 }, 462 { 463 ID_AHA_29160_CPQ, 464 ID_ALL_MASK, 465 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 466 ahc_aic7892_setup 467 }, 468 { 469 ID_AHA_29160N, 470 ID_ALL_MASK, 471 "Adaptec 29160N Ultra160 SCSI adapter", 472 ahc_aic7892_setup 473 }, 474 { 475 ID_AHA_29160C, 476 ID_ALL_MASK, 477 "Adaptec 29160C Ultra160 SCSI adapter", 478 ahc_aha29160C_setup 479 }, 480 { 481 ID_AHA_29160B, 482 ID_ALL_MASK, 483 "Adaptec 29160B Ultra160 SCSI adapter", 484 ahc_aic7892_setup 485 }, 486 { 487 ID_AHA_19160B, 488 ID_ALL_MASK, 489 "Adaptec 19160B Ultra160 SCSI adapter", 490 ahc_aic7892_setup 491 }, 492 { 493 ID_AIC7892_ARO, 494 ID_ALL_MASK, 495 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)", 496 ahc_aic7892_setup 497 }, 498 { 499 ID_AHA_2915LP, 500 ID_ALL_MASK, 501 "Adaptec 2915LP Ultra160 SCSI adapter", 502 ahc_aic7892_setup 503 }, 504 /* aic7895 based controllers */ 505 { 506 ID_AHA_2940U_DUAL, 507 ID_ALL_MASK, 508 "Adaptec 2940/DUAL Ultra SCSI adapter", 509 ahc_aic7895_setup 510 }, 511 { 512 ID_AHA_3940AU, 513 ID_ALL_MASK, 514 "Adaptec 3940A Ultra SCSI adapter", 515 ahc_aic7895_setup 516 }, 517 { 518 ID_AHA_3944AU, 519 ID_ALL_MASK, 520 "Adaptec 3944A Ultra SCSI adapter", 521 ahc_aic7895_setup 522 }, 523 { 524 ID_AIC7895_ARO, 525 ID_AIC7895_ARO_MASK, 526 "Adaptec aic7895 Ultra SCSI adapter (ARO)", 527 ahc_aic7895_setup 528 }, 529 /* aic7896/97 based controllers */ 530 { 531 ID_AHA_3950U2B_0, 532 ID_ALL_MASK, 533 "Adaptec 3950B Ultra2 SCSI adapter", 534 ahc_aic7896_setup 535 }, 536 { 537 ID_AHA_3950U2B_1, 538 ID_ALL_MASK, 539 "Adaptec 3950B Ultra2 SCSI adapter", 540 ahc_aic7896_setup 541 }, 542 { 543 ID_AHA_3950U2D_0, 544 ID_ALL_MASK, 545 "Adaptec 3950D Ultra2 SCSI adapter", 546 ahc_aic7896_setup 547 }, 548 { 549 ID_AHA_3950U2D_1, 550 ID_ALL_MASK, 551 "Adaptec 3950D Ultra2 SCSI adapter", 552 ahc_aic7896_setup 553 }, 554 { 555 ID_AIC7896_ARO, 556 ID_ALL_MASK, 557 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)", 558 ahc_aic7896_setup 559 }, 560 /* aic7899 based controllers */ 561 { 562 ID_AHA_3960D, 563 ID_ALL_MASK, 564 "Adaptec 3960D Ultra160 SCSI adapter", 565 ahc_aic7899_setup 566 }, 567 { 568 ID_AHA_3960D_CPQ, 569 ID_ALL_MASK, 570 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 571 ahc_aic7899_setup 572 }, 573 { 574 ID_AIC7899_ARO, 575 ID_ALL_MASK, 576 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)", 577 ahc_aic7899_setup 578 }, 579 /* Generic chip probes for devices we don't know 'exactly' */ 580 { 581 ID_AIC7850 & ID_DEV_VENDOR_MASK, 582 ID_DEV_VENDOR_MASK, 583 "Adaptec aic7850 SCSI adapter", 584 ahc_aic785X_setup 585 }, 586 { 587 ID_AIC7855 & ID_DEV_VENDOR_MASK, 588 ID_DEV_VENDOR_MASK, 589 "Adaptec aic7855 SCSI adapter", 590 ahc_aic785X_setup 591 }, 592 { 593 ID_AIC7859 & ID_DEV_VENDOR_MASK, 594 ID_DEV_VENDOR_MASK, 595 "Adaptec aic7859 SCSI adapter", 596 ahc_aic7860_setup 597 }, 598 { 599 ID_AIC7860 & ID_DEV_VENDOR_MASK, 600 ID_DEV_VENDOR_MASK, 601 "Adaptec aic7860 Ultra SCSI adapter", 602 ahc_aic7860_setup 603 }, 604 { 605 ID_AIC7870 & ID_DEV_VENDOR_MASK, 606 ID_DEV_VENDOR_MASK, 607 "Adaptec aic7870 SCSI adapter", 608 ahc_aic7870_setup 609 }, 610 { 611 ID_AIC7880 & ID_DEV_VENDOR_MASK, 612 ID_DEV_VENDOR_MASK, 613 "Adaptec aic7880 Ultra SCSI adapter", 614 ahc_aic7880_setup 615 }, 616 { 617 ID_AIC7890 & ID_9005_GENERIC_MASK, 618 ID_9005_GENERIC_MASK, 619 "Adaptec aic7890/91 Ultra2 SCSI adapter", 620 ahc_aic7890_setup 621 }, 622 { 623 ID_AIC7892 & ID_9005_GENERIC_MASK, 624 ID_9005_GENERIC_MASK, 625 "Adaptec aic7892 Ultra160 SCSI adapter", 626 ahc_aic7892_setup 627 }, 628 { 629 ID_AIC7895 & ID_DEV_VENDOR_MASK, 630 ID_DEV_VENDOR_MASK, 631 "Adaptec aic7895 Ultra SCSI adapter", 632 ahc_aic7895_setup 633 }, 634 { 635 ID_AIC7896 & ID_9005_GENERIC_MASK, 636 ID_9005_GENERIC_MASK, 637 "Adaptec aic7896/97 Ultra2 SCSI adapter", 638 ahc_aic7896_setup 639 }, 640 { 641 ID_AIC7899 & ID_9005_GENERIC_MASK, 642 ID_9005_GENERIC_MASK, 643 "Adaptec aic7899 Ultra160 SCSI adapter", 644 ahc_aic7899_setup 645 }, 646 { 647 ID_AIC7810 & ID_DEV_VENDOR_MASK, 648 ID_DEV_VENDOR_MASK, 649 "Adaptec aic7810 RAID memory controller", 650 ahc_raid_setup 651 }, 652 { 653 ID_AIC7815 & ID_DEV_VENDOR_MASK, 654 ID_DEV_VENDOR_MASK, 655 "Adaptec aic7815 RAID memory controller", 656 ahc_raid_setup 657 } 658 }; 659 660 static const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table); 661 662 #define AHC_394X_SLOT_CHANNEL_A 4 663 #define AHC_394X_SLOT_CHANNEL_B 5 664 665 #define AHC_398X_SLOT_CHANNEL_A 4 666 #define AHC_398X_SLOT_CHANNEL_B 8 667 #define AHC_398X_SLOT_CHANNEL_C 12 668 669 #define AHC_494X_SLOT_CHANNEL_A 4 670 #define AHC_494X_SLOT_CHANNEL_B 5 671 #define AHC_494X_SLOT_CHANNEL_C 6 672 #define AHC_494X_SLOT_CHANNEL_D 7 673 674 #define DEVCONFIG 0x40 675 #define PCIERRGENDIS 0x80000000ul 676 #define SCBSIZE32 0x00010000ul /* aic789X only */ 677 #define REXTVALID 0x00001000ul /* ultra cards only */ 678 #define MPORTMODE 0x00000400ul /* aic7870+ only */ 679 #define RAMPSM 0x00000200ul /* aic7870+ only */ 680 #define VOLSENSE 0x00000100ul 681 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ 682 #define SCBRAMSEL 0x00000080ul 683 #define MRDCEN 0x00000040ul 684 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 685 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 686 #define BERREN 0x00000008ul 687 #define DACEN 0x00000004ul 688 #define STPWLEVEL 0x00000002ul 689 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 690 691 #define CSIZE_LATTIME 0x0c 692 #define CACHESIZE 0x0000003ful /* only 5 bits */ 693 #define LATTIME 0x0000ff00ul 694 695 /* PCI STATUS definitions */ 696 #define DPE 0x80 697 #define SSE 0x40 698 #define RMA 0x20 699 #define RTA 0x10 700 #define STA 0x08 701 #define DPR 0x01 702 703 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device, 704 uint16_t subvendor, uint16_t subdevice); 705 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 706 static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 707 int pcheck, int fast, int large); 708 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 709 710 static void ahc_pci_intr(struct ahc_softc *); 711 712 static bool ahc_pci_suspend(device_t PMF_FN_PROTO); 713 static bool ahc_pci_resume(device_t PMF_FN_PROTO); 714 715 static const struct ahc_pci_identity * 716 ahc_find_pci_device(pcireg_t id, pcireg_t subid, u_int func) 717 { 718 u_int64_t full_id; 719 const struct ahc_pci_identity *entry; 720 u_int i; 721 722 full_id = ahc_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 723 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 724 725 /* 726 * If the second function is not hooked up, ignore it. 727 * Unfortunately, not all MB vendors implement the 728 * subdevice ID as per the Adaptec spec, so do our best 729 * to sanity check it prior to accepting the subdevice 730 * ID as valid. 731 */ 732 if (func > 0 733 && ahc_9005_subdevinfo_valid(PCI_VENDOR(id), PCI_PRODUCT(id), 734 PCI_VENDOR(subid), PCI_PRODUCT(subid)) 735 && SUBID_9005_MFUNCENB(PCI_PRODUCT(subid)) == 0) 736 return (NULL); 737 738 for (i = 0; i < ahc_num_pci_devs; i++) { 739 entry = &ahc_pci_ident_table[i]; 740 if (entry->full_id == (full_id & entry->id_mask)) 741 return (entry); 742 } 743 return (NULL); 744 } 745 746 static int 747 ahc_pci_probe(device_t parent, struct cfdata *match, void *aux) 748 { 749 struct pci_attach_args *pa = aux; 750 const struct ahc_pci_identity *entry; 751 pcireg_t subid; 752 753 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 754 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); 755 return (entry != NULL && entry->setup != NULL) ? 1 : 0; 756 } 757 758 static void 759 ahc_pci_attach(device_t parent, device_t self, void *aux) 760 { 761 struct pci_attach_args *pa = aux; 762 const struct ahc_pci_identity *entry; 763 struct ahc_softc *ahc = device_private(self); 764 pcireg_t command; 765 u_int our_id = 0; 766 u_int sxfrctl1; 767 u_int scsiseq; 768 u_int sblkctl; 769 uint8_t dscommand0; 770 uint32_t devconfig; 771 int error; 772 pcireg_t subid; 773 int ioh_valid; 774 bus_space_tag_t st, iot; 775 bus_space_handle_t sh, ioh; 776 #ifdef AHC_ALLOW_MEMIO 777 int memh_valid; 778 bus_space_tag_t memt; 779 bus_space_handle_t memh; 780 pcireg_t memtype; 781 #endif 782 pci_intr_handle_t ih; 783 const char *intrstr; 784 struct ahc_pci_busdata *bd; 785 bool override_ultra; 786 787 ahc_set_name(ahc, device_xname(&ahc->sc_dev)); 788 ahc->parent_dmat = pa->pa_dmat; 789 790 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 791 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 792 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); 793 if (entry == NULL) 794 return; 795 printf(": %s\n", entry->name); 796 797 /* Keep information about the PCI bus */ 798 bd = malloc(sizeof (struct ahc_pci_busdata), M_DEVBUF, M_NOWAIT); 799 if (bd == NULL) { 800 printf("%s: unable to allocate bus-specific data\n", 801 ahc_name(ahc)); 802 return; 803 } 804 memset(bd, 0, sizeof(struct ahc_pci_busdata)); 805 806 bd->pc = pa->pa_pc; 807 bd->tag = pa->pa_tag; 808 bd->func = pa->pa_function; 809 bd->dev = pa->pa_device; 810 bd->class = pa->pa_class; 811 812 ahc->bd = bd; 813 814 ahc->description = entry->name; 815 816 error = entry->setup(ahc); 817 if (error != 0) 818 return; 819 820 ioh_valid = 0; 821 822 #ifdef AHC_ALLOW_MEMIO 823 memh_valid = 0; 824 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHC_PCI_MEMADDR); 825 switch (memtype) { 826 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 827 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 828 memh_valid = (pci_mapreg_map(pa, AHC_PCI_MEMADDR, 829 memtype, 0, &memt, &memh, NULL, NULL) == 0); 830 break; 831 default: 832 memh_valid = 0; 833 } 834 #endif 835 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_IOADDR, 836 PCI_MAPREG_TYPE_IO, 0, &iot, 837 &ioh, NULL, NULL) == 0); 838 #if 0 839 printf("%s: bus info: memt 0x%lx, memh 0x%lx, iot 0x%lx, ioh 0x%lx\n", 840 ahc_name(ahc), (u_long)memt, (u_long)memh, (u_long)iot, 841 (u_long)ioh); 842 #endif 843 844 if (ioh_valid) { 845 st = iot; 846 sh = ioh; 847 #ifdef AHC_ALLOW_MEMIO 848 } else if (memh_valid) { 849 st = memt; 850 sh = memh; 851 #endif 852 } else { 853 printf(": unable to map registers\n"); 854 return; 855 } 856 ahc->tag = st; 857 ahc->bsh = sh; 858 859 ahc->chip |= AHC_PCI; 860 /* 861 * Before we continue probing the card, ensure that 862 * its interrupts are *disabled*. We don't want 863 * a misstep to hang the machine in an interrupt 864 * storm. 865 */ 866 ahc_intr_enable(ahc, FALSE); 867 868 /* 869 * XXX somehow reading this once fails on some sparc64 systems. 870 * This may be a problem in the sparc64 PCI code. Doing it 871 * twice works around it. 872 */ 873 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 874 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 875 876 /* 877 * If we need to support high memory, enable dual 878 * address cycles. This bit must be set to enable 879 * high address bit generation even if we are on a 880 * 64bit bus (PCI64BIT set in devconfig). 881 */ 882 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 883 884 if (1/*bootverbose*/) 885 printf("%s: Enabling 39Bit Addressing\n", 886 ahc_name(ahc)); 887 devconfig |= DACEN; 888 } 889 890 /* Ensure that pci error generation, a test feature, is disabled. */ 891 devconfig |= PCIERRGENDIS; 892 893 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); 894 895 /* Ensure busmastering is enabled */ 896 command |= PCI_COMMAND_MASTER_ENABLE; 897 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 898 899 /* 900 * Disable PCI parity error reporting. Users typically 901 * do this to work around broken PCI chipsets that get 902 * the parity timing wrong and thus generate lots of spurious 903 * errors. 904 */ 905 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0) 906 command &= ~PCI_COMMAND_PARITY_ENABLE; 907 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 908 909 /* On all PCI adapters, we allow SCB paging */ 910 ahc->flags |= AHC_PAGESCBS; 911 error = ahc_softc_init(ahc); 912 if (error != 0) 913 goto error_out; 914 915 ahc->bus_intr = ahc_pci_intr; 916 917 /* Remember how the card was setup in case there is no SEEPROM */ 918 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 919 ahc_pause(ahc); 920 if ((ahc->features & AHC_ULTRA2) != 0) 921 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 922 else 923 our_id = ahc_inb(ahc, SCSIID) & OID; 924 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 925 scsiseq = ahc_inb(ahc, SCSISEQ); 926 } else { 927 sxfrctl1 = STPWEN; 928 our_id = 7; 929 scsiseq = 0; 930 } 931 932 error = ahc_reset(ahc); 933 if (error != 0) 934 goto error_out; 935 936 if ((ahc->features & AHC_DT) != 0) { 937 u_int sfunct; 938 939 /* Perform ALT-Mode Setup */ 940 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 941 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 942 ahc_outb(ahc, OPTIONMODE, 943 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 944 ahc_outb(ahc, SFUNCT, sfunct); 945 946 /* Normal mode setup */ 947 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 948 |TARGCRCENDEN); 949 } 950 951 if (pci_intr_map(pa, &ih)) { 952 printf("%s: couldn't map interrupt\n", ahc_name(ahc)); 953 ahc_free(ahc); 954 return; 955 } 956 intrstr = pci_intr_string(pa->pa_pc, ih); 957 ahc->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahc_intr, ahc); 958 if (ahc->ih == NULL) { 959 aprint_error_dev(&ahc->sc_dev, 960 "couldn't establish interrupt\n"); 961 if (intrstr != NULL) 962 printf(" at %s", intrstr); 963 printf("\n"); 964 ahc_free(ahc); 965 return; 966 } 967 if (intrstr != NULL) 968 printf("%s: interrupting at %s\n", ahc_name(ahc), intrstr); 969 970 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 971 dscommand0 |= MPARCKEN|CACHETHEN; 972 if ((ahc->features & AHC_ULTRA2) != 0) { 973 974 /* 975 * DPARCKEN doesn't work correctly on 976 * some MBs so don't use it. 977 */ 978 dscommand0 &= ~DPARCKEN; 979 } 980 981 /* 982 * Handle chips that must have cache line 983 * streaming (dis/en)abled. 984 */ 985 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 986 dscommand0 |= CACHETHEN; 987 988 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 989 dscommand0 &= ~CACHETHEN; 990 991 ahc_outb(ahc, DSCOMMAND0, dscommand0); 992 993 ahc->pci_cachesize = 994 pci_conf_read(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME) & CACHESIZE; 995 ahc->pci_cachesize *= 4; 996 997 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 998 && ahc->pci_cachesize == 4) { 999 pci_conf_write(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME, 0); 1000 ahc->pci_cachesize = 0; 1001 } 1002 1003 /* 1004 * We cannot perform ULTRA speeds without the presence 1005 * of the external precision resistor. 1006 * Allow override for the SGI O2 though, which has two onboard ahc 1007 * that fail here but are perfectly capable of ultra speeds. 1008 */ 1009 override_ultra = FALSE; 1010 prop_dictionary_get_bool(device_properties(self), 1011 "aic7xxx-override-ultra", &override_ultra); 1012 1013 if (((ahc->features & AHC_ULTRA) != 0) && (!override_ultra)) { 1014 uint32_t dvconfig; 1015 1016 dvconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 1017 if ((dvconfig & REXTVALID) == 0) 1018 ahc->features &= ~AHC_ULTRA; 1019 } 1020 1021 ahc->seep_config = malloc(sizeof(*ahc->seep_config), 1022 M_DEVBUF, M_NOWAIT); 1023 if (ahc->seep_config == NULL) 1024 goto error_out; 1025 1026 memset(ahc->seep_config, 0, sizeof(*ahc->seep_config)); 1027 1028 /* See if we have a SEEPROM and perform auto-term */ 1029 ahc_check_extport(ahc, &sxfrctl1); 1030 1031 /* 1032 * Take the LED out of diagnostic mode 1033 */ 1034 sblkctl = ahc_inb(ahc, SBLKCTL); 1035 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 1036 1037 if ((ahc->features & AHC_ULTRA2) != 0) { 1038 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 1039 } else { 1040 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 1041 } 1042 1043 if (ahc->flags & AHC_USEDEFAULTS) { 1044 /* 1045 * PCI Adapter default setup 1046 * Should only be used if the adapter does not have 1047 * a SEEPROM. 1048 */ 1049 /* See if someone else set us up already */ 1050 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0 1051 && scsiseq != 0) { 1052 prop_bool_t usetd; 1053 1054 printf("%s: Using left over BIOS settings\n", 1055 ahc_name(ahc)); 1056 ahc->flags &= ~AHC_USEDEFAULTS; 1057 /* 1058 * Ignore target device settings and use default 1059 * if BIOS initializes chip's SRAM with some 1060 * conservative settings (async, no tagged 1061 * queuing etc.) and machine dependent device 1062 * property is set. 1063 */ 1064 usetd = prop_dictionary_get( 1065 device_properties(&ahc->sc_dev), 1066 "aic7xxx-use-target-defaults"); 1067 if (usetd != NULL) { 1068 KASSERT(prop_object_type(usetd) == 1069 PROP_TYPE_BOOL); 1070 if (prop_bool_true(usetd)) 1071 ahc->flags |= AHC_USETARGETDEFAULTS; 1072 } 1073 ahc->flags |= AHC_BIOS_ENABLED; 1074 } else { 1075 /* 1076 * Assume only one connector and always turn 1077 * on termination. 1078 */ 1079 our_id = 0x07; 1080 sxfrctl1 = STPWEN; 1081 } 1082 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 1083 1084 ahc->our_id = our_id; 1085 } 1086 1087 /* 1088 * Take a look to see if we have external SRAM. 1089 * We currently do not attempt to use SRAM that is 1090 * shared among multiple controllers. 1091 */ 1092 ahc_probe_ext_scbram(ahc); 1093 1094 /* 1095 * Record our termination setting for the 1096 * generic initialization routine. 1097 */ 1098 if ((sxfrctl1 & STPWEN) != 0) 1099 ahc->flags |= AHC_TERM_ENB_A; 1100 1101 if (ahc_init(ahc)) 1102 goto error_out; 1103 1104 pmf_device_register(self, ahc_pci_suspend, ahc_pci_resume); 1105 ahc_attach(ahc); 1106 1107 return; 1108 1109 error_out: 1110 ahc_free(ahc); 1111 return; 1112 } 1113 1114 /* 1115 * XXX we should call the real suspend and resume functions here 1116 * but for some reason ahc_suspend() panics on shutdown 1117 */ 1118 1119 static bool 1120 ahc_pci_suspend(device_t dev PMF_FN_ARGS) 1121 { 1122 struct ahc_softc *sc = device_private(dev); 1123 #if 0 1124 return (ahc_suspend(sc) == 0); 1125 #else 1126 ahc_shutdown(sc); 1127 return true; 1128 #endif 1129 } 1130 1131 static bool 1132 ahc_pci_resume(device_t dev PMF_FN_ARGS) 1133 { 1134 #if 0 1135 struct ahc_softc *sc = device_private(dev); 1136 1137 return (ahc_resume(sc) == 0); 1138 #else 1139 return true; 1140 #endif 1141 } 1142 1143 CFATTACH_DECL(ahc_pci, sizeof(struct ahc_softc), 1144 ahc_pci_probe, ahc_pci_attach, NULL, NULL); 1145 1146 static int 1147 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, 1148 uint16_t subdevice, uint16_t subvendor) 1149 { 1150 int result; 1151 1152 /* Default to invalid. */ 1153 result = 0; 1154 if (vendor == 0x9005 1155 && subvendor == 0x9005 1156 && subdevice != device 1157 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) { 1158 1159 switch (SUBID_9005_TYPE(subdevice)) { 1160 case SUBID_9005_TYPE_MB: 1161 break; 1162 case SUBID_9005_TYPE_CARD: 1163 case SUBID_9005_TYPE_LCCARD: 1164 /* 1165 * Currently only trust Adaptec cards to 1166 * get the sub device info correct. 1167 */ 1168 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA) 1169 result = 1; 1170 break; 1171 case SUBID_9005_TYPE_RAID: 1172 break; 1173 default: 1174 break; 1175 } 1176 } 1177 return (result); 1178 } 1179 1180 1181 /* 1182 * Test for the presense of external sram in an 1183 * "unshared" configuration. 1184 */ 1185 static int 1186 ahc_ext_scbram_present(struct ahc_softc *ahc) 1187 { 1188 u_int chip; 1189 int ramps; 1190 int single_user; 1191 uint32_t devconfig; 1192 1193 chip = ahc->chip & AHC_CHIPID_MASK; 1194 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1195 single_user = (devconfig & MPORTMODE) != 0; 1196 1197 if ((ahc->features & AHC_ULTRA2) != 0) 1198 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 1199 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C) 1200 /* 1201 * External SCBRAM arbitration is flakey 1202 * on these chips. Unfortunately this means 1203 * we don't use the extra SCB ram space on the 1204 * 3940AUW. 1205 */ 1206 ramps = 0; 1207 else if (chip >= AHC_AIC7870) 1208 ramps = (devconfig & RAMPSM) != 0; 1209 else 1210 ramps = 0; 1211 1212 if (ramps && single_user) 1213 return (1); 1214 return (0); 1215 } 1216 1217 /* 1218 * Enable external scbram. 1219 */ 1220 static void 1221 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 1222 int fast, int large) 1223 { 1224 uint32_t devconfig; 1225 1226 if (ahc->features & AHC_MULTI_FUNC) { 1227 /* 1228 * Set the SCB Base addr (highest address bit) 1229 * depending on which channel we are. 1230 */ 1231 ahc_outb(ahc, SCBBADDR, ahc->bd->func); 1232 } 1233 1234 ahc->flags &= ~AHC_LSCBS_ENABLED; 1235 if (large) 1236 ahc->flags |= AHC_LSCBS_ENABLED; 1237 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1238 if ((ahc->features & AHC_ULTRA2) != 0) { 1239 u_int dscommand0; 1240 1241 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1242 if (enable) 1243 dscommand0 &= ~INTSCBRAMSEL; 1244 else 1245 dscommand0 |= INTSCBRAMSEL; 1246 if (large) 1247 dscommand0 &= ~USCBSIZE32; 1248 else 1249 dscommand0 |= USCBSIZE32; 1250 ahc_outb(ahc, DSCOMMAND0, dscommand0); 1251 } else { 1252 if (fast) 1253 devconfig &= ~EXTSCBTIME; 1254 else 1255 devconfig |= EXTSCBTIME; 1256 if (enable) 1257 devconfig &= ~SCBRAMSEL; 1258 else 1259 devconfig |= SCBRAMSEL; 1260 if (large) 1261 devconfig &= ~SCBSIZE32; 1262 else 1263 devconfig |= SCBSIZE32; 1264 } 1265 if (pcheck) 1266 devconfig |= EXTSCBPEN; 1267 else 1268 devconfig &= ~EXTSCBPEN; 1269 1270 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig); 1271 } 1272 1273 /* 1274 * Take a look to see if we have external SRAM. 1275 * We currently do not attempt to use SRAM that is 1276 * shared among multiple controllers. 1277 */ 1278 static void 1279 ahc_probe_ext_scbram(struct ahc_softc *ahc) 1280 { 1281 int num_scbs; 1282 int test_num_scbs; 1283 int enable; 1284 int pcheck; 1285 int fast; 1286 int large; 1287 1288 enable = FALSE; 1289 pcheck = FALSE; 1290 fast = FALSE; 1291 large = FALSE; 1292 num_scbs = 0; 1293 1294 if (ahc_ext_scbram_present(ahc) == 0) 1295 goto done; 1296 1297 /* 1298 * Probe for the best parameters to use. 1299 */ 1300 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 1301 num_scbs = ahc_probe_scbs(ahc); 1302 if (num_scbs == 0) { 1303 /* The SRAM wasn't really present. */ 1304 goto done; 1305 } 1306 enable = TRUE; 1307 1308 /* 1309 * Clear any outstanding parity error 1310 * and ensure that parity error reporting 1311 * is enabled. 1312 */ 1313 ahc_outb(ahc, SEQCTL, 0); 1314 ahc_outb(ahc, CLRINT, CLRPARERR); 1315 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1316 1317 /* Now see if we can do parity */ 1318 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1319 num_scbs = ahc_probe_scbs(ahc); 1320 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1321 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1322 pcheck = TRUE; 1323 1324 /* Clear any resulting parity error */ 1325 ahc_outb(ahc, CLRINT, CLRPARERR); 1326 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1327 1328 /* Now see if we can do fast timing */ 1329 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1330 test_num_scbs = ahc_probe_scbs(ahc); 1331 if (test_num_scbs == num_scbs 1332 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1333 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1334 fast = TRUE; 1335 1336 /* 1337 * See if we can use large SCBs and still maintain 1338 * the same overall count of SCBs. 1339 */ 1340 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1341 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1342 test_num_scbs = ahc_probe_scbs(ahc); 1343 if (test_num_scbs >= num_scbs) { 1344 large = TRUE; 1345 num_scbs = test_num_scbs; 1346 if (num_scbs >= 64) { 1347 /* 1348 * We have enough space to move the 1349 * "busy targets table" into SCB space 1350 * and make it qualify all the way to the 1351 * lun level. 1352 */ 1353 ahc->flags |= AHC_SCB_BTT; 1354 } 1355 } 1356 } 1357 done: 1358 /* 1359 * Disable parity error reporting until we 1360 * can load instruction ram. 1361 */ 1362 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1363 /* Clear any latched parity error */ 1364 ahc_outb(ahc, CLRINT, CLRPARERR); 1365 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1366 if (1/*bootverbose*/ && enable) { 1367 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1368 ahc_name(ahc), fast ? "fast" : "slow", 1369 pcheck ? ", parity checking enabled" : "", 1370 large ? 64 : 32); 1371 } 1372 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1373 } 1374 1375 #if 0 1376 /* 1377 * Perform some simple tests that should catch situations where 1378 * our registers are invalidly mapped. 1379 */ 1380 static int 1381 ahc_pci_test_register_access(struct ahc_softc *ahc) 1382 { 1383 int error; 1384 u_int status1; 1385 uint32_t cmd; 1386 uint8_t hcntrl; 1387 1388 error = EIO; 1389 1390 /* 1391 * Enable PCI error interrupt status, but suppress NMIs 1392 * generated by SERR raised due to target aborts. 1393 */ 1394 cmd = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND); 1395 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND, 1396 cmd & ~PCIM_CMD_SERRESPEN); 1397 1398 /* 1399 * First a simple test to see if any 1400 * registers can be read. Reading 1401 * HCNTRL has no side effects and has 1402 * at least one bit that is guaranteed to 1403 * be zero so it is a good register to 1404 * use for this test. 1405 */ 1406 hcntrl = ahc_inb(ahc, HCNTRL); 1407 if (hcntrl == 0xFF) 1408 goto fail; 1409 1410 /* 1411 * Next create a situation where write combining 1412 * or read prefetching could be initiated by the 1413 * CPU or host bridge. Our device does not support 1414 * either, so look for data corruption and/or flagged 1415 * PCI errors. 1416 */ 1417 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE); 1418 while (ahc_is_paused(ahc) == 0) 1419 ; 1420 ahc_outb(ahc, SEQCTL, PERRORDIS); 1421 ahc_outb(ahc, SCBPTR, 0); 1422 ahc_outl(ahc, SCB_BASE, 0x5aa555aa); 1423 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa) 1424 goto fail; 1425 1426 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1427 PCI_COMMAND_STATUS_REG + 1); 1428 if ((status1 & STA) != 0) 1429 goto fail; 1430 1431 error = 0; 1432 1433 fail: 1434 /* Silently clear any latched errors. */ 1435 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1436 PCI_COMMAND_STATUS_REG + 1); 1437 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1438 status1, /*bytes*/1); 1439 ahc_outb(ahc, CLRINT, CLRPARERR); 1440 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1441 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 1442 return (error); 1443 } 1444 #endif 1445 1446 static void 1447 ahc_pci_intr(struct ahc_softc *ahc) 1448 { 1449 u_int error; 1450 u_int status1; 1451 1452 error = ahc_inb(ahc, ERROR); 1453 if ((error & PCIERRSTAT) == 0) 1454 return; 1455 1456 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1457 PCI_COMMAND_STATUS_REG); 1458 1459 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1460 ahc_name(ahc), 1461 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1462 1463 if (status1 & DPE) { 1464 printf("%s: Data Parity Error Detected during address " 1465 "or write data phase\n", ahc_name(ahc)); 1466 } 1467 if (status1 & SSE) { 1468 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1469 } 1470 if (status1 & RMA) { 1471 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1472 } 1473 if (status1 & RTA) { 1474 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1475 } 1476 if (status1 & STA) { 1477 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1478 } 1479 if (status1 & DPR) { 1480 printf("%s: Data Parity Error has been reported via PERR#\n", 1481 ahc_name(ahc)); 1482 } 1483 1484 /* Clear latched errors. */ 1485 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG, 1486 status1); 1487 1488 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1489 printf("%s: Latched PCIERR interrupt with " 1490 "no status bits set\n", ahc_name(ahc)); 1491 } else { 1492 ahc_outb(ahc, CLRINT, CLRPARERR); 1493 } 1494 1495 ahc_unpause(ahc); 1496 } 1497 1498 static int 1499 ahc_aic785X_setup(struct ahc_softc *ahc) 1500 { 1501 uint8_t rev; 1502 1503 ahc->channel = 'A'; 1504 ahc->chip = AHC_AIC7850; 1505 ahc->features = AHC_AIC7850_FE; 1506 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1507 rev = PCI_REVISION(ahc->bd->class); 1508 if (rev >= 1) 1509 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1510 return (0); 1511 } 1512 1513 static int 1514 ahc_aic7860_setup(struct ahc_softc *ahc) 1515 { 1516 uint8_t rev; 1517 1518 ahc->channel = 'A'; 1519 ahc->chip = AHC_AIC7860; 1520 ahc->features = AHC_AIC7860_FE; 1521 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1522 rev = PCI_REVISION(ahc->bd->class); 1523 if (rev >= 1) 1524 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1525 return (0); 1526 } 1527 1528 static int 1529 ahc_apa1480_setup(struct ahc_softc *ahc) 1530 { 1531 int error; 1532 1533 error = ahc_aic7860_setup(ahc); 1534 if (error != 0) 1535 return (error); 1536 ahc->features |= AHC_REMOVABLE; 1537 return (0); 1538 } 1539 1540 static int 1541 ahc_aic7870_setup(struct ahc_softc *ahc) 1542 { 1543 1544 ahc->channel = 'A'; 1545 ahc->chip = AHC_AIC7870; 1546 ahc->features = AHC_AIC7870_FE; 1547 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1548 return (0); 1549 } 1550 1551 static int 1552 ahc_aha394X_setup(struct ahc_softc *ahc) 1553 { 1554 int error; 1555 1556 error = ahc_aic7870_setup(ahc); 1557 if (error == 0) 1558 error = ahc_aha394XX_setup(ahc); 1559 return (error); 1560 } 1561 1562 static int 1563 ahc_aha398X_setup(struct ahc_softc *ahc) 1564 { 1565 int error; 1566 1567 error = ahc_aic7870_setup(ahc); 1568 if (error == 0) 1569 error = ahc_aha398XX_setup(ahc); 1570 return (error); 1571 } 1572 1573 static int 1574 ahc_aha494X_setup(struct ahc_softc *ahc) 1575 { 1576 int error; 1577 1578 error = ahc_aic7870_setup(ahc); 1579 if (error == 0) 1580 error = ahc_aha494XX_setup(ahc); 1581 return (error); 1582 } 1583 1584 static int 1585 ahc_aic7880_setup(struct ahc_softc *ahc) 1586 { 1587 uint8_t rev; 1588 1589 ahc->channel = 'A'; 1590 ahc->chip = AHC_AIC7880; 1591 ahc->features = AHC_AIC7880_FE; 1592 ahc->bugs |= AHC_TMODE_WIDEODD_BUG; 1593 rev = PCI_REVISION(ahc->bd->class); 1594 if (rev >= 1) { 1595 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1596 } else { 1597 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1598 } 1599 return (0); 1600 } 1601 1602 static int 1603 ahc_aha2940Pro_setup(struct ahc_softc *ahc) 1604 { 1605 1606 ahc->flags |= AHC_INT50_SPEEDFLEX; 1607 return (ahc_aic7880_setup(ahc)); 1608 } 1609 1610 static int 1611 ahc_aha394XU_setup(struct ahc_softc *ahc) 1612 { 1613 int error; 1614 1615 error = ahc_aic7880_setup(ahc); 1616 if (error == 0) 1617 error = ahc_aha394XX_setup(ahc); 1618 return (error); 1619 } 1620 1621 static int 1622 ahc_aha398XU_setup(struct ahc_softc *ahc) 1623 { 1624 int error; 1625 1626 error = ahc_aic7880_setup(ahc); 1627 if (error == 0) 1628 error = ahc_aha398XX_setup(ahc); 1629 return (error); 1630 } 1631 1632 static int 1633 ahc_aic7890_setup(struct ahc_softc *ahc) 1634 { 1635 uint8_t rev; 1636 1637 ahc->channel = 'A'; 1638 ahc->chip = AHC_AIC7890; 1639 ahc->features = AHC_AIC7890_FE; 1640 ahc->flags |= AHC_NEWEEPROM_FMT; 1641 rev = PCI_REVISION(ahc->bd->class); 1642 if (rev == 0) 1643 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 1644 return (0); 1645 } 1646 1647 static int 1648 ahc_aic7892_setup(struct ahc_softc *ahc) 1649 { 1650 1651 ahc->channel = 'A'; 1652 ahc->chip = AHC_AIC7892; 1653 ahc->features = AHC_AIC7892_FE; 1654 ahc->flags |= AHC_NEWEEPROM_FMT; 1655 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1656 return (0); 1657 } 1658 1659 static int 1660 ahc_aic7895_setup(struct ahc_softc *ahc) 1661 { 1662 uint8_t rev; 1663 1664 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1665 /* 1666 * The 'C' revision of the aic7895 has a few additional features. 1667 */ 1668 rev = PCI_REVISION(ahc->bd->class); 1669 if (rev >= 4) { 1670 ahc->chip = AHC_AIC7895C; 1671 ahc->features = AHC_AIC7895C_FE; 1672 } else { 1673 u_int command; 1674 1675 ahc->chip = AHC_AIC7895; 1676 ahc->features = AHC_AIC7895_FE; 1677 1678 /* 1679 * The BIOS disables the use of MWI transactions 1680 * since it does not have the MWI bug work around 1681 * we have. Disabling MWI reduces performance, so 1682 * turn it on again. 1683 */ 1684 command = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1685 PCI_COMMAND_STATUS_REG); 1686 command |= PCI_COMMAND_INVALIDATE_ENABLE; 1687 pci_conf_write(ahc->bd->pc, ahc->bd->tag, 1688 PCI_COMMAND_STATUS_REG, command); 1689 ahc->bugs |= AHC_PCI_MWI_BUG; 1690 } 1691 /* 1692 * XXX Does CACHETHEN really not work??? What about PCI retry? 1693 * on C level chips. Need to test, but for now, play it safe. 1694 */ 1695 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 1696 | AHC_CACHETHEN_BUG; 1697 1698 #if 0 1699 uint32_t devconfig; 1700 1701 /* 1702 * Cachesize must also be zero due to stray DAC 1703 * problem when sitting behind some bridges. 1704 */ 1705 pci_conf_write(ahc->bd->pc, ahc->bd->tag, CSIZE_LATTIME, 0); 1706 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1707 devconfig |= MRDCEN; 1708 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig); 1709 #endif 1710 ahc->flags |= AHC_NEWEEPROM_FMT; 1711 return (0); 1712 } 1713 1714 static int 1715 ahc_aic7896_setup(struct ahc_softc *ahc) 1716 { 1717 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1718 ahc->chip = AHC_AIC7896; 1719 ahc->features = AHC_AIC7896_FE; 1720 ahc->flags |= AHC_NEWEEPROM_FMT; 1721 ahc->bugs |= AHC_CACHETHEN_DIS_BUG; 1722 return (0); 1723 } 1724 1725 static int 1726 ahc_aic7899_setup(struct ahc_softc *ahc) 1727 { 1728 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1729 ahc->chip = AHC_AIC7899; 1730 ahc->features = AHC_AIC7899_FE; 1731 ahc->flags |= AHC_NEWEEPROM_FMT; 1732 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1733 return (0); 1734 } 1735 1736 static int 1737 ahc_aha29160C_setup(struct ahc_softc *ahc) 1738 { 1739 int error; 1740 1741 error = ahc_aic7899_setup(ahc); 1742 if (error != 0) 1743 return (error); 1744 ahc->features |= AHC_REMOVABLE; 1745 return (0); 1746 } 1747 1748 static int 1749 ahc_raid_setup(struct ahc_softc *ahc) 1750 { 1751 aprint_normal_dev(&ahc->sc_dev, "RAID functionality unsupported\n"); 1752 return (ENXIO); 1753 } 1754 1755 static int 1756 ahc_aha394XX_setup(struct ahc_softc *ahc) 1757 { 1758 1759 switch (ahc->bd->dev) { 1760 case AHC_394X_SLOT_CHANNEL_A: 1761 ahc->channel = 'A'; 1762 break; 1763 case AHC_394X_SLOT_CHANNEL_B: 1764 ahc->channel = 'B'; 1765 break; 1766 default: 1767 printf("adapter at unexpected slot %d\n" 1768 "unable to map to a channel\n", 1769 ahc->bd->dev); 1770 ahc->channel = 'A'; 1771 } 1772 return (0); 1773 } 1774 1775 static int 1776 ahc_aha398XX_setup(struct ahc_softc *ahc) 1777 { 1778 1779 switch (ahc->bd->dev) { 1780 case AHC_398X_SLOT_CHANNEL_A: 1781 ahc->channel = 'A'; 1782 break; 1783 case AHC_398X_SLOT_CHANNEL_B: 1784 ahc->channel = 'B'; 1785 break; 1786 case AHC_398X_SLOT_CHANNEL_C: 1787 ahc->channel = 'C'; 1788 break; 1789 default: 1790 printf("adapter at unexpected slot %d\n" 1791 "unable to map to a channel\n", 1792 ahc->bd->dev); 1793 ahc->channel = 'A'; 1794 break; 1795 } 1796 ahc->flags |= AHC_LARGE_SEEPROM; 1797 return (0); 1798 } 1799 1800 static int 1801 ahc_aha494XX_setup(struct ahc_softc *ahc) 1802 { 1803 1804 switch (ahc->bd->dev) { 1805 case AHC_494X_SLOT_CHANNEL_A: 1806 ahc->channel = 'A'; 1807 break; 1808 case AHC_494X_SLOT_CHANNEL_B: 1809 ahc->channel = 'B'; 1810 break; 1811 case AHC_494X_SLOT_CHANNEL_C: 1812 ahc->channel = 'C'; 1813 break; 1814 case AHC_494X_SLOT_CHANNEL_D: 1815 ahc->channel = 'D'; 1816 break; 1817 default: 1818 printf("adapter at unexpected slot %d\n" 1819 "unable to map to a channel\n", 1820 ahc->bd->dev); 1821 ahc->channel = 'A'; 1822 } 1823 ahc->flags |= AHC_LARGE_SEEPROM; 1824 return (0); 1825 } 1826
Indexes created Wed Oct 01 19:09:53 GMT 2025