ahc_pci.c revision 1.7
1 /* $NetBSD: ahc_pci.c,v 1.7 1996/10/10 19:55:48 christos Exp $ */ 2 3 /* 4 * Product specific probe and attach routines for: 5 * 3940, 2940, aic7880, aic7870, aic7860 and aic7850 SCSI controllers 6 * 7 * Copyright (c) 1995, 1996 Justin T. Gibbs. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice immediately at the beginning of the file, without modification, 15 * this list of conditions, and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from Id: aic7870.c,v 1.37 1996/06/08 06:55:55 gibbs Exp 35 */ 36 37 #if defined(__FreeBSD__) 38 #include <pci.h> 39 #endif 40 #if NPCI > 0 || defined(__NetBSD__) 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/queue.h> 46 #if defined(__NetBSD__) 47 #include <sys/device.h> 48 #include <machine/bus.h> 49 #include <machine/intr.h> 50 #endif /* defined(__NetBSD__) */ 51 52 #include <scsi/scsi_all.h> 53 #include <scsi/scsiconf.h> 54 55 #if defined(__FreeBSD__) 56 57 #include <pci/pcireg.h> 58 #include <pci/pcivar.h> 59 60 #include <machine/clock.h> 61 62 #include <i386/scsi/aic7xxx.h> 63 #include <i386/scsi/93cx6.h> 64 65 #include <dev/aic7xxx/aic7xxx_reg.h> 66 67 #define PCI_BASEADR0 PCI_MAP_REG_START 68 69 #elif defined(__NetBSD__) 70 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 74 #include <dev/ic/aic7xxxreg.h> 75 #include <dev/ic/aic7xxxvar.h> 76 #include <dev/ic/smc93cx6var.h> 77 78 /* 79 * Under normal circumstances, these messages are unnecessary 80 * and not terribly cosmetic. 81 */ 82 #ifdef DEBUG 83 #define bootverbose 1 84 #else 85 #define bootverbose 0 86 #endif 87 88 #define PCI_BASEADR0 PCI_MAPREG_START 89 90 #endif /* defined(__NetBSD__) */ 91 92 #define PCI_DEVICE_ID_ADAPTEC_3940U 0x82789004ul 93 #define PCI_DEVICE_ID_ADAPTEC_2944U 0x84789004ul 94 #define PCI_DEVICE_ID_ADAPTEC_2940U 0x81789004ul 95 #define PCI_DEVICE_ID_ADAPTEC_2940AU 0x61789004ul 96 #define PCI_DEVICE_ID_ADAPTEC_3940 0x72789004ul 97 #define PCI_DEVICE_ID_ADAPTEC_2944 0x74789004ul 98 #define PCI_DEVICE_ID_ADAPTEC_2940 0x71789004ul 99 #define PCI_DEVICE_ID_ADAPTEC_AIC7880 0x80789004ul 100 #define PCI_DEVICE_ID_ADAPTEC_AIC7870 0x70789004ul 101 #define PCI_DEVICE_ID_ADAPTEC_AIC7860 0x60789004ul 102 #define PCI_DEVICE_ID_ADAPTEC_AIC7855 0x55789004ul 103 #define PCI_DEVICE_ID_ADAPTEC_AIC7850 0x50789004ul 104 105 #define DEVCONFIG 0x40 106 #define MPORTMODE 0x00000400ul /* aic7870 only */ 107 #define RAMPSM 0x00000200ul /* aic7870 only */ 108 #define VOLSENSE 0x00000100ul 109 #define SCBRAMSEL 0x00000080ul 110 #define MRDCEN 0x00000040ul 111 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 112 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 113 #define BERREN 0x00000008ul 114 #define DACEN 0x00000004ul 115 #define STPWLEVEL 0x00000002ul 116 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 117 118 #define CSIZE_LATTIME 0x0c 119 #define CACHESIZE 0x0000003ful /* only 5 bits */ 120 #define LATTIME 0x0000ff00ul 121 122 /* 123 * Define the format of the aic78X0 SEEPROM registers (16 bits). 124 * 125 */ 126 127 struct seeprom_config { 128 129 /* 130 * SCSI ID Configuration Flags 131 */ 132 #define CFXFER 0x0007 /* synchronous transfer rate */ 133 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 134 #define CFDISC 0x0010 /* enable disconnection */ 135 #define CFWIDEB 0x0020 /* wide bus device */ 136 /* UNUSED 0x00C0 */ 137 #define CFSTART 0x0100 /* send start unit SCSI command */ 138 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 139 #define CFRNFOUND 0x0400 /* report even if not found */ 140 /* UNUSED 0xf800 */ 141 u_int16_t device_flags[16]; /* words 0-15 */ 142 143 /* 144 * BIOS Control Bits 145 */ 146 #define CFSUPREM 0x0001 /* support all removeable drives */ 147 #define CFSUPREMB 0x0002 /* support removeable drives for boot only */ 148 #define CFBIOSEN 0x0004 /* BIOS enabled */ 149 /* UNUSED 0x0008 */ 150 #define CFSM2DRV 0x0010 /* support more than two drives */ 151 /* UNUSED 0x0060 */ 152 #define CFEXTEND 0x0080 /* extended translation enabled */ 153 /* UNUSED 0xff00 */ 154 u_int16_t bios_control; /* word 16 */ 155 156 /* 157 * Host Adapter Control Bits 158 */ 159 /* UNUSED 0x0001 */ 160 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable (Ultra cards) */ 161 #define CFSTERM 0x0004 /* SCSI low byte termination (non-wide cards) */ 162 #define CFWSTERM 0x0008 /* SCSI high byte termination (wide card) */ 163 #define CFSPARITY 0x0010 /* SCSI parity */ 164 /* UNUSED 0x0020 */ 165 #define CFRESETB 0x0040 /* reset SCSI bus at IC initialization */ 166 /* UNUSED 0xff80 */ 167 u_int16_t adapter_control; /* word 17 */ 168 169 /* 170 * Bus Release, Host Adapter ID 171 */ 172 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 173 /* UNUSED 0x00f0 */ 174 #define CFBRTIME 0xff00 /* bus release time */ 175 u_int16_t brtime_id; /* word 18 */ 176 177 /* 178 * Maximum targets 179 */ 180 #define CFMAXTARG 0x00ff /* maximum targets */ 181 /* UNUSED 0xff00 */ 182 u_int16_t max_targets; /* word 19 */ 183 184 u_int16_t res_1[11]; /* words 20-30 */ 185 u_int16_t checksum; /* word 31 */ 186 }; 187 188 static void load_seeprom __P((struct ahc_data *ahc)); 189 static int acquire_seeprom __P((struct seeprom_descriptor *sd)); 190 static void release_seeprom __P((struct seeprom_descriptor *sd)); 191 192 static u_char aic3940_count; 193 194 #if defined(__FreeBSD__) 195 196 static char* aic7870_probe __P((pcici_t tag, pcidi_t type)); 197 static void aic7870_attach __P((pcici_t config_id, int unit)); 198 199 static struct pci_device ahc_pci_driver = { 200 "ahc", 201 aic7870_probe, 202 aic7870_attach, 203 &ahc_unit, 204 NULL 205 }; 206 207 DATA_SET (pcidevice_set, ahc_pci_driver); 208 209 static char* 210 aic7870_probe (pcici_t tag, pcidi_t type) 211 { 212 switch(type) { 213 case PCI_DEVICE_ID_ADAPTEC_3940U: 214 return ("Adaptec 3940 Ultra SCSI host adapter"); 215 break; 216 case PCI_DEVICE_ID_ADAPTEC_3940: 217 return ("Adaptec 3940 SCSI host adapter"); 218 break; 219 case PCI_DEVICE_ID_ADAPTEC_2944U: 220 return ("Adaptec 2944 Ultra SCSI host adapter"); 221 break; 222 case PCI_DEVICE_ID_ADAPTEC_2940U: 223 return ("Adaptec 2940 Ultra SCSI host adapter"); 224 break; 225 case PCI_DEVICE_ID_ADAPTEC_2944: 226 return ("Adaptec 2944 SCSI host adapter"); 227 break; 228 case PCI_DEVICE_ID_ADAPTEC_2940: 229 return ("Adaptec 2940 SCSI host adapter"); 230 break; 231 case PCI_DEVICE_ID_ADAPTEC_2940AU: 232 return ("Adaptec 2940A Ultra SCSI host adapter"); 233 break; 234 case PCI_DEVICE_ID_ADAPTEC_AIC7880: 235 return ("Adaptec aic7880 Ultra SCSI host adapter"); 236 break; 237 case PCI_DEVICE_ID_ADAPTEC_AIC7870: 238 return ("Adaptec aic7870 SCSI host adapter"); 239 break; 240 case PCI_DEVICE_ID_ADAPTEC_AIC7860: 241 return ("Adaptec aic7860 SCSI host adapter"); 242 break; 243 case PCI_DEVICE_ID_ADAPTEC_AIC7855: 244 return ("Adaptec aic7855 SCSI host adapter"); 245 break; 246 case PCI_DEVICE_ID_ADAPTEC_AIC7850: 247 return ("Adaptec aic7850 SCSI host adapter"); 248 break; 249 default: 250 break; 251 } 252 return (0); 253 254 } 255 256 #elif defined(__NetBSD__) 257 258 int ahc_pci_probe __P((struct device *, void *, void *)); 259 void ahc_pci_attach __P((struct device *, struct device *, void *)); 260 261 struct cfattach ahc_pci_ca = { 262 sizeof(struct ahc_data), ahc_pci_probe, ahc_pci_attach 263 }; 264 265 int 266 ahc_pci_probe(parent, match, aux) 267 struct device *parent; 268 void *match, *aux; 269 { 270 struct pci_attach_args *pa = aux; 271 272 switch (pa->pa_id) { 273 case PCI_DEVICE_ID_ADAPTEC_3940U: 274 case PCI_DEVICE_ID_ADAPTEC_2944U: 275 case PCI_DEVICE_ID_ADAPTEC_2940U: 276 case PCI_DEVICE_ID_ADAPTEC_2940AU: 277 case PCI_DEVICE_ID_ADAPTEC_3940: 278 case PCI_DEVICE_ID_ADAPTEC_2944: 279 case PCI_DEVICE_ID_ADAPTEC_2940: 280 case PCI_DEVICE_ID_ADAPTEC_AIC7880: 281 case PCI_DEVICE_ID_ADAPTEC_AIC7870: 282 case PCI_DEVICE_ID_ADAPTEC_AIC7860: 283 case PCI_DEVICE_ID_ADAPTEC_AIC7855: 284 case PCI_DEVICE_ID_ADAPTEC_AIC7850: 285 return 1; 286 } 287 return 0; 288 } 289 #endif /* defined(__NetBSD__) */ 290 291 #if defined(__FreeBSD__) 292 static void 293 aic7870_attach(config_id, unit) 294 pcici_t config_id; 295 int unit; 296 #elif defined(__NetBSD__) 297 void 298 ahc_pci_attach(parent, self, aux) 299 struct device *parent, *self; 300 void *aux; 301 #endif 302 { 303 #if defined(__FreeBSD__) 304 u_long io_port; 305 int unit = ahc->sc_dev.dv_unit; 306 #elif defined(__NetBSD__) 307 struct pci_attach_args *pa = aux; 308 struct ahc_data *ahc = (void *)self; 309 bus_io_addr_t iobase; 310 bus_io_size_t iosize; 311 bus_io_handle_t ioh; 312 pci_intr_handle_t ih; 313 const char *intrstr; 314 #endif 315 u_long id; 316 unsigned opri = 0; 317 ahc_type ahc_t = AHC_NONE; 318 ahc_flag ahc_f = AHC_FNONE; 319 #if defined(__FreeBSD__) 320 struct ahc_data *ahc; 321 #endif 322 u_char ultra_enb = 0; 323 u_char our_id = 0; 324 325 #if defined(__FreeBSD__) 326 if(!(io_port = pci_conf_read(config_id, PCI_BASEADR0))) 327 return; 328 /* 329 * The first bit of PCI_BASEADR0 is always 330 * set hence we mask it off. 331 */ 332 io_port &= 0xfffffffe; 333 #elif defined(__NetBSD__) 334 if (pci_io_find(pa->pa_pc, pa->pa_tag, PCI_BASEADR0, &iobase, &iosize)) 335 return; 336 if (bus_io_map(pa->pa_bc, iobase, iosize, &ioh)) 337 return; 338 #endif 339 340 #if defined(__FreeBSD__) 341 switch ((id = pci_conf_read(config_id, PCI_ID_REG))) { 342 #elif defined(__NetBSD__) 343 switch (id = pa->pa_id) { 344 #endif 345 case PCI_DEVICE_ID_ADAPTEC_3940U: 346 case PCI_DEVICE_ID_ADAPTEC_3940: 347 if (id == PCI_DEVICE_ID_ADAPTEC_3940U) 348 ahc_t = AHC_394U; 349 else 350 ahc_t = AHC_394; 351 aic3940_count++; 352 if(!(aic3940_count & 0x01)) 353 /* Even count implies second channel */ 354 ahc_f |= AHC_CHNLB; 355 break; 356 case PCI_DEVICE_ID_ADAPTEC_2944U: 357 case PCI_DEVICE_ID_ADAPTEC_2940U: 358 ahc_t = AHC_294U; 359 break; 360 case PCI_DEVICE_ID_ADAPTEC_2944: 361 case PCI_DEVICE_ID_ADAPTEC_2940: 362 ahc_t = AHC_294; 363 break; 364 case PCI_DEVICE_ID_ADAPTEC_2940AU: 365 ahc_t = AHC_294AU; 366 break; 367 case PCI_DEVICE_ID_ADAPTEC_AIC7880: 368 ahc_t = AHC_AIC7880; 369 break; 370 case PCI_DEVICE_ID_ADAPTEC_AIC7870: 371 ahc_t = AHC_AIC7870; 372 break; 373 case PCI_DEVICE_ID_ADAPTEC_AIC7860: 374 ahc_t = AHC_AIC7860; 375 break; 376 case PCI_DEVICE_ID_ADAPTEC_AIC7855: 377 case PCI_DEVICE_ID_ADAPTEC_AIC7850: 378 ahc_t = AHC_AIC7850; 379 break; 380 default: 381 break; 382 } 383 384 /* On all PCI adapters, we allow SCB paging */ 385 ahc_f |= AHC_PAGESCBS; 386 387 /* Remeber how the card was setup in case there is no SEEPROM */ 388 #if defined(__FreeBSD__) 389 our_id = inb(SCSIID + io_port) & OID; 390 if(ahc_t & AHC_ULTRA) 391 ultra_enb = inb(SXFRCTL0 + io_port) & ULTRAEN; 392 #else 393 our_id = bus_io_read_1(pa->pa_bc, ioh, SCSIID) & OID; 394 if(ahc_t & AHC_ULTRA) 395 ultra_enb = bus_io_read_1(pa->pa_bc, ioh, SXFRCTL0) & ULTRAEN; 396 #endif 397 398 #if defined(__FreeBSD__) 399 ahc_reset(io_port); 400 #elif defined(__NetBSD__) 401 kprintf("\n"); 402 ahc_reset(ahc->sc_dev.dv_xname, pa->pa_bc, ioh); 403 #endif 404 405 if(ahc_t & AHC_AIC7870){ 406 #if defined(__FreeBSD__) 407 u_long devconfig = pci_conf_read(config_id, DEVCONFIG); 408 #elif defined(__NetBSD__) 409 u_long devconfig = 410 pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 411 #endif 412 413 if(devconfig & (RAMPSM)) { 414 /* 415 * External SRAM present. Have the probe walk 416 * the SCBs to see how much SRAM we have and set 417 * the number of SCBs accordingly. We have to 418 * turn off SCBRAMSEL to access the external 419 * SCB SRAM. 420 * 421 * It seems that early versions of the aic7870 422 * didn't use these bits, hence the hack for the 423 * 3940 above. I would guess that recent 3940s 424 * using later aic7870 or aic7880 chips do 425 * actually set RAMPSM. 426 * 427 * The documentation isn't clear, but it sounds 428 * like the value written to devconfig must not 429 * have RAMPSM set. The second sixteen bits of 430 * the register are R/O anyway, so it shouldn't 431 * affect RAMPSM either way. 432 */ 433 devconfig &= ~(RAMPSM|SCBRAMSEL); 434 #if defined(__FreeBSD__) 435 pci_conf_write(config_id, DEVCONFIG, devconfig); 436 #elif defined(__NetBSD__) 437 pci_conf_write(pa->pa_pc, pa->pa_tag, 438 DEVCONFIG, devconfig); 439 #endif 440 } 441 } 442 443 #if defined(__FreeBSD__) 444 if(!(ahc = ahc_alloc(unit, io_port, ahc_t, ahc_f))) 445 return; /* XXX PCI code should take return status */ 446 447 if(!(pci_map_int(config_id, ahc_intr, (void *)ahc, &bio_imask))) { 448 ahc_free(ahc); 449 return; 450 } 451 #elif defined(__NetBSD__) 452 ahc_construct(ahc, pa->pa_bc, ioh, ahc_t, ahc_f); 453 454 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 455 pa->pa_intrline, &ih)) { 456 kprintf("%s: couldn't map interrupt\n", ahc->sc_dev.dv_xname); 457 ahc_free(ahc); 458 return; 459 } 460 intrstr = pci_intr_string(pa->pa_pc, ih); 461 #if defined(__OpenBSD__) 462 ahc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahc_intr, ahc, 463 ahc->sc_dev.dv_xname); 464 #else 465 ahc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahc_intr, ahc); 466 #endif 467 if (ahc->sc_ih == NULL) { 468 kprintf("%s: couldn't establish interrupt", 469 ahc->sc_dev.dv_xname); 470 if (intrstr != NULL) 471 kprintf(" at %s", intrstr); 472 kprintf("\n"); 473 ahc_free(ahc); 474 return; 475 } 476 if (intrstr != NULL) 477 kprintf("%s: interrupting at %s\n", ahc->sc_dev.dv_xname, 478 intrstr); 479 #endif 480 /* 481 * Protect ourself from spurrious interrupts during 482 * intialization. 483 */ 484 opri = splbio(); 485 486 /* 487 * Do aic7870/aic7880/aic7850 specific initialization 488 */ 489 { 490 u_char sblkctl; 491 char *id_string; 492 493 switch(ahc->type) { 494 case AHC_394U: 495 case AHC_294U: 496 case AHC_AIC7880: 497 { 498 id_string = "aic7880 "; 499 load_seeprom(ahc); 500 break; 501 } 502 case AHC_394: 503 case AHC_294: 504 case AHC_AIC7870: 505 { 506 id_string = "aic7870 "; 507 load_seeprom(ahc); 508 break; 509 } 510 case AHC_294AU: 511 case AHC_AIC7860: 512 { 513 id_string = "aic7860 "; 514 load_seeprom(ahc); 515 break; 516 } 517 case AHC_AIC7850: 518 { 519 id_string = "aic7850 "; 520 /* 521 * Use defaults, if the chip wasn't initialized by 522 * a BIOS. 523 */ 524 ahc->flags |= AHC_USEDEFAULTS; 525 break; 526 } 527 default: 528 { 529 kprintf("ahc: Unknown controller type. Ignoring.\n"); 530 ahc_free(ahc); 531 splx(opri); 532 return; 533 } 534 } 535 536 /* 537 * Take the LED out of diagnostic mode 538 */ 539 sblkctl = AHC_INB(ahc, SBLKCTL); 540 AHC_OUTB(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 541 542 /* 543 * I don't know where this is set in the SEEPROM or by the 544 * BIOS, so we default to 100%. 545 */ 546 AHC_OUTB(ahc, DSPCISTATUS, DFTHRSH_100); 547 548 if(ahc->flags & AHC_USEDEFAULTS) { 549 /* 550 * PCI Adapter default setup 551 * Should only be used if the adapter does not have 552 * an SEEPROM. 553 */ 554 /* See if someone else set us up already */ 555 u_long i; 556 for(i = TARG_SCRATCH; i < 0x60; i++) { 557 if(AHC_INB(ahc, i) != 0x00) 558 break; 559 } 560 if(i == TARG_SCRATCH) { 561 /* 562 * Try looking for all ones. You can get 563 * either. 564 */ 565 for (i = TARG_SCRATCH; i < 0x60; i++) { 566 if(AHC_INB(ahc, i) != 0xff) 567 break; 568 } 569 } 570 if((i != 0x60) && (our_id != 0)) { 571 kprintf("%s: Using left over BIOS settings\n", 572 ahc_name(ahc)); 573 ahc->flags &= ~AHC_USEDEFAULTS; 574 } 575 else 576 our_id = 0x07; 577 AHC_OUTB(ahc, SCSICONF, 578 (our_id & 0x07)|ENSPCHK|RESET_SCSI); 579 /* In case we are a wide card */ 580 AHC_OUTB(ahc, SCSICONF + 1, our_id); 581 582 if(!ultra_enb || (ahc->flags & AHC_USEDEFAULTS)) { 583 /* 584 * If there wasn't a BIOS or the board 585 * wasn't in this mode to begin with, 586 * turn off ultra. 587 */ 588 ahc->type &= ~AHC_ULTRA; 589 } 590 } 591 592 kprintf("%s: %s", ahc_name(ahc), id_string); 593 } 594 595 if(ahc_init(ahc)){ 596 ahc_free(ahc); 597 splx(opri); 598 return; /* XXX PCI code should take return status */ 599 } 600 splx(opri); 601 602 ahc_attach(ahc); 603 } 604 605 /* 606 * Read the SEEPROM. Return 0 on failure 607 */ 608 void 609 load_seeprom(ahc) 610 struct ahc_data *ahc; 611 { 612 struct seeprom_descriptor sd; 613 struct seeprom_config sc; 614 u_short *scarray = (u_short *)≻ 615 u_short checksum = 0; 616 u_char scsi_conf; 617 u_char host_id; 618 int have_seeprom; 619 620 #if defined(__FreeBSD__) 621 sd.sd_iobase = ahc->baseport + SEECTL; 622 #elif defined(__NetBSD__) 623 sd.sd_bc = ahc->sc_bc; 624 sd.sd_ioh = ahc->sc_ioh; 625 sd.sd_offset = SEECTL; 626 #endif 627 sd.sd_MS = SEEMS; 628 sd.sd_RDY = SEERDY; 629 sd.sd_CS = SEECS; 630 sd.sd_CK = SEECK; 631 sd.sd_DO = SEEDO; 632 sd.sd_DI = SEEDI; 633 634 if(bootverbose) 635 kprintf("%s: Reading SEEPROM...", ahc_name(ahc)); 636 have_seeprom = acquire_seeprom(&sd); 637 if (have_seeprom) { 638 have_seeprom = read_seeprom(&sd, 639 (u_int16_t *)&sc, 640 ahc->flags & AHC_CHNLB, 641 sizeof(sc)/2); 642 release_seeprom(&sd); 643 if (have_seeprom) { 644 /* Check checksum */ 645 int i; 646 647 for (i = 0;i < (sizeof(sc)/2 - 1);i = i + 1) 648 checksum = checksum + scarray[i]; 649 if (checksum != sc.checksum) { 650 if(bootverbose) 651 kprintf ("checksum error"); 652 have_seeprom = 0; 653 } 654 else if(bootverbose) 655 kprintf("done.\n"); 656 } 657 } 658 if (!have_seeprom) { 659 if(bootverbose) 660 kprintf("\n%s: No SEEPROM availible\n", ahc_name(ahc)); 661 ahc->flags |= AHC_USEDEFAULTS; 662 } 663 else { 664 /* 665 * Put the data we've collected down into SRAM 666 * where ahc_init will find it. 667 */ 668 int i; 669 int max_targ = sc.max_targets & CFMAXTARG; 670 671 for(i = 0; i < max_targ; i++){ 672 u_char target_settings; 673 target_settings = (sc.device_flags[i] & CFXFER) << 4; 674 if (sc.device_flags[i] & CFSYNCH) 675 target_settings |= SOFS; 676 if (sc.device_flags[i] & CFWIDEB) 677 target_settings |= WIDEXFER; 678 if (sc.device_flags[i] & CFDISC) 679 ahc->discenable |= (0x01 << i); 680 AHC_OUTB(ahc, TARG_SCRATCH+i, target_settings); 681 } 682 AHC_OUTB(ahc, DISC_DSB, ~(ahc->discenable & 0xff)); 683 AHC_OUTB(ahc, DISC_DSB + 1, ~((ahc->discenable >> 8) & 0xff)); 684 685 host_id = sc.brtime_id & CFSCSIID; 686 687 scsi_conf = (host_id & 0x7); 688 if(sc.adapter_control & CFSPARITY) 689 scsi_conf |= ENSPCHK; 690 if(sc.adapter_control & CFRESETB) 691 scsi_conf |= RESET_SCSI; 692 693 if(ahc->type & AHC_ULTRA) { 694 /* Should we enable Ultra mode? */ 695 if(!(sc.adapter_control & CFULTRAEN)) 696 /* Treat us as a non-ultra card */ 697 ahc->type &= ~AHC_ULTRA; 698 } 699 /* Set the host ID */ 700 AHC_OUTB(ahc, SCSICONF, scsi_conf); 701 /* In case we are a wide card */ 702 AHC_OUTB(ahc, SCSICONF + 1, host_id); 703 } 704 } 705 706 static int 707 acquire_seeprom(sd) 708 struct seeprom_descriptor *sd; 709 { 710 int wait; 711 712 /* 713 * Request access of the memory port. When access is 714 * granted, SEERDY will go high. We use a 1 second 715 * timeout which should be near 1 second more than 716 * is needed. Reason: after the chip reset, there 717 * should be no contention. 718 */ 719 SEEPROM_OUTB(sd, sd->sd_MS); 720 wait = 1000; /* 1 second timeout in msec */ 721 while (--wait && ((SEEPROM_INB(sd) & sd->sd_RDY) == 0)) { 722 DELAY (1000); /* delay 1 msec */ 723 } 724 if ((SEEPROM_INB(sd) & sd->sd_RDY) == 0) { 725 SEEPROM_OUTB(sd, 0); 726 return (0); 727 } 728 return(1); 729 } 730 731 static void 732 release_seeprom(sd) 733 struct seeprom_descriptor *sd; 734 { 735 /* Release access to the memory port and the serial EEPROM. */ 736 SEEPROM_OUTB(sd, 0); 737 } 738 739 #endif /* NPCI > 0 */ 740
Indexes created Wed Oct 01 19:09:53 GMT 2025