ahd_pci.c revision 1.13.6.1
1 /* $NetBSD: ahd_pci.c,v 1.13.6.1 2005/05/13 18:36:28 riz Exp $ */ 2 3 /* 4 * Product specific probe and attach routines for: 5 * aic7901 and aic7902 SCSI controllers 6 * 7 * Copyright (c) 1994-2001 Justin T. Gibbs. 8 * Copyright (c) 2000-2002 Adaptec Inc. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * substantially similar to the "NO WARRANTY" disclaimer below 19 * ("Disclaimer") and any redistribution must be conditioned upon 20 * including a substantially similar Disclaimer requirement for further 21 * binary redistribution. 22 * 3. Neither the names of the above-listed copyright holders nor the names 23 * of any contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * Alternatively, this software may be distributed under the terms of the 27 * GNU General Public License ("GPL") version 2 as published by the Free 28 * Software Foundation. 29 * 30 * NO WARRANTY 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGES. 42 * 43 * Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#80 $ 44 * 45 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx_pci.c,v 1.16 2003/06/28 04:39:49 gibbs Exp $ 46 */ 47 /* 48 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: ahd_pci.c,v 1.13.6.1 2005/05/13 18:36:28 riz Exp $"); 53 54 #define AHD_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 55 #define AHD_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 56 57 #include <dev/ic/aic79xx_osm.h> 58 #include <dev/ic/aic79xx_inline.h> 59 60 static __inline uint64_t 61 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 62 { 63 uint64_t id; 64 65 id = subvendor 66 | (subdevice << 16) 67 | ((uint64_t)vendor << 32) 68 | ((uint64_t)device << 48); 69 70 return (id); 71 } 72 73 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 74 #define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull 75 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 76 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 77 #define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull 78 79 #define ID_AIC7901 0x800F9005FFFF9005ull 80 #define ID_AHA_29320A 0x8000900500609005ull 81 #define ID_AHA_29320ALP 0x8017900500449005ull 82 83 #define ID_AIC7901A 0x801E9005FFFF9005ull 84 #define ID_AHA_29320LP 0x8014900500449005ull 85 86 #define ID_AIC7902 0x801F9005FFFF9005ull 87 #define ID_AIC7902_B 0x801D9005FFFF9005ull 88 #define ID_AHA_39320 0x8010900500409005ull 89 #define ID_AHA_29320 0x8012900500429005ull 90 #define ID_AHA_29320B 0x8013900500439005ull 91 #define ID_AHA_39320_B 0x8015900500409005ull 92 #define ID_AHA_39320A 0x8016900500409005ull 93 #define ID_AHA_39320D 0x8011900500419005ull 94 #define ID_AHA_39320D_B 0x801C900500419005ull 95 #define ID_AHA_39320_B_DELL 0x8015900501681028ull 96 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull 97 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 98 #define ID_AIC7902_PCI_REV_A4 0x3 99 #define ID_AIC7902_PCI_REV_B0 0x10 100 #define SUBID_HP 0x0E11 101 102 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80) 103 104 #define DEVID_9005_TYPE(id) ((id) & 0xF) 105 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 106 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 107 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 108 109 #define DEVID_9005_MFUNC(id) ((id) & 0x10) 110 111 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 112 113 #define SUBID_9005_TYPE(id) ((id) & 0xF) 114 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 115 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 116 117 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 118 119 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 120 121 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 122 #define SUBID_9005_SEEPTYPE_NONE 0x0 123 #define SUBID_9005_SEEPTYPE_4K 0x1 124 125 static ahd_device_setup_t ahd_aic7901_setup; 126 static ahd_device_setup_t ahd_aic7901A_setup; 127 static ahd_device_setup_t ahd_aic7902_setup; 128 static ahd_device_setup_t ahd_aic790X_setup; 129 130 struct ahd_pci_identity ahd_pci_ident_table [] = 131 { 132 /* aic7901 based controllers */ 133 { 134 ID_AHA_29320A, 135 ID_ALL_MASK, 136 "Adaptec 29320A Ultra320 SCSI adapter", 137 ahd_aic7901_setup 138 }, 139 { 140 ID_AHA_29320ALP, 141 ID_ALL_MASK, 142 "Adaptec 29320ALP Ultra320 SCSI adapter", 143 ahd_aic7901_setup 144 }, 145 /* aic7901A based controllers */ 146 { 147 ID_AHA_29320LP, 148 ID_ALL_MASK, 149 "Adaptec 29320LP Ultra320 SCSI adapter", 150 ahd_aic7901A_setup 151 }, 152 /* aic7902 based controllers */ 153 { 154 ID_AHA_39320, 155 ID_ALL_MASK, 156 "Adaptec 39320 Ultra320 SCSI adapter", 157 ahd_aic7902_setup 158 }, 159 { 160 ID_AHA_39320_B, 161 ID_ALL_MASK, 162 "Adaptec 39320 Ultra320 SCSI adapter", 163 ahd_aic7902_setup 164 }, 165 { 166 ID_AHA_39320_B_DELL, 167 ID_ALL_IROC_MASK, 168 "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter", 169 ahd_aic7902_setup 170 }, 171 { 172 ID_AHA_39320A, 173 ID_ALL_MASK, 174 "Adaptec 39320A Ultra320 SCSI adapter", 175 ahd_aic7902_setup 176 }, 177 { 178 ID_AHA_39320D, 179 ID_ALL_MASK, 180 "Adaptec 39320D Ultra320 SCSI adapter", 181 ahd_aic7902_setup 182 }, 183 { 184 ID_AHA_39320D_HP, 185 ID_ALL_MASK, 186 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 187 ahd_aic7902_setup 188 }, 189 { 190 ID_AHA_39320D_B, 191 ID_ALL_MASK, 192 "Adaptec 39320D Ultra320 SCSI adapter", 193 ahd_aic7902_setup 194 }, 195 { 196 ID_AHA_39320D_B_HP, 197 ID_ALL_MASK, 198 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 199 ahd_aic7902_setup 200 }, 201 /* Generic chip probes for devices we don't know 'exactly' */ 202 { 203 ID_AIC7901 & ID_9005_GENERIC_MASK, 204 ID_9005_GENERIC_MASK, 205 "Adaptec AIC7901 Ultra320 SCSI adapter", 206 ahd_aic7901_setup 207 }, 208 { 209 ID_AIC7901A & ID_DEV_VENDOR_MASK, 210 ID_DEV_VENDOR_MASK, 211 "Adaptec AIC7901A Ultra320 SCSI adapter", 212 ahd_aic7901A_setup 213 }, 214 { 215 ID_AIC7902 & ID_9005_GENERIC_MASK, 216 ID_9005_GENERIC_MASK, 217 "Adaptec AIC7902 Ultra320 SCSI adapter", 218 ahd_aic7902_setup 219 } 220 }; 221 222 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 223 224 #define DEVCONFIG 0x40 225 #define PCIXINITPAT 0x0000E000ul 226 #define PCIXINIT_PCI33_66 0x0000E000ul 227 #define PCIXINIT_PCIX50_66 0x0000C000ul 228 #define PCIXINIT_PCIX66_100 0x0000A000ul 229 #define PCIXINIT_PCIX100_133 0x00008000ul 230 #define PCI_BUS_MODES_INDEX(devconfig) \ 231 (((devconfig) & PCIXINITPAT) >> 13) 232 233 static const char *pci_bus_modes[] = 234 { 235 "PCI bus mode unknown", 236 "PCI bus mode unknown", 237 "PCI bus mode unknown", 238 "PCI bus mode unknown", 239 "PCI-X 101-133Mhz", 240 "PCI-X 67-100Mhz", 241 "PCI-X 50-66Mhz", 242 "PCI 33 or 66Mhz" 243 }; 244 245 #define TESTMODE 0x00000800ul 246 #define IRDY_RST 0x00000200ul 247 #define FRAME_RST 0x00000100ul 248 #define PCI64BIT 0x00000080ul 249 #define MRDCEN 0x00000040ul 250 #define ENDIANSEL 0x00000020ul 251 #define MIXQWENDIANEN 0x00000008ul 252 #define DACEN 0x00000004ul 253 #define STPWLEVEL 0x00000002ul 254 #define QWENDIANSEL 0x00000001ul 255 256 #define DEVCONFIG1 0x44 257 #define PREQDIS 0x01 258 259 #define LATTIME 0x0000ff00ul 260 261 int ahd_pci_probe __P((struct device *, struct cfdata *, void *)); 262 void ahd_pci_attach __P((struct device *, struct device *, void *)); 263 264 CFATTACH_DECL(ahd_pci, sizeof(struct ahd_softc), 265 ahd_pci_probe, ahd_pci_attach, NULL, NULL); 266 267 static int ahd_check_extport(struct ahd_softc *ahd); 268 static void ahd_configure_termination(struct ahd_softc *ahd, 269 u_int adapter_control); 270 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 271 272 const struct ahd_pci_identity * 273 ahd_find_pci_device(id, subid) 274 pcireg_t id, subid; 275 { 276 u_int64_t full_id; 277 const struct ahd_pci_identity *entry; 278 u_int i; 279 280 full_id = ahd_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 281 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 282 283 for (i = 0; i < ahd_num_pci_devs; i++) { 284 entry = &ahd_pci_ident_table[i]; 285 if (entry->full_id == (full_id & entry->id_mask)) 286 return (entry); 287 } 288 return (NULL); 289 } 290 291 int 292 ahd_pci_probe(parent, match, aux) 293 struct device *parent; 294 struct cfdata *match; 295 void *aux; 296 { 297 struct pci_attach_args *pa = aux; 298 const struct ahd_pci_identity *entry; 299 pcireg_t subid; 300 301 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 302 entry = ahd_find_pci_device(pa->pa_id, subid); 303 return entry != NULL ? 1 : 0; 304 } 305 306 void 307 ahd_pci_attach(parent, self, aux) 308 struct device *parent, *self; 309 void *aux; 310 { 311 struct pci_attach_args *pa = aux; 312 struct ahd_softc *ahd = (void *)self; 313 314 const struct ahd_pci_identity *entry; 315 316 uint32_t devconfig; 317 pcireg_t command; 318 int error; 319 pcireg_t subid; 320 uint16_t subvendor; 321 int pci_pwrmgmt_cap_reg; 322 int pci_pwrmgmt_csr_reg; 323 pcireg_t reg; 324 int ioh_valid, ioh2_valid, memh_valid; 325 pcireg_t memtype; 326 pci_intr_handle_t ih; 327 const char *intrstr; 328 struct ahd_pci_busdata *bd; 329 330 ahd_set_name(ahd, ahd->sc_dev.dv_xname); 331 ahd->parent_dmat = pa->pa_dmat; 332 333 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 334 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 335 entry = ahd_find_pci_device(pa->pa_id, subid); 336 if (entry == NULL) 337 return; 338 339 /* Keep information about the PCI bus */ 340 bd = malloc(sizeof (struct ahd_pci_busdata), M_DEVBUF, M_NOWAIT); 341 if (bd == NULL) { 342 aprint_error("%s: unable to allocate bus-specific data\n", ahd_name(ahd)); 343 return; 344 } 345 memset(bd, 0, sizeof(struct ahd_pci_busdata)); 346 347 bd->pc = pa->pa_pc; 348 bd->tag = pa->pa_tag; 349 bd->func = pa->pa_function; 350 bd->dev = pa->pa_device; 351 352 ahd->bus_data = bd; 353 354 ahd->description = entry->name; 355 356 ahd->seep_config = malloc(sizeof(*ahd->seep_config), 357 M_DEVBUF, M_NOWAIT); 358 if (ahd->seep_config == NULL) { 359 aprint_error("%s: cannot malloc seep_config!\n", ahd_name(ahd)); 360 return; 361 } 362 memset(ahd->seep_config, 0, sizeof(*ahd->seep_config)); 363 364 LIST_INIT(&ahd->pending_scbs); 365 ahd_timer_init(&ahd->reset_timer); 366 ahd_timer_init(&ahd->stat_timer); 367 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A 368 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A; 369 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT; 370 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT; 371 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT; 372 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT; 373 ahd->int_coalescing_stop_threshold = AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT; 374 375 if (ahd_platform_alloc(ahd, NULL) != 0) { 376 ahd_free(ahd); 377 return; 378 } 379 380 /* 381 * Record if this is an HP board. 382 */ 383 subvendor = PCI_VENDOR(subid); 384 if (subvendor == SUBID_HP) 385 ahd->flags |= AHD_HP_BOARD; 386 387 error = entry->setup(ahd, pa); 388 if (error != 0) 389 return; 390 391 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 392 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 393 ahd->chip |= AHD_PCI; 394 /* Disable PCIX workarounds when running in PCI mode. */ 395 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 396 } else { 397 ahd->chip |= AHD_PCIX; 398 } 399 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 400 401 memh_valid = ioh_valid = ioh2_valid = 0; 402 403 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 404 &bd->pcix_off, NULL)) { 405 if (ahd->chip & AHD_PCIX) 406 aprint_error("%s: warning: can't find PCI-X capability\n", 407 ahd->sc_dev.dv_xname); 408 ahd->chip &= ~AHD_PCIX; 409 ahd->chip |= AHD_PCI; 410 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 411 } 412 413 /* 414 * Map PCI Registers 415 */ 416 if ((ahd->bugs & AHD_PCIX_MMAPIO_BUG) == 0) { 417 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 418 AHD_PCI_MEMADDR); 419 switch (memtype) { 420 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 421 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 422 memh_valid = (pci_mapreg_map(pa, AHD_PCI_MEMADDR, 423 memtype, 0, &ahd->tags[0], 424 &ahd->bshs[0], 425 NULL, NULL) == 0); 426 if (memh_valid) { 427 ahd->tags[1] = ahd->tags[0]; 428 bus_space_subregion(ahd->tags[0], ahd->bshs[0], 429 /*offset*/0x100, 430 /*size*/0x100, 431 &ahd->bshs[1]); 432 if (ahd_pci_test_register_access(ahd) != 0) 433 memh_valid = 0; 434 } 435 break; 436 default: 437 memh_valid = 0; 438 aprint_error("%s: unknown memory type: 0x%x\n", 439 ahd_name(ahd), memtype); 440 break; 441 } 442 443 if (memh_valid) { 444 command &= ~PCI_COMMAND_IO_ENABLE; 445 pci_conf_write(pa->pa_pc, pa->pa_tag, 446 PCI_COMMAND_STATUS_REG, command); 447 } 448 #ifdef AHD_DEBUG 449 printf("%s: doing memory mapping tag0 0x%x, tag1 0x%x, " 450 "shs0 0x%lx, shs1 0x%lx\n", 451 ahd_name(ahd), ahd->tags[0], ahd->tags[1], 452 ahd->bshs[0], ahd->bshs[1]); 453 #endif 454 } 455 456 if (command & PCI_COMMAND_IO_ENABLE) { 457 /* First BAR */ 458 ioh_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR, 459 PCI_MAPREG_TYPE_IO, 0, 460 &ahd->tags[0], &ahd->bshs[0], 461 NULL, NULL) == 0); 462 463 /* 2nd BAR */ 464 ioh2_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR1, 465 PCI_MAPREG_TYPE_IO, 0, 466 &ahd->tags[1], &ahd->bshs[1], 467 NULL, NULL) == 0); 468 469 if (ioh_valid && ioh2_valid) { 470 KASSERT(memh_valid == 0); 471 command &= ~PCI_COMMAND_MEM_ENABLE; 472 pci_conf_write(pa->pa_pc, pa->pa_tag, 473 PCI_COMMAND_STATUS_REG, command); 474 } 475 #ifdef AHD_DEBUG 476 printf("%s: doing io mapping tag0 0x%x, tag1 0x%x, " 477 "shs0 0x%lx, shs1 0x%lx\n", ahd_name(ahd), ahd->tags[0], 478 ahd->tags[1], ahd->bshs[0], ahd->bshs[1]); 479 #endif 480 481 } 482 483 if (memh_valid == 0 && (ioh_valid == 0 || ioh2_valid == 0)) { 484 aprint_error("%s: unable to map registers\n", ahd_name(ahd)); 485 return; 486 } 487 488 aprint_normal("\n"); 489 aprint_naive("\n"); 490 491 /* 492 * Set Power State D0. 493 */ 494 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 495 &pci_pwrmgmt_cap_reg, 0)) { 496 497 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 498 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 499 pci_pwrmgmt_csr_reg); 500 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 501 pci_conf_write(pa->pa_pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 502 (reg & ~PCI_PMCSR_STATE_MASK) | 503 PCI_PMCSR_STATE_D0); 504 } 505 } 506 507 /* 508 * Should we bother disabling 39Bit addressing 509 * based on installed memory? 510 */ 511 if (sizeof(bus_addr_t) > 4) 512 ahd->flags |= AHD_39BIT_ADDRESSING; 513 514 /* 515 * If we need to support high memory, enable dual 516 * address cycles. This bit must be set to enable 517 * high address bit generation even if we are on a 518 * 64bit bus (PCI64BIT set in devconfig). 519 */ 520 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 521 uint32_t devconfig; 522 523 aprint_normal("%s: Enabling 39Bit Addressing\n", ahd_name(ahd)); 524 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 525 devconfig |= DACEN; 526 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); 527 } 528 529 /* Ensure busmastering is enabled */ 530 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 531 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 532 reg | PCI_COMMAND_MASTER_ENABLE); 533 534 ahd_softc_init(ahd); 535 536 /* 537 * Map the interrupt routines 538 */ 539 ahd->bus_intr = ahd_pci_intr; 540 541 error = ahd_reset(ahd, /*reinit*/FALSE); 542 if (error != 0) { 543 ahd_free(ahd); 544 return; 545 } 546 547 if (pci_intr_map(pa, &ih)) { 548 aprint_error("%s: couldn't map interrupt\n", ahd_name(ahd)); 549 ahd_free(ahd); 550 return; 551 } 552 intrstr = pci_intr_string(pa->pa_pc, ih); 553 ahd->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahd_intr, ahd); 554 if (ahd->ih == NULL) { 555 aprint_error("%s: couldn't establish interrupt", 556 ahd_name(ahd)); 557 if (intrstr != NULL) 558 aprint_error(" at %s", intrstr); 559 aprint_error("\n"); 560 ahd_free(ahd); 561 return; 562 } 563 if (intrstr != NULL) 564 aprint_normal("%s: interrupting at %s\n", ahd_name(ahd), 565 intrstr); 566 567 /* Get the size of the cache */ 568 ahd->pci_cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 569 ahd->pci_cachesize *= 4; 570 571 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 572 /* See if we have a SEEPROM and perform auto-term */ 573 error = ahd_check_extport(ahd); 574 if (error != 0) 575 return; 576 577 /* Core initialization */ 578 error = ahd_init(ahd); 579 if (error != 0) 580 return; 581 582 /* 583 * Link this softc in with all other ahd instances. 584 */ 585 ahd_attach(ahd); 586 } 587 588 /* 589 * Perform some simple tests that should catch situations where 590 * our registers are invalidly mapped. 591 */ 592 int 593 ahd_pci_test_register_access(struct ahd_softc *ahd) 594 { 595 uint32_t cmd; 596 struct ahd_pci_busdata *bd = ahd->bus_data; 597 u_int targpcistat; 598 uint32_t pci_status1; 599 int error; 600 uint8_t hcntrl; 601 602 error = EIO; 603 604 /* 605 * Enable PCI error interrupt status, but suppress NMIs 606 * generated by SERR raised due to target aborts. 607 */ 608 cmd = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 609 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 610 cmd & ~PCI_COMMAND_SERR_ENABLE); 611 612 /* 613 * First a simple test to see if any 614 * registers can be read. Reading 615 * HCNTRL has no side effects and has 616 * at least one bit that is guaranteed to 617 * be zero so it is a good register to 618 * use for this test. 619 */ 620 hcntrl = ahd_inb(ahd, HCNTRL); 621 if (hcntrl == 0xFF) 622 goto fail; 623 624 /* 625 * Next create a situation where write combining 626 * or read prefetching could be initiated by the 627 * CPU or host bridge. Our device does not support 628 * either, so look for data corruption and/or flaged 629 * PCI errors. First pause without causing another 630 * chip reset. 631 */ 632 hcntrl &= ~CHIPRST; 633 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 634 while (ahd_is_paused(ahd) == 0) 635 ; 636 637 /* Clear any PCI errors that occurred before our driver attached. */ 638 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 639 targpcistat = ahd_inb(ahd, TARGPCISTAT); 640 ahd_outb(ahd, TARGPCISTAT, targpcistat); 641 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 642 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, pci_status1); 643 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 644 ahd_outb(ahd, CLRINT, CLRPCIINT); 645 646 ahd_outb(ahd, SEQCTL0, PERRORDIS); 647 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 648 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 649 goto fail; 650 651 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 652 u_int targpcistat; 653 654 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 655 targpcistat = ahd_inb(ahd, TARGPCISTAT); 656 if ((targpcistat & STA) != 0) 657 goto fail; 658 } 659 660 error = 0; 661 662 fail: 663 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 664 665 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 666 targpcistat = ahd_inb(ahd, TARGPCISTAT); 667 668 /* Silently clear any latched errors. */ 669 ahd_outb(ahd, TARGPCISTAT, targpcistat); 670 pci_status1 = pci_conf_read(bd->pc, bd->tag, 671 PCI_COMMAND_STATUS_REG); 672 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 673 pci_status1); 674 ahd_outb(ahd, CLRINT, CLRPCIINT); 675 } 676 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 677 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, cmd); 678 return (error); 679 } 680 681 /* 682 * Check the external port logic for a serial eeprom 683 * and termination/cable detection contrls. 684 */ 685 static int 686 ahd_check_extport(struct ahd_softc *ahd) 687 { 688 struct vpd_config vpd; 689 struct seeprom_config *sc; 690 u_int adapter_control; 691 int have_seeprom; 692 int error; 693 694 sc = ahd->seep_config; 695 have_seeprom = ahd_acquire_seeprom(ahd); 696 if (have_seeprom) { 697 u_int start_addr; 698 699 /* 700 * Fetch VPD for this function and parse it. 701 */ 702 #ifdef AHD_DEBUG 703 printf("%s: Reading VPD from SEEPROM...", 704 ahd_name(ahd)); 705 #endif 706 /* Address is always in units of 16bit words */ 707 start_addr = ((2 * sizeof(*sc)) 708 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 709 710 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 711 start_addr, sizeof(vpd)/2, 712 /*bytestream*/TRUE); 713 if (error == 0) 714 error = ahd_parse_vpddata(ahd, &vpd); 715 #ifdef AHD_DEBUG 716 printf("%s: VPD parsing %s\n", 717 ahd_name(ahd), 718 error == 0 ? "successful" : "failed"); 719 #endif 720 721 #ifdef AHD_DEBUG 722 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 723 #endif 724 725 /* Address is always in units of 16bit words */ 726 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 727 728 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 729 start_addr, sizeof(*sc)/2, 730 /*bytestream*/FALSE); 731 732 if (error != 0) { 733 #ifdef AHD_DEBUG 734 printf("Unable to read SEEPROM\n"); 735 #endif 736 have_seeprom = 0; 737 } else { 738 have_seeprom = ahd_verify_cksum(sc); 739 #ifdef AHD_DEBUG 740 if (have_seeprom == 0) 741 printf ("checksum error\n"); 742 else 743 printf ("done.\n"); 744 #endif 745 } 746 ahd_release_seeprom(ahd); 747 } 748 749 if (!have_seeprom) { 750 u_int nvram_scb; 751 752 /* 753 * Pull scratch ram settings and treat them as 754 * if they are the contents of an seeprom if 755 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 756 * in SCB 0xFF. We manually compose the data as 16bit 757 * values to avoid endian issues. 758 */ 759 ahd_set_scbptr(ahd, 0xFF); 760 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 761 if (nvram_scb != 0xFF 762 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 763 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 764 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 765 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 766 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 767 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 768 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 769 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 770 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 771 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 772 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 773 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 774 uint16_t *sc_data; 775 int i; 776 777 ahd_set_scbptr(ahd, nvram_scb); 778 sc_data = (uint16_t *)sc; 779 for (i = 0; i < 64; i += 2) 780 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 781 have_seeprom = ahd_verify_cksum(sc); 782 if (have_seeprom) 783 ahd->flags |= AHD_SCB_CONFIG_USED; 784 } 785 } 786 787 #ifdef AHD_DEBUG 788 if ((have_seeprom != 0) && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 789 uint16_t *sc_data; 790 int i; 791 792 printf("%s: Seeprom Contents:", ahd_name(ahd)); 793 sc_data = (uint16_t *)sc; 794 for (i = 0; i < (sizeof(*sc)); i += 2) 795 printf("\n\t0x%.4x", sc_data[i]); 796 printf("\n"); 797 } 798 #endif 799 800 if (!have_seeprom) { 801 aprint_error("%s: No SEEPROM available.\n", ahd_name(ahd)); 802 ahd->flags |= AHD_USEDEFAULTS; 803 error = ahd_default_config(ahd); 804 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 805 free(ahd->seep_config, M_DEVBUF); 806 ahd->seep_config = NULL; 807 } else { 808 error = ahd_parse_cfgdata(ahd, sc); 809 adapter_control = sc->adapter_control; 810 } 811 if (error != 0) 812 return (error); 813 814 ahd_configure_termination(ahd, adapter_control); 815 816 return (0); 817 } 818 819 static void 820 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 821 { 822 int error; 823 u_int sxfrctl1; 824 uint8_t termctl; 825 uint32_t devconfig; 826 struct ahd_pci_busdata *bd = ahd->bus_data; 827 828 devconfig = pci_conf_read(bd->pc, bd->tag, DEVCONFIG); 829 devconfig &= ~STPWLEVEL; 830 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 831 devconfig |= STPWLEVEL; 832 #ifdef AHD_DEBUG 833 printf("%s: STPWLEVEL is %s\n", 834 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 835 #endif 836 pci_conf_write(bd->pc, bd->tag, DEVCONFIG, devconfig); 837 838 /* Make sure current sensing is off. */ 839 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 840 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 841 } 842 843 /* 844 * Read to sense. Write to set. 845 */ 846 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 847 if ((adapter_control & CFAUTOTERM) == 0) { 848 if (bootverbose) 849 printf("%s: Manual Primary Termination\n", 850 ahd_name(ahd)); 851 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 852 if ((adapter_control & CFSTERM) != 0) 853 termctl |= FLX_TERMCTL_ENPRILOW; 854 if ((adapter_control & CFWSTERM) != 0) 855 termctl |= FLX_TERMCTL_ENPRIHIGH; 856 } else if (error != 0) { 857 if (bootverbose) 858 printf("%s: Primary Auto-Term Sensing failed! " 859 "Using Defaults.\n", ahd_name(ahd)); 860 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 861 } 862 863 if ((adapter_control & CFSEAUTOTERM) == 0) { 864 if (bootverbose) 865 printf("%s: Manual Secondary Termination\n", 866 ahd_name(ahd)); 867 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 868 if ((adapter_control & CFSELOWTERM) != 0) 869 termctl |= FLX_TERMCTL_ENSECLOW; 870 if ((adapter_control & CFSEHIGHTERM) != 0) 871 termctl |= FLX_TERMCTL_ENSECHIGH; 872 } else if (error != 0) { 873 if (bootverbose) 874 printf("%s: Secondary Auto-Term Sensing failed! " 875 "Using Defaults.\n", ahd_name(ahd)); 876 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 877 } 878 879 /* 880 * Now set the termination based on what we found. 881 */ 882 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 883 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 884 ahd->flags |= AHD_TERM_ENB_A; 885 sxfrctl1 |= STPWEN; 886 } 887 /* Must set the latch once in order to be effective. */ 888 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 889 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 890 891 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 892 if (error != 0) { 893 aprint_error("%s: Unable to set termination settings!\n", 894 ahd_name(ahd)); 895 } else { 896 if (bootverbose) { 897 printf("%s: Primary High byte termination %sabled\n", 898 ahd_name(ahd), 899 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 900 901 printf("%s: Primary Low byte termination %sabled\n", 902 ahd_name(ahd), 903 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 904 905 printf("%s: Secondary High byte termination %sabled\n", 906 ahd_name(ahd), 907 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 908 909 printf("%s: Secondary Low byte termination %sabled\n", 910 ahd_name(ahd), 911 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 912 } 913 } 914 return; 915 } 916 917 #define DPE 0x80 918 #define SSE 0x40 919 #define RMA 0x20 920 #define RTA 0x10 921 #define STA 0x08 922 #define DPR 0x01 923 924 static const char *split_status_source[] = 925 { 926 "DFF0", 927 "DFF1", 928 "OVLY", 929 "CMC", 930 }; 931 932 static const char *pci_status_source[] = 933 { 934 "DFF0", 935 "DFF1", 936 "SG", 937 "CMC", 938 "OVLY", 939 "NONE", 940 "MSI", 941 "TARG" 942 }; 943 944 static const char *split_status_strings[] = 945 { 946 "%s: Received split response in %s.\n", 947 "%s: Received split completion error message in %s\n", 948 "%s: Receive overrun in %s\n", 949 "%s: Count not complete in %s\n", 950 "%s: Split completion data bucket in %s\n", 951 "%s: Split completion address error in %s\n", 952 "%s: Split completion byte count error in %s\n", 953 "%s: Signaled Target-abort to early terminate a split in %s\n" 954 }; 955 956 static const char *pci_status_strings[] = 957 { 958 "%s: Data Parity Error has been reported via PERR# in %s\n", 959 "%s: Target initial wait state error in %s\n", 960 "%s: Split completion read data parity error in %s\n", 961 "%s: Split completion address attribute parity error in %s\n", 962 "%s: Received a Target Abort in %s\n", 963 "%s: Received a Master Abort in %s\n", 964 "%s: Signal System Error Detected in %s\n", 965 "%s: Address or Write Phase Parity Error Detected in %s.\n" 966 }; 967 968 int 969 ahd_pci_intr(struct ahd_softc *ahd) 970 { 971 uint8_t pci_status[8]; 972 ahd_mode_state saved_modes; 973 u_int pci_status1; 974 u_int intstat; 975 u_int i; 976 u_int reg; 977 struct ahd_pci_busdata *bd = ahd->bus_data; 978 979 intstat = ahd_inb(ahd, INTSTAT); 980 981 if ((intstat & SPLTINT) != 0) 982 ahd_pci_split_intr(ahd, intstat); 983 984 if ((intstat & PCIINT) == 0) 985 return 0; 986 987 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 988 saved_modes = ahd_save_modes(ahd); 989 ahd_dump_card_state(ahd); 990 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 991 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 992 993 if (i == 5) 994 continue; 995 pci_status[i] = ahd_inb(ahd, reg); 996 /* Clear latched errors. So our interrupt deasserts. */ 997 ahd_outb(ahd, reg, pci_status[i]); 998 } 999 1000 for (i = 0; i < 8; i++) { 1001 u_int bit; 1002 1003 if (i == 5) 1004 continue; 1005 1006 for (bit = 0; bit < 8; bit++) { 1007 1008 if ((pci_status[i] & (0x1 << bit)) != 0) { 1009 static const char *s; 1010 1011 s = pci_status_strings[bit]; 1012 if (i == 7/*TARG*/ && bit == 3) 1013 s = "%s: Signaled Target Abort\n"; 1014 printf(s, ahd_name(ahd), pci_status_source[i]); 1015 } 1016 } 1017 } 1018 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 1019 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG , pci_status1); 1020 1021 ahd_restore_modes(ahd, saved_modes); 1022 ahd_outb(ahd, CLRINT, CLRPCIINT); 1023 ahd_unpause(ahd); 1024 1025 return 1; 1026 } 1027 1028 static void 1029 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 1030 { 1031 uint8_t split_status[4]; 1032 uint8_t split_status1[4]; 1033 uint8_t sg_split_status[2]; 1034 uint8_t sg_split_status1[2]; 1035 ahd_mode_state saved_modes; 1036 u_int i; 1037 pcireg_t pcix_status; 1038 struct ahd_pci_busdata *bd = ahd->bus_data; 1039 1040 /* 1041 * Check for splits in all modes. Modes 0 and 1 1042 * additionally have SG engine splits to look at. 1043 */ 1044 pcix_status = pci_conf_read(bd->pc, bd->tag, 1045 bd->pcix_off + PCI_PCIX_STATUS); 1046 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 1047 ahd_name(ahd), pcix_status); 1048 1049 saved_modes = ahd_save_modes(ahd); 1050 for (i = 0; i < 4; i++) { 1051 ahd_set_modes(ahd, i, i); 1052 1053 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 1054 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 1055 /* Clear latched errors. So our interrupt deasserts. */ 1056 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 1057 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 1058 if (i > 1) 1059 continue; 1060 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 1061 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 1062 /* Clear latched errors. So our interrupt deasserts. */ 1063 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 1064 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 1065 } 1066 1067 for (i = 0; i < 4; i++) { 1068 u_int bit; 1069 1070 for (bit = 0; bit < 8; bit++) { 1071 1072 if ((split_status[i] & (0x1 << bit)) != 0) { 1073 static const char *s; 1074 1075 s = split_status_strings[bit]; 1076 printf(s, ahd_name(ahd), 1077 split_status_source[i]); 1078 } 1079 1080 if (i > 0) 1081 continue; 1082 1083 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 1084 static const char *s; 1085 1086 s = split_status_strings[bit]; 1087 printf(s, ahd_name(ahd), "SG"); 1088 } 1089 } 1090 } 1091 /* 1092 * Clear PCI-X status bits. 1093 */ 1094 pci_conf_write(bd->pc, bd->tag, bd->pcix_off + PCI_PCIX_STATUS, 1095 pcix_status); 1096 ahd_outb(ahd, CLRINT, CLRSPLTINT); 1097 ahd_restore_modes(ahd, saved_modes); 1098 } 1099 1100 static int 1101 ahd_aic7901_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1102 { 1103 1104 ahd->chip = AHD_AIC7901; 1105 ahd->features = AHD_AIC7901_FE; 1106 return (ahd_aic790X_setup(ahd, pa)); 1107 } 1108 1109 static int 1110 ahd_aic7901A_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1111 { 1112 1113 ahd->chip = AHD_AIC7901A; 1114 ahd->features = AHD_AIC7901A_FE; 1115 return (ahd_aic790X_setup(ahd, pa)); 1116 } 1117 1118 static int 1119 ahd_aic7902_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1120 { 1121 1122 ahd->chip = AHD_AIC7902; 1123 ahd->features = AHD_AIC7902_FE; 1124 return (ahd_aic790X_setup(ahd, pa)); 1125 } 1126 1127 static int 1128 ahd_aic790X_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1129 { 1130 u_int rev; 1131 1132 rev = PCI_REVISION(pa->pa_class); 1133 #ifdef AHD_DEBUG 1134 printf("\n%s: aic7902 chip revision 0x%x\n", ahd_name(ahd), rev); 1135 #endif 1136 if (rev < ID_AIC7902_PCI_REV_A4) { 1137 aprint_error("%s: Unable to attach to unsupported chip revision %d\n", 1138 ahd_name(ahd), rev); 1139 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 0); 1140 return (ENXIO); 1141 } 1142 1143 ahd->channel = (pa->pa_function == 1) ? 'B' : 'A'; 1144 if (rev < ID_AIC7902_PCI_REV_B0) { 1145 /* 1146 * Enable A series workarounds. 1147 */ 1148 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 1149 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 1150 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 1151 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 1152 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 1153 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 1154 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 1155 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 1156 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 1157 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 1158 | AHD_FAINT_LED_BUG; 1159 1160 1161 /* 1162 * IO Cell parameter setup. 1163 */ 1164 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1165 1166 if ((ahd->flags & AHD_HP_BOARD) == 0) 1167 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 1168 } else { 1169 u_int devconfig1; 1170 1171 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1172 | AHD_NEW_DFCNTRL_OPTS; 1173 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; 1174 1175 /* 1176 * Some issues have been resolved in the 7901B. 1177 */ 1178 if ((ahd->features & AHD_MULTI_FUNC) != 0) 1179 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG; 1180 1181 /* 1182 * IO Cell parameter setup. 1183 */ 1184 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1185 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1186 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1187 1188 /* 1189 * Set the PREQDIS bit for H2B which disables some workaround 1190 * that doesn't work on regular PCI busses. 1191 * XXX - Find out exactly what this does from the hardware 1192 * folks! 1193 */ 1194 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1195 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG1, devconfig1|PREQDIS); 1196 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1197 } 1198 1199 return (0); 1200 } 1201
Indexes created Thu Oct 02 10:09:58 GMT 2025