ahd_pci.c revision 1.16
1 /* $NetBSD: ahd_pci.c,v 1.16 2005/04/25 22:44:47 bad Exp $ */ 2 3 /* 4 * Product specific probe and attach routines for: 5 * aic7901 and aic7902 SCSI controllers 6 * 7 * Copyright (c) 1994-2001 Justin T. Gibbs. 8 * Copyright (c) 2000-2002 Adaptec Inc. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * substantially similar to the "NO WARRANTY" disclaimer below 19 * ("Disclaimer") and any redistribution must be conditioned upon 20 * including a substantially similar Disclaimer requirement for further 21 * binary redistribution. 22 * 3. Neither the names of the above-listed copyright holders nor the names 23 * of any contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * Alternatively, this software may be distributed under the terms of the 27 * GNU General Public License ("GPL") version 2 as published by the Free 28 * Software Foundation. 29 * 30 * NO WARRANTY 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGES. 42 * 43 * Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#80 $ 44 * 45 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx_pci.c,v 1.16 2003/06/28 04:39:49 gibbs Exp $ 46 */ 47 /* 48 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: ahd_pci.c,v 1.16 2005/04/25 22:44:47 bad Exp $"); 53 54 #define AHD_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 55 #define AHD_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 56 57 #include <dev/ic/aic79xx_osm.h> 58 #include <dev/ic/aic79xx_inline.h> 59 60 static __inline uint64_t 61 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 62 { 63 uint64_t id; 64 65 id = subvendor 66 | (subdevice << 16) 67 | ((uint64_t)vendor << 32) 68 | ((uint64_t)device << 48); 69 70 return (id); 71 } 72 73 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 74 #define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull 75 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 76 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 77 #define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull 78 79 #define ID_AIC7901 0x800F9005FFFF9005ull 80 #define ID_AHA_29320A 0x8000900500609005ull 81 #define ID_AHA_29320ALP 0x8017900500449005ull 82 83 #define ID_AIC7901A 0x801E9005FFFF9005ull 84 #define ID_AHA_29320LP 0x8014900500449005ull 85 86 #define ID_AIC7902 0x801F9005FFFF9005ull 87 #define ID_AIC7902_B 0x801D9005FFFF9005ull 88 #define ID_AHA_39320 0x8010900500409005ull 89 #define ID_AHA_29320 0x8012900500429005ull 90 #define ID_AHA_29320B 0x8013900500439005ull 91 #define ID_AHA_39320_B 0x8015900500409005ull 92 #define ID_AHA_39320A 0x8016900500409005ull 93 #define ID_AHA_39320D 0x8011900500419005ull 94 #define ID_AHA_39320D_B 0x801C900500419005ull 95 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull 96 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 97 #define ID_AIC7902_PCI_REV_A4 0x3 98 #define ID_AIC7902_PCI_REV_B0 0x10 99 #define SUBID_HP 0x0E11 100 101 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80) 102 103 #define DEVID_9005_TYPE(id) ((id) & 0xF) 104 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 105 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 106 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 107 108 #define DEVID_9005_MFUNC(id) ((id) & 0x10) 109 110 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 111 112 #define SUBID_9005_TYPE(id) ((id) & 0xF) 113 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 114 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 115 116 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 117 118 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 119 120 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 121 #define SUBID_9005_SEEPTYPE_NONE 0x0 122 #define SUBID_9005_SEEPTYPE_4K 0x1 123 124 static ahd_device_setup_t ahd_aic7901_setup; 125 static ahd_device_setup_t ahd_aic7901A_setup; 126 static ahd_device_setup_t ahd_aic7902_setup; 127 static ahd_device_setup_t ahd_aic790X_setup; 128 129 struct ahd_pci_identity ahd_pci_ident_table [] = 130 { 131 /* aic7901 based controllers */ 132 { 133 ID_AHA_29320A, 134 ID_ALL_MASK, 135 "Adaptec 29320A Ultra320 SCSI adapter", 136 ahd_aic7901_setup 137 }, 138 { 139 ID_AHA_29320ALP, 140 ID_ALL_MASK, 141 "Adaptec 29320ALP Ultra320 SCSI adapter", 142 ahd_aic7901_setup 143 }, 144 /* aic7901A based controllers */ 145 { 146 ID_AHA_29320LP, 147 ID_ALL_MASK, 148 "Adaptec 29320LP Ultra320 SCSI adapter", 149 ahd_aic7901A_setup 150 }, 151 /* aic7902 based controllers */ 152 { 153 ID_AHA_39320, 154 ID_ALL_MASK, 155 "Adaptec 39320 Ultra320 SCSI adapter", 156 ahd_aic7902_setup 157 }, 158 { 159 ID_AHA_39320_B, 160 ID_ALL_MASK, 161 "Adaptec 39320 Ultra320 SCSI adapter", 162 ahd_aic7902_setup 163 }, 164 { 165 ID_AHA_39320A, 166 ID_ALL_MASK, 167 "Adaptec 39320A Ultra320 SCSI adapter", 168 ahd_aic7902_setup 169 }, 170 { 171 ID_AHA_39320D, 172 ID_ALL_MASK, 173 "Adaptec 39320D Ultra320 SCSI adapter", 174 ahd_aic7902_setup 175 }, 176 { 177 ID_AHA_39320D_HP, 178 ID_ALL_MASK, 179 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 180 ahd_aic7902_setup 181 }, 182 { 183 ID_AHA_39320D_B, 184 ID_ALL_MASK, 185 "Adaptec 39320D Ultra320 SCSI adapter", 186 ahd_aic7902_setup 187 }, 188 { 189 ID_AHA_39320D_B_HP, 190 ID_ALL_MASK, 191 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 192 ahd_aic7902_setup 193 }, 194 /* Generic chip probes for devices we don't know 'exactly' */ 195 { 196 ID_AIC7901 & ID_9005_GENERIC_MASK, 197 ID_9005_GENERIC_MASK, 198 "Adaptec AIC7901 Ultra320 SCSI adapter", 199 ahd_aic7901_setup 200 }, 201 { 202 ID_AIC7901A & ID_DEV_VENDOR_MASK, 203 ID_DEV_VENDOR_MASK, 204 "Adaptec AIC7901A Ultra320 SCSI adapter", 205 ahd_aic7901A_setup 206 }, 207 { 208 ID_AIC7902 & ID_9005_GENERIC_MASK, 209 ID_9005_GENERIC_MASK, 210 "Adaptec AIC7902 Ultra320 SCSI adapter", 211 ahd_aic7902_setup 212 } 213 }; 214 215 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 216 217 #define DEVCONFIG 0x40 218 #define PCIXINITPAT 0x0000E000ul 219 #define PCIXINIT_PCI33_66 0x0000E000ul 220 #define PCIXINIT_PCIX50_66 0x0000C000ul 221 #define PCIXINIT_PCIX66_100 0x0000A000ul 222 #define PCIXINIT_PCIX100_133 0x00008000ul 223 #define PCI_BUS_MODES_INDEX(devconfig) \ 224 (((devconfig) & PCIXINITPAT) >> 13) 225 226 static const char *pci_bus_modes[] = 227 { 228 "PCI bus mode unknown", 229 "PCI bus mode unknown", 230 "PCI bus mode unknown", 231 "PCI bus mode unknown", 232 "PCI-X 101-133Mhz", 233 "PCI-X 67-100Mhz", 234 "PCI-X 50-66Mhz", 235 "PCI 33 or 66Mhz" 236 }; 237 238 #define TESTMODE 0x00000800ul 239 #define IRDY_RST 0x00000200ul 240 #define FRAME_RST 0x00000100ul 241 #define PCI64BIT 0x00000080ul 242 #define MRDCEN 0x00000040ul 243 #define ENDIANSEL 0x00000020ul 244 #define MIXQWENDIANEN 0x00000008ul 245 #define DACEN 0x00000004ul 246 #define STPWLEVEL 0x00000002ul 247 #define QWENDIANSEL 0x00000001ul 248 249 #define DEVCONFIG1 0x44 250 #define PREQDIS 0x01 251 252 #define LATTIME 0x0000ff00ul 253 254 int ahd_pci_probe(struct device *, struct cfdata *, void *); 255 void ahd_pci_attach(struct device *, struct device *, void *); 256 257 CFATTACH_DECL(ahd_pci, sizeof(struct ahd_softc), 258 ahd_pci_probe, ahd_pci_attach, NULL, NULL); 259 260 static int ahd_check_extport(struct ahd_softc *ahd); 261 static void ahd_configure_termination(struct ahd_softc *ahd, 262 u_int adapter_control); 263 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 264 265 const struct ahd_pci_identity * 266 ahd_find_pci_device(id, subid) 267 pcireg_t id, subid; 268 { 269 u_int64_t full_id; 270 const struct ahd_pci_identity *entry; 271 u_int i; 272 273 full_id = ahd_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 274 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 275 276 for (i = 0; i < ahd_num_pci_devs; i++) { 277 entry = &ahd_pci_ident_table[i]; 278 if (entry->full_id == (full_id & entry->id_mask)) 279 return (entry); 280 } 281 return (NULL); 282 } 283 284 int 285 ahd_pci_probe(parent, match, aux) 286 struct device *parent; 287 struct cfdata *match; 288 void *aux; 289 { 290 struct pci_attach_args *pa = aux; 291 const struct ahd_pci_identity *entry; 292 pcireg_t subid; 293 294 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 295 entry = ahd_find_pci_device(pa->pa_id, subid); 296 return entry != NULL ? 1 : 0; 297 } 298 299 void 300 ahd_pci_attach(parent, self, aux) 301 struct device *parent, *self; 302 void *aux; 303 { 304 struct pci_attach_args *pa = aux; 305 struct ahd_softc *ahd = (void *)self; 306 307 const struct ahd_pci_identity *entry; 308 309 uint32_t devconfig; 310 pcireg_t command; 311 int error; 312 pcireg_t subid; 313 uint16_t subvendor; 314 int pci_pwrmgmt_cap_reg; 315 int pci_pwrmgmt_csr_reg; 316 pcireg_t reg; 317 int ioh_valid, ioh2_valid, memh_valid; 318 pcireg_t memtype; 319 pci_intr_handle_t ih; 320 const char *intrstr; 321 struct ahd_pci_busdata *bd; 322 323 ahd_set_name(ahd, ahd->sc_dev.dv_xname); 324 ahd->parent_dmat = pa->pa_dmat; 325 326 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 327 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 328 entry = ahd_find_pci_device(pa->pa_id, subid); 329 if (entry == NULL) 330 return; 331 332 /* Keep information about the PCI bus */ 333 bd = malloc(sizeof (struct ahd_pci_busdata), M_DEVBUF, M_NOWAIT); 334 if (bd == NULL) { 335 aprint_error("%s: unable to allocate bus-specific data\n", ahd_name(ahd)); 336 return; 337 } 338 memset(bd, 0, sizeof(struct ahd_pci_busdata)); 339 340 bd->pc = pa->pa_pc; 341 bd->tag = pa->pa_tag; 342 bd->func = pa->pa_function; 343 bd->dev = pa->pa_device; 344 345 ahd->bus_data = bd; 346 347 ahd->description = entry->name; 348 349 ahd->seep_config = malloc(sizeof(*ahd->seep_config), 350 M_DEVBUF, M_NOWAIT); 351 if (ahd->seep_config == NULL) { 352 aprint_error("%s: cannot malloc seep_config!\n", ahd_name(ahd)); 353 return; 354 } 355 memset(ahd->seep_config, 0, sizeof(*ahd->seep_config)); 356 357 LIST_INIT(&ahd->pending_scbs); 358 ahd_timer_init(&ahd->reset_timer); 359 ahd_timer_init(&ahd->stat_timer); 360 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A 361 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A; 362 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT; 363 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT; 364 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT; 365 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT; 366 ahd->int_coalescing_stop_threshold = AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT; 367 368 if (ahd_platform_alloc(ahd, NULL) != 0) { 369 ahd_free(ahd); 370 return; 371 } 372 373 /* 374 * Record if this is an HP board. 375 */ 376 subvendor = PCI_VENDOR(subid); 377 if (subvendor == SUBID_HP) 378 ahd->flags |= AHD_HP_BOARD; 379 380 error = entry->setup(ahd, pa); 381 if (error != 0) 382 return; 383 384 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 385 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 386 ahd->chip |= AHD_PCI; 387 /* Disable PCIX workarounds when running in PCI mode. */ 388 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 389 } else { 390 ahd->chip |= AHD_PCIX; 391 } 392 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 393 394 memh_valid = ioh_valid = ioh2_valid = 0; 395 396 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 397 &bd->pcix_off, NULL)) { 398 if (ahd->chip & AHD_PCIX) 399 aprint_error("%s: warning: can't find PCI-X capability\n", 400 ahd->sc_dev.dv_xname); 401 ahd->chip &= ~AHD_PCIX; 402 ahd->chip |= AHD_PCI; 403 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 404 } 405 406 /* 407 * Map PCI Registers 408 */ 409 if ((ahd->bugs & AHD_PCIX_MMAPIO_BUG) == 0) { 410 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 411 AHD_PCI_MEMADDR); 412 switch (memtype) { 413 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 414 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 415 memh_valid = (pci_mapreg_map(pa, AHD_PCI_MEMADDR, 416 memtype, 0, &ahd->tags[0], 417 &ahd->bshs[0], 418 NULL, NULL) == 0); 419 if (memh_valid) { 420 ahd->tags[1] = ahd->tags[0]; 421 bus_space_subregion(ahd->tags[0], ahd->bshs[0], 422 /*offset*/0x100, 423 /*size*/0x100, 424 &ahd->bshs[1]); 425 if (ahd_pci_test_register_access(ahd) != 0) 426 memh_valid = 0; 427 } 428 break; 429 default: 430 memh_valid = 0; 431 aprint_error("%s: unknown memory type: 0x%x\n", 432 ahd_name(ahd), memtype); 433 break; 434 } 435 436 if (memh_valid) { 437 command &= ~PCI_COMMAND_IO_ENABLE; 438 pci_conf_write(pa->pa_pc, pa->pa_tag, 439 PCI_COMMAND_STATUS_REG, command); 440 } 441 #ifdef AHD_DEBUG 442 printf("%s: doing memory mapping tag0 0x%x, tag1 0x%x, " 443 "shs0 0x%lx, shs1 0x%lx\n", 444 ahd_name(ahd), ahd->tags[0], ahd->tags[1], 445 ahd->bshs[0], ahd->bshs[1]); 446 #endif 447 } 448 449 if (command & PCI_COMMAND_IO_ENABLE) { 450 /* First BAR */ 451 ioh_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR, 452 PCI_MAPREG_TYPE_IO, 0, 453 &ahd->tags[0], &ahd->bshs[0], 454 NULL, NULL) == 0); 455 456 /* 2nd BAR */ 457 ioh2_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR1, 458 PCI_MAPREG_TYPE_IO, 0, 459 &ahd->tags[1], &ahd->bshs[1], 460 NULL, NULL) == 0); 461 462 if (ioh_valid && ioh2_valid) { 463 KASSERT(memh_valid == 0); 464 command &= ~PCI_COMMAND_MEM_ENABLE; 465 pci_conf_write(pa->pa_pc, pa->pa_tag, 466 PCI_COMMAND_STATUS_REG, command); 467 } 468 #ifdef AHD_DEBUG 469 printf("%s: doing io mapping tag0 0x%x, tag1 0x%x, " 470 "shs0 0x%lx, shs1 0x%lx\n", ahd_name(ahd), ahd->tags[0], 471 ahd->tags[1], ahd->bshs[0], ahd->bshs[1]); 472 #endif 473 474 } 475 476 if (memh_valid == 0 && (ioh_valid == 0 || ioh2_valid == 0)) { 477 aprint_error("%s: unable to map registers\n", ahd_name(ahd)); 478 return; 479 } 480 481 aprint_normal("\n"); 482 aprint_naive("\n"); 483 484 /* 485 * Set Power State D0. 486 */ 487 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 488 &pci_pwrmgmt_cap_reg, 0)) { 489 490 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 491 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 492 pci_pwrmgmt_csr_reg); 493 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 494 pci_conf_write(pa->pa_pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 495 (reg & ~PCI_PMCSR_STATE_MASK) | 496 PCI_PMCSR_STATE_D0); 497 } 498 } 499 500 /* 501 * Should we bother disabling 39Bit addressing 502 * based on installed memory? 503 */ 504 if (sizeof(bus_addr_t) > 4) 505 ahd->flags |= AHD_39BIT_ADDRESSING; 506 507 /* 508 * If we need to support high memory, enable dual 509 * address cycles. This bit must be set to enable 510 * high address bit generation even if we are on a 511 * 64bit bus (PCI64BIT set in devconfig). 512 */ 513 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 514 uint32_t devconfig; 515 516 aprint_normal("%s: Enabling 39Bit Addressing\n", ahd_name(ahd)); 517 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 518 devconfig |= DACEN; 519 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); 520 } 521 522 /* Ensure busmastering is enabled */ 523 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 524 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 525 reg | PCI_COMMAND_MASTER_ENABLE); 526 527 ahd_softc_init(ahd); 528 529 /* 530 * Map the interrupt routines 531 */ 532 ahd->bus_intr = ahd_pci_intr; 533 534 error = ahd_reset(ahd, /*reinit*/FALSE); 535 if (error != 0) { 536 ahd_free(ahd); 537 return; 538 } 539 540 if (pci_intr_map(pa, &ih)) { 541 aprint_error("%s: couldn't map interrupt\n", ahd_name(ahd)); 542 ahd_free(ahd); 543 return; 544 } 545 intrstr = pci_intr_string(pa->pa_pc, ih); 546 ahd->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahd_intr, ahd); 547 if (ahd->ih == NULL) { 548 aprint_error("%s: couldn't establish interrupt", 549 ahd_name(ahd)); 550 if (intrstr != NULL) 551 aprint_error(" at %s", intrstr); 552 aprint_error("\n"); 553 ahd_free(ahd); 554 return; 555 } 556 if (intrstr != NULL) 557 aprint_normal("%s: interrupting at %s\n", ahd_name(ahd), 558 intrstr); 559 560 /* Get the size of the cache */ 561 ahd->pci_cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 562 ahd->pci_cachesize *= 4; 563 564 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 565 /* See if we have a SEEPROM and perform auto-term */ 566 error = ahd_check_extport(ahd); 567 if (error != 0) 568 return; 569 570 /* Core initialization */ 571 error = ahd_init(ahd); 572 if (error != 0) 573 return; 574 575 /* 576 * Link this softc in with all other ahd instances. 577 */ 578 ahd_attach(ahd); 579 } 580 581 /* 582 * Perform some simple tests that should catch situations where 583 * our registers are invalidly mapped. 584 */ 585 int 586 ahd_pci_test_register_access(struct ahd_softc *ahd) 587 { 588 uint32_t cmd; 589 struct ahd_pci_busdata *bd = ahd->bus_data; 590 u_int targpcistat; 591 uint32_t pci_status1; 592 int error; 593 uint8_t hcntrl; 594 595 error = EIO; 596 597 /* 598 * Enable PCI error interrupt status, but suppress NMIs 599 * generated by SERR raised due to target aborts. 600 */ 601 cmd = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 602 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 603 cmd & ~PCI_COMMAND_SERR_ENABLE); 604 605 /* 606 * First a simple test to see if any 607 * registers can be read. Reading 608 * HCNTRL has no side effects and has 609 * at least one bit that is guaranteed to 610 * be zero so it is a good register to 611 * use for this test. 612 */ 613 hcntrl = ahd_inb(ahd, HCNTRL); 614 if (hcntrl == 0xFF) 615 goto fail; 616 617 /* 618 * Next create a situation where write combining 619 * or read prefetching could be initiated by the 620 * CPU or host bridge. Our device does not support 621 * either, so look for data corruption and/or flaged 622 * PCI errors. First pause without causing another 623 * chip reset. 624 */ 625 hcntrl &= ~CHIPRST; 626 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 627 while (ahd_is_paused(ahd) == 0) 628 ; 629 630 /* Clear any PCI errors that occurred before our driver attached. */ 631 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 632 targpcistat = ahd_inb(ahd, TARGPCISTAT); 633 ahd_outb(ahd, TARGPCISTAT, targpcistat); 634 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 635 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, pci_status1); 636 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 637 ahd_outb(ahd, CLRINT, CLRPCIINT); 638 639 ahd_outb(ahd, SEQCTL0, PERRORDIS); 640 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 641 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 642 goto fail; 643 644 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 645 u_int targpcistat; 646 647 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 648 targpcistat = ahd_inb(ahd, TARGPCISTAT); 649 if ((targpcistat & STA) != 0) 650 goto fail; 651 } 652 653 error = 0; 654 655 fail: 656 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 657 658 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 659 targpcistat = ahd_inb(ahd, TARGPCISTAT); 660 661 /* Silently clear any latched errors. */ 662 ahd_outb(ahd, TARGPCISTAT, targpcistat); 663 pci_status1 = pci_conf_read(bd->pc, bd->tag, 664 PCI_COMMAND_STATUS_REG); 665 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 666 pci_status1); 667 ahd_outb(ahd, CLRINT, CLRPCIINT); 668 } 669 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 670 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, cmd); 671 return (error); 672 } 673 674 /* 675 * Check the external port logic for a serial eeprom 676 * and termination/cable detection contrls. 677 */ 678 static int 679 ahd_check_extport(struct ahd_softc *ahd) 680 { 681 struct vpd_config vpd; 682 struct seeprom_config *sc; 683 u_int adapter_control; 684 int have_seeprom; 685 int error; 686 687 sc = ahd->seep_config; 688 have_seeprom = ahd_acquire_seeprom(ahd); 689 if (have_seeprom) { 690 u_int start_addr; 691 692 /* 693 * Fetch VPD for this function and parse it. 694 */ 695 #ifdef AHD_DEBUG 696 printf("%s: Reading VPD from SEEPROM...", 697 ahd_name(ahd)); 698 #endif 699 /* Address is always in units of 16bit words */ 700 start_addr = ((2 * sizeof(*sc)) 701 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 702 703 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 704 start_addr, sizeof(vpd)/2, 705 /*bytestream*/TRUE); 706 if (error == 0) 707 error = ahd_parse_vpddata(ahd, &vpd); 708 #ifdef AHD_DEBUG 709 printf("%s: VPD parsing %s\n", 710 ahd_name(ahd), 711 error == 0 ? "successful" : "failed"); 712 #endif 713 714 #ifdef AHD_DEBUG 715 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 716 #endif 717 718 /* Address is always in units of 16bit words */ 719 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 720 721 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 722 start_addr, sizeof(*sc)/2, 723 /*bytestream*/FALSE); 724 725 if (error != 0) { 726 #ifdef AHD_DEBUG 727 printf("Unable to read SEEPROM\n"); 728 #endif 729 have_seeprom = 0; 730 } else { 731 have_seeprom = ahd_verify_cksum(sc); 732 #ifdef AHD_DEBUG 733 if (have_seeprom == 0) 734 printf ("checksum error\n"); 735 else 736 printf ("done.\n"); 737 #endif 738 } 739 ahd_release_seeprom(ahd); 740 } 741 742 if (!have_seeprom) { 743 u_int nvram_scb; 744 745 /* 746 * Pull scratch ram settings and treat them as 747 * if they are the contents of an seeprom if 748 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 749 * in SCB 0xFF. We manually compose the data as 16bit 750 * values to avoid endian issues. 751 */ 752 ahd_set_scbptr(ahd, 0xFF); 753 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 754 if (nvram_scb != 0xFF 755 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 756 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 757 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 758 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 759 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 760 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 761 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 762 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 763 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 764 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 765 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 766 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 767 uint16_t *sc_data; 768 int i; 769 770 ahd_set_scbptr(ahd, nvram_scb); 771 sc_data = (uint16_t *)sc; 772 for (i = 0; i < 64; i += 2) 773 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 774 have_seeprom = ahd_verify_cksum(sc); 775 if (have_seeprom) 776 ahd->flags |= AHD_SCB_CONFIG_USED; 777 } 778 } 779 780 #ifdef AHD_DEBUG 781 if ((have_seeprom != 0) && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 782 uint16_t *sc_data; 783 int i; 784 785 printf("%s: Seeprom Contents:", ahd_name(ahd)); 786 sc_data = (uint16_t *)sc; 787 for (i = 0; i < (sizeof(*sc)); i += 2) 788 printf("\n\t0x%.4x", sc_data[i]); 789 printf("\n"); 790 } 791 #endif 792 793 if (!have_seeprom) { 794 aprint_error("%s: No SEEPROM available.\n", ahd_name(ahd)); 795 ahd->flags |= AHD_USEDEFAULTS; 796 error = ahd_default_config(ahd); 797 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 798 free(ahd->seep_config, M_DEVBUF); 799 ahd->seep_config = NULL; 800 } else { 801 error = ahd_parse_cfgdata(ahd, sc); 802 adapter_control = sc->adapter_control; 803 } 804 if (error != 0) 805 return (error); 806 807 ahd_configure_termination(ahd, adapter_control); 808 809 return (0); 810 } 811 812 static void 813 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 814 { 815 int error; 816 u_int sxfrctl1; 817 uint8_t termctl; 818 uint32_t devconfig; 819 struct ahd_pci_busdata *bd = ahd->bus_data; 820 821 devconfig = pci_conf_read(bd->pc, bd->tag, DEVCONFIG); 822 devconfig &= ~STPWLEVEL; 823 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 824 devconfig |= STPWLEVEL; 825 #ifdef AHD_DEBUG 826 printf("%s: STPWLEVEL is %s\n", 827 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 828 #endif 829 pci_conf_write(bd->pc, bd->tag, DEVCONFIG, devconfig); 830 831 /* Make sure current sensing is off. */ 832 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 833 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 834 } 835 836 /* 837 * Read to sense. Write to set. 838 */ 839 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 840 if ((adapter_control & CFAUTOTERM) == 0) { 841 if (bootverbose) 842 printf("%s: Manual Primary Termination\n", 843 ahd_name(ahd)); 844 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 845 if ((adapter_control & CFSTERM) != 0) 846 termctl |= FLX_TERMCTL_ENPRILOW; 847 if ((adapter_control & CFWSTERM) != 0) 848 termctl |= FLX_TERMCTL_ENPRIHIGH; 849 } else if (error != 0) { 850 if (bootverbose) 851 printf("%s: Primary Auto-Term Sensing failed! " 852 "Using Defaults.\n", ahd_name(ahd)); 853 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 854 } 855 856 if ((adapter_control & CFSEAUTOTERM) == 0) { 857 if (bootverbose) 858 printf("%s: Manual Secondary Termination\n", 859 ahd_name(ahd)); 860 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 861 if ((adapter_control & CFSELOWTERM) != 0) 862 termctl |= FLX_TERMCTL_ENSECLOW; 863 if ((adapter_control & CFSEHIGHTERM) != 0) 864 termctl |= FLX_TERMCTL_ENSECHIGH; 865 } else if (error != 0) { 866 if (bootverbose) 867 printf("%s: Secondary Auto-Term Sensing failed! " 868 "Using Defaults.\n", ahd_name(ahd)); 869 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 870 } 871 872 /* 873 * Now set the termination based on what we found. 874 */ 875 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 876 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 877 ahd->flags |= AHD_TERM_ENB_A; 878 sxfrctl1 |= STPWEN; 879 } 880 /* Must set the latch once in order to be effective. */ 881 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 882 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 883 884 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 885 if (error != 0) { 886 aprint_error("%s: Unable to set termination settings!\n", 887 ahd_name(ahd)); 888 } else { 889 if (bootverbose) { 890 printf("%s: Primary High byte termination %sabled\n", 891 ahd_name(ahd), 892 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 893 894 printf("%s: Primary Low byte termination %sabled\n", 895 ahd_name(ahd), 896 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 897 898 printf("%s: Secondary High byte termination %sabled\n", 899 ahd_name(ahd), 900 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 901 902 printf("%s: Secondary Low byte termination %sabled\n", 903 ahd_name(ahd), 904 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 905 } 906 } 907 return; 908 } 909 910 #define DPE 0x80 911 #define SSE 0x40 912 #define RMA 0x20 913 #define RTA 0x10 914 #define STA 0x08 915 #define DPR 0x01 916 917 static const char *split_status_source[] = 918 { 919 "DFF0", 920 "DFF1", 921 "OVLY", 922 "CMC", 923 }; 924 925 static const char *pci_status_source[] = 926 { 927 "DFF0", 928 "DFF1", 929 "SG", 930 "CMC", 931 "OVLY", 932 "NONE", 933 "MSI", 934 "TARG" 935 }; 936 937 static const char *split_status_strings[] = 938 { 939 "%s: Received split response in %s.\n", 940 "%s: Received split completion error message in %s\n", 941 "%s: Receive overrun in %s\n", 942 "%s: Count not complete in %s\n", 943 "%s: Split completion data bucket in %s\n", 944 "%s: Split completion address error in %s\n", 945 "%s: Split completion byte count error in %s\n", 946 "%s: Signaled Target-abort to early terminate a split in %s\n" 947 }; 948 949 static const char *pci_status_strings[] = 950 { 951 "%s: Data Parity Error has been reported via PERR# in %s\n", 952 "%s: Target initial wait state error in %s\n", 953 "%s: Split completion read data parity error in %s\n", 954 "%s: Split completion address attribute parity error in %s\n", 955 "%s: Received a Target Abort in %s\n", 956 "%s: Received a Master Abort in %s\n", 957 "%s: Signal System Error Detected in %s\n", 958 "%s: Address or Write Phase Parity Error Detected in %s.\n" 959 }; 960 961 int 962 ahd_pci_intr(struct ahd_softc *ahd) 963 { 964 uint8_t pci_status[8]; 965 ahd_mode_state saved_modes; 966 u_int pci_status1; 967 u_int intstat; 968 u_int i; 969 u_int reg; 970 struct ahd_pci_busdata *bd = ahd->bus_data; 971 972 intstat = ahd_inb(ahd, INTSTAT); 973 974 if ((intstat & SPLTINT) != 0) 975 ahd_pci_split_intr(ahd, intstat); 976 977 if ((intstat & PCIINT) == 0) 978 return 0; 979 980 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 981 saved_modes = ahd_save_modes(ahd); 982 ahd_dump_card_state(ahd); 983 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 984 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 985 986 if (i == 5) 987 continue; 988 pci_status[i] = ahd_inb(ahd, reg); 989 /* Clear latched errors. So our interrupt deasserts. */ 990 ahd_outb(ahd, reg, pci_status[i]); 991 } 992 993 for (i = 0; i < 8; i++) { 994 u_int bit; 995 996 if (i == 5) 997 continue; 998 999 for (bit = 0; bit < 8; bit++) { 1000 1001 if ((pci_status[i] & (0x1 << bit)) != 0) { 1002 static const char *s; 1003 1004 s = pci_status_strings[bit]; 1005 if (i == 7/*TARG*/ && bit == 3) 1006 s = "%s: Signaled Target Abort\n"; 1007 printf(s, ahd_name(ahd), pci_status_source[i]); 1008 } 1009 } 1010 } 1011 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 1012 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG , pci_status1); 1013 1014 ahd_restore_modes(ahd, saved_modes); 1015 ahd_outb(ahd, CLRINT, CLRPCIINT); 1016 ahd_unpause(ahd); 1017 1018 return 1; 1019 } 1020 1021 static void 1022 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 1023 { 1024 uint8_t split_status[4]; 1025 uint8_t split_status1[4]; 1026 uint8_t sg_split_status[2]; 1027 uint8_t sg_split_status1[2]; 1028 ahd_mode_state saved_modes; 1029 u_int i; 1030 pcireg_t pcix_status; 1031 struct ahd_pci_busdata *bd = ahd->bus_data; 1032 1033 /* 1034 * Check for splits in all modes. Modes 0 and 1 1035 * additionally have SG engine splits to look at. 1036 */ 1037 pcix_status = pci_conf_read(bd->pc, bd->tag, 1038 bd->pcix_off + PCI_PCIX_STATUS); 1039 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 1040 ahd_name(ahd), pcix_status); 1041 1042 saved_modes = ahd_save_modes(ahd); 1043 for (i = 0; i < 4; i++) { 1044 ahd_set_modes(ahd, i, i); 1045 1046 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 1047 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 1048 /* Clear latched errors. So our interrupt deasserts. */ 1049 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 1050 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 1051 if (i > 1) 1052 continue; 1053 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 1054 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 1055 /* Clear latched errors. So our interrupt deasserts. */ 1056 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 1057 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 1058 } 1059 1060 for (i = 0; i < 4; i++) { 1061 u_int bit; 1062 1063 for (bit = 0; bit < 8; bit++) { 1064 1065 if ((split_status[i] & (0x1 << bit)) != 0) { 1066 static const char *s; 1067 1068 s = split_status_strings[bit]; 1069 printf(s, ahd_name(ahd), 1070 split_status_source[i]); 1071 } 1072 1073 if (i > 0) 1074 continue; 1075 1076 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 1077 static const char *s; 1078 1079 s = split_status_strings[bit]; 1080 printf(s, ahd_name(ahd), "SG"); 1081 } 1082 } 1083 } 1084 /* 1085 * Clear PCI-X status bits. 1086 */ 1087 pci_conf_write(bd->pc, bd->tag, bd->pcix_off + PCI_PCIX_STATUS, 1088 pcix_status); 1089 ahd_outb(ahd, CLRINT, CLRSPLTINT); 1090 ahd_restore_modes(ahd, saved_modes); 1091 } 1092 1093 static int 1094 ahd_aic7901_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1095 { 1096 1097 ahd->chip = AHD_AIC7901; 1098 ahd->features = AHD_AIC7901_FE; 1099 return (ahd_aic790X_setup(ahd, pa)); 1100 } 1101 1102 static int 1103 ahd_aic7901A_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1104 { 1105 1106 ahd->chip = AHD_AIC7901A; 1107 ahd->features = AHD_AIC7901A_FE; 1108 return (ahd_aic790X_setup(ahd, pa)); 1109 } 1110 1111 static int 1112 ahd_aic7902_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1113 { 1114 1115 ahd->chip = AHD_AIC7902; 1116 ahd->features = AHD_AIC7902_FE; 1117 return (ahd_aic790X_setup(ahd, pa)); 1118 } 1119 1120 static int 1121 ahd_aic790X_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1122 { 1123 u_int rev; 1124 1125 rev = PCI_REVISION(pa->pa_class); 1126 #ifdef AHD_DEBUG 1127 printf("\n%s: aic7902 chip revision 0x%x\n", ahd_name(ahd), rev); 1128 #endif 1129 if (rev < ID_AIC7902_PCI_REV_A4) { 1130 aprint_error("%s: Unable to attach to unsupported chip revision %d\n", 1131 ahd_name(ahd), rev); 1132 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 0); 1133 return (ENXIO); 1134 } 1135 1136 ahd->channel = (pa->pa_function == 1) ? 'B' : 'A'; 1137 if (rev < ID_AIC7902_PCI_REV_B0) { 1138 /* 1139 * Enable A series workarounds. 1140 */ 1141 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 1142 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 1143 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 1144 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 1145 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 1146 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 1147 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 1148 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 1149 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 1150 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 1151 | AHD_FAINT_LED_BUG; 1152 1153 1154 /* 1155 * IO Cell parameter setup. 1156 */ 1157 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1158 1159 if ((ahd->flags & AHD_HP_BOARD) == 0) 1160 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 1161 } else { 1162 u_int devconfig1; 1163 1164 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1165 | AHD_NEW_DFCNTRL_OPTS; 1166 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; 1167 1168 /* 1169 * Some issues have been resolved in the 7901B. 1170 */ 1171 if ((ahd->features & AHD_MULTI_FUNC) != 0) 1172 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG; 1173 1174 /* 1175 * IO Cell parameter setup. 1176 */ 1177 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1178 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1179 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1180 1181 /* 1182 * Set the PREQDIS bit for H2B which disables some workaround 1183 * that doesn't work on regular PCI busses. 1184 * XXX - Find out exactly what this does from the hardware 1185 * folks! 1186 */ 1187 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1188 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG1, devconfig1|PREQDIS); 1189 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1190 } 1191 1192 return (0); 1193 } 1194
Indexes created Thu Oct 02 10:09:58 GMT 2025