ahd_pci.c revision 1.21
1 /* $NetBSD: ahd_pci.c,v 1.21 2005/12/24 20:27:42 perry Exp $ */ 2 3 /* 4 * Product specific probe and attach routines for: 5 * aic7901 and aic7902 SCSI controllers 6 * 7 * Copyright (c) 1994-2001 Justin T. Gibbs. 8 * Copyright (c) 2000-2002 Adaptec Inc. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * substantially similar to the "NO WARRANTY" disclaimer below 19 * ("Disclaimer") and any redistribution must be conditioned upon 20 * including a substantially similar Disclaimer requirement for further 21 * binary redistribution. 22 * 3. Neither the names of the above-listed copyright holders nor the names 23 * of any contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * Alternatively, this software may be distributed under the terms of the 27 * GNU General Public License ("GPL") version 2 as published by the Free 28 * Software Foundation. 29 * 30 * NO WARRANTY 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGES. 42 * 43 * Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#80 $ 44 * 45 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx_pci.c,v 1.16 2003/06/28 04:39:49 gibbs Exp $ 46 */ 47 /* 48 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: ahd_pci.c,v 1.21 2005/12/24 20:27:42 perry Exp $"); 53 54 #define AHD_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 55 #define AHD_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 56 57 #include <dev/ic/aic79xx_osm.h> 58 #include <dev/ic/aic79xx_inline.h> 59 60 static inline uint64_t 61 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 62 { 63 uint64_t id; 64 65 id = subvendor 66 | (subdevice << 16) 67 | ((uint64_t)vendor << 32) 68 | ((uint64_t)device << 48); 69 70 return (id); 71 } 72 73 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 74 #define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull 75 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 76 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 77 #define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull 78 79 #define ID_AIC7901 0x800F9005FFFF9005ull 80 #define ID_AHA_29320A 0x8000900500609005ull 81 #define ID_AHA_29320ALP 0x8017900500449005ull 82 83 #define ID_AIC7901A 0x801E9005FFFF9005ull 84 #define ID_AHA_29320LP 0x8014900500449005ull 85 86 #define ID_AIC7902 0x801F9005FFFF9005ull 87 #define ID_AIC7902_B 0x801D9005FFFF9005ull 88 #define ID_AHA_39320 0x8010900500409005ull 89 #define ID_AHA_29320 0x8012900500429005ull 90 #define ID_AHA_29320B 0x8013900500439005ull 91 #define ID_AHA_39320_B 0x8015900500409005ull 92 #define ID_AHA_39320A 0x8016900500409005ull 93 #define ID_AHA_39320D 0x8011900500419005ull 94 #define ID_AHA_39320D_B 0x801C900500419005ull 95 #define ID_AHA_39320_B_DELL 0x8015900501681028ull 96 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull 97 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 98 #define ID_AIC7902_PCI_REV_A4 0x3 99 #define ID_AIC7902_PCI_REV_B0 0x10 100 #define SUBID_HP 0x0E11 101 102 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80) 103 104 #define DEVID_9005_TYPE(id) ((id) & 0xF) 105 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 106 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 107 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 108 109 #define DEVID_9005_MFUNC(id) ((id) & 0x10) 110 111 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 112 113 #define SUBID_9005_TYPE(id) ((id) & 0xF) 114 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 115 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 116 117 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 118 119 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 120 121 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 122 #define SUBID_9005_SEEPTYPE_NONE 0x0 123 #define SUBID_9005_SEEPTYPE_4K 0x1 124 125 static ahd_device_setup_t ahd_aic7901_setup; 126 static ahd_device_setup_t ahd_aic7901A_setup; 127 static ahd_device_setup_t ahd_aic7902_setup; 128 static ahd_device_setup_t ahd_aic790X_setup; 129 130 static struct ahd_pci_identity ahd_pci_ident_table [] = 131 { 132 /* aic7901 based controllers */ 133 { 134 ID_AHA_29320A, 135 ID_ALL_MASK, 136 "Adaptec 29320A Ultra320 SCSI adapter", 137 ahd_aic7901_setup 138 }, 139 { 140 ID_AHA_29320ALP, 141 ID_ALL_MASK, 142 "Adaptec 29320ALP Ultra320 SCSI adapter", 143 ahd_aic7901_setup 144 }, 145 /* aic7901A based controllers */ 146 { 147 ID_AHA_29320LP, 148 ID_ALL_MASK, 149 "Adaptec 29320LP Ultra320 SCSI adapter", 150 ahd_aic7901A_setup 151 }, 152 /* aic7902 based controllers */ 153 { 154 ID_AHA_39320, 155 ID_ALL_MASK, 156 "Adaptec 39320 Ultra320 SCSI adapter", 157 ahd_aic7902_setup 158 }, 159 { 160 ID_AHA_39320_B, 161 ID_ALL_MASK, 162 "Adaptec 39320 Ultra320 SCSI adapter", 163 ahd_aic7902_setup 164 }, 165 { 166 ID_AHA_39320_B_DELL, 167 ID_ALL_IROC_MASK, 168 "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter", 169 ahd_aic7902_setup 170 }, 171 { 172 ID_AHA_39320A, 173 ID_ALL_MASK, 174 "Adaptec 39320A Ultra320 SCSI adapter", 175 ahd_aic7902_setup 176 }, 177 { 178 ID_AHA_39320D, 179 ID_ALL_MASK, 180 "Adaptec 39320D Ultra320 SCSI adapter", 181 ahd_aic7902_setup 182 }, 183 { 184 ID_AHA_39320D_HP, 185 ID_ALL_MASK, 186 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 187 ahd_aic7902_setup 188 }, 189 { 190 ID_AHA_39320D_B, 191 ID_ALL_MASK, 192 "Adaptec 39320D Ultra320 SCSI adapter", 193 ahd_aic7902_setup 194 }, 195 { 196 ID_AHA_39320D_B_HP, 197 ID_ALL_MASK, 198 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 199 ahd_aic7902_setup 200 }, 201 /* Generic chip probes for devices we don't know 'exactly' */ 202 { 203 ID_AIC7901 & ID_9005_GENERIC_MASK, 204 ID_9005_GENERIC_MASK, 205 "Adaptec AIC7901 Ultra320 SCSI adapter", 206 ahd_aic7901_setup 207 }, 208 { 209 ID_AIC7901A & ID_DEV_VENDOR_MASK, 210 ID_DEV_VENDOR_MASK, 211 "Adaptec AIC7901A Ultra320 SCSI adapter", 212 ahd_aic7901A_setup 213 }, 214 { 215 ID_AIC7902 & ID_9005_GENERIC_MASK, 216 ID_9005_GENERIC_MASK, 217 "Adaptec AIC7902 Ultra320 SCSI adapter", 218 ahd_aic7902_setup 219 } 220 }; 221 222 static const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 223 224 #define DEVCONFIG 0x40 225 #define PCIXINITPAT 0x0000E000ul 226 #define PCIXINIT_PCI33_66 0x0000E000ul 227 #define PCIXINIT_PCIX50_66 0x0000C000ul 228 #define PCIXINIT_PCIX66_100 0x0000A000ul 229 #define PCIXINIT_PCIX100_133 0x00008000ul 230 #define PCI_BUS_MODES_INDEX(devconfig) \ 231 (((devconfig) & PCIXINITPAT) >> 13) 232 233 static const char *pci_bus_modes[] = 234 { 235 "PCI bus mode unknown", 236 "PCI bus mode unknown", 237 "PCI bus mode unknown", 238 "PCI bus mode unknown", 239 "PCI-X 101-133Mhz", 240 "PCI-X 67-100Mhz", 241 "PCI-X 50-66Mhz", 242 "PCI 33 or 66Mhz" 243 }; 244 245 #define TESTMODE 0x00000800ul 246 #define IRDY_RST 0x00000200ul 247 #define FRAME_RST 0x00000100ul 248 #define PCI64BIT 0x00000080ul 249 #define MRDCEN 0x00000040ul 250 #define ENDIANSEL 0x00000020ul 251 #define MIXQWENDIANEN 0x00000008ul 252 #define DACEN 0x00000004ul 253 #define STPWLEVEL 0x00000002ul 254 #define QWENDIANSEL 0x00000001ul 255 256 #define DEVCONFIG1 0x44 257 #define PREQDIS 0x01 258 259 #define LATTIME 0x0000ff00ul 260 261 static int ahd_check_extport(struct ahd_softc *ahd); 262 static void ahd_configure_termination(struct ahd_softc *ahd, 263 u_int adapter_control); 264 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 265 266 static int ahd_pci_test_register_access(struct ahd_softc *); 267 268 static int ahd_pci_intr(struct ahd_softc *); 269 270 static const struct ahd_pci_identity * 271 ahd_find_pci_device(pcireg_t id, pcireg_t subid) 272 { 273 u_int64_t full_id; 274 const struct ahd_pci_identity *entry; 275 u_int i; 276 277 full_id = ahd_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 278 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 279 280 for (i = 0; i < ahd_num_pci_devs; i++) { 281 entry = &ahd_pci_ident_table[i]; 282 if (entry->full_id == (full_id & entry->id_mask)) 283 return (entry); 284 } 285 return (NULL); 286 } 287 288 static int 289 ahd_pci_probe(struct device *parent, struct cfdata *match, void *aux) 290 { 291 struct pci_attach_args *pa = aux; 292 const struct ahd_pci_identity *entry; 293 pcireg_t subid; 294 295 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 296 entry = ahd_find_pci_device(pa->pa_id, subid); 297 return entry != NULL ? 1 : 0; 298 } 299 300 static void 301 ahd_pci_attach(struct device *parent, struct device *self, void *aux) 302 { 303 struct pci_attach_args *pa = aux; 304 struct ahd_softc *ahd = (void *)self; 305 306 const struct ahd_pci_identity *entry; 307 308 uint32_t devconfig; 309 pcireg_t command; 310 int error; 311 pcireg_t subid; 312 uint16_t subvendor; 313 int pci_pwrmgmt_cap_reg; 314 int pci_pwrmgmt_csr_reg; 315 pcireg_t reg; 316 int ioh_valid, ioh2_valid, memh_valid; 317 pcireg_t memtype; 318 pci_intr_handle_t ih; 319 const char *intrstr; 320 struct ahd_pci_busdata *bd; 321 322 ahd_set_name(ahd, ahd->sc_dev.dv_xname); 323 ahd->parent_dmat = pa->pa_dmat; 324 325 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 326 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 327 entry = ahd_find_pci_device(pa->pa_id, subid); 328 if (entry == NULL) 329 return; 330 331 /* Keep information about the PCI bus */ 332 bd = malloc(sizeof (struct ahd_pci_busdata), M_DEVBUF, M_NOWAIT); 333 if (bd == NULL) { 334 aprint_error("%s: unable to allocate bus-specific data\n", ahd_name(ahd)); 335 return; 336 } 337 memset(bd, 0, sizeof(struct ahd_pci_busdata)); 338 339 bd->pc = pa->pa_pc; 340 bd->tag = pa->pa_tag; 341 bd->func = pa->pa_function; 342 bd->dev = pa->pa_device; 343 344 ahd->bus_data = bd; 345 346 ahd->description = entry->name; 347 348 ahd->seep_config = malloc(sizeof(*ahd->seep_config), 349 M_DEVBUF, M_NOWAIT); 350 if (ahd->seep_config == NULL) { 351 aprint_error("%s: cannot malloc seep_config!\n", ahd_name(ahd)); 352 return; 353 } 354 memset(ahd->seep_config, 0, sizeof(*ahd->seep_config)); 355 356 LIST_INIT(&ahd->pending_scbs); 357 ahd_timer_init(&ahd->reset_timer); 358 ahd_timer_init(&ahd->stat_timer); 359 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A 360 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A; 361 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT; 362 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT; 363 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT; 364 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT; 365 ahd->int_coalescing_stop_threshold = AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT; 366 367 if (ahd_platform_alloc(ahd, NULL) != 0) { 368 ahd_free(ahd); 369 return; 370 } 371 372 /* 373 * Record if this is an HP board. 374 */ 375 subvendor = PCI_VENDOR(subid); 376 if (subvendor == SUBID_HP) 377 ahd->flags |= AHD_HP_BOARD; 378 379 error = entry->setup(ahd, pa); 380 if (error != 0) 381 return; 382 383 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 384 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 385 ahd->chip |= AHD_PCI; 386 /* Disable PCIX workarounds when running in PCI mode. */ 387 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 388 } else { 389 ahd->chip |= AHD_PCIX; 390 } 391 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 392 393 memh_valid = ioh_valid = ioh2_valid = 0; 394 395 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 396 &bd->pcix_off, NULL)) { 397 if (ahd->chip & AHD_PCIX) 398 aprint_error("%s: warning: can't find PCI-X capability\n", 399 ahd->sc_dev.dv_xname); 400 ahd->chip &= ~AHD_PCIX; 401 ahd->chip |= AHD_PCI; 402 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 403 } 404 405 /* 406 * Map PCI Registers 407 */ 408 if ((ahd->bugs & AHD_PCIX_MMAPIO_BUG) == 0) { 409 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 410 AHD_PCI_MEMADDR); 411 switch (memtype) { 412 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 413 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 414 memh_valid = (pci_mapreg_map(pa, AHD_PCI_MEMADDR, 415 memtype, 0, &ahd->tags[0], 416 &ahd->bshs[0], 417 NULL, NULL) == 0); 418 if (memh_valid) { 419 ahd->tags[1] = ahd->tags[0]; 420 bus_space_subregion(ahd->tags[0], ahd->bshs[0], 421 /*offset*/0x100, 422 /*size*/0x100, 423 &ahd->bshs[1]); 424 if (ahd_pci_test_register_access(ahd) != 0) 425 memh_valid = 0; 426 } 427 break; 428 default: 429 memh_valid = 0; 430 aprint_error("%s: unknown memory type: 0x%x\n", 431 ahd_name(ahd), memtype); 432 break; 433 } 434 435 if (memh_valid) { 436 command &= ~PCI_COMMAND_IO_ENABLE; 437 pci_conf_write(pa->pa_pc, pa->pa_tag, 438 PCI_COMMAND_STATUS_REG, command); 439 } 440 #ifdef AHD_DEBUG 441 printf("%s: doing memory mapping tag0 0x%x, tag1 0x%x, " 442 "shs0 0x%lx, shs1 0x%lx\n", 443 ahd_name(ahd), ahd->tags[0], ahd->tags[1], 444 ahd->bshs[0], ahd->bshs[1]); 445 #endif 446 } 447 448 if (command & PCI_COMMAND_IO_ENABLE) { 449 /* First BAR */ 450 ioh_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR, 451 PCI_MAPREG_TYPE_IO, 0, 452 &ahd->tags[0], &ahd->bshs[0], 453 NULL, NULL) == 0); 454 455 /* 2nd BAR */ 456 ioh2_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR1, 457 PCI_MAPREG_TYPE_IO, 0, 458 &ahd->tags[1], &ahd->bshs[1], 459 NULL, NULL) == 0); 460 461 if (ioh_valid && ioh2_valid) { 462 KASSERT(memh_valid == 0); 463 command &= ~PCI_COMMAND_MEM_ENABLE; 464 pci_conf_write(pa->pa_pc, pa->pa_tag, 465 PCI_COMMAND_STATUS_REG, command); 466 } 467 #ifdef AHD_DEBUG 468 printf("%s: doing io mapping tag0 0x%x, tag1 0x%x, " 469 "shs0 0x%lx, shs1 0x%lx\n", ahd_name(ahd), ahd->tags[0], 470 ahd->tags[1], ahd->bshs[0], ahd->bshs[1]); 471 #endif 472 473 } 474 475 if (memh_valid == 0 && (ioh_valid == 0 || ioh2_valid == 0)) { 476 aprint_error("%s: unable to map registers\n", ahd_name(ahd)); 477 return; 478 } 479 480 aprint_normal("\n"); 481 aprint_naive("\n"); 482 483 /* 484 * Set Power State D0. 485 */ 486 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 487 &pci_pwrmgmt_cap_reg, 0)) { 488 489 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 490 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 491 pci_pwrmgmt_csr_reg); 492 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 493 pci_conf_write(pa->pa_pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 494 (reg & ~PCI_PMCSR_STATE_MASK) | 495 PCI_PMCSR_STATE_D0); 496 } 497 } 498 499 /* 500 * Should we bother disabling 39Bit addressing 501 * based on installed memory? 502 */ 503 if (sizeof(bus_addr_t) > 4) 504 ahd->flags |= AHD_39BIT_ADDRESSING; 505 506 /* 507 * If we need to support high memory, enable dual 508 * address cycles. This bit must be set to enable 509 * high address bit generation even if we are on a 510 * 64bit bus (PCI64BIT set in devconfig). 511 */ 512 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 513 uint32_t dvconfig; 514 515 aprint_normal("%s: Enabling 39Bit Addressing\n", ahd_name(ahd)); 516 dvconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 517 dvconfig |= DACEN; 518 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, dvconfig); 519 } 520 521 /* Ensure busmastering is enabled */ 522 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 523 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 524 reg | PCI_COMMAND_MASTER_ENABLE); 525 526 ahd_softc_init(ahd); 527 528 /* 529 * Map the interrupt routines 530 */ 531 ahd->bus_intr = ahd_pci_intr; 532 533 error = ahd_reset(ahd, /*reinit*/FALSE); 534 if (error != 0) { 535 ahd_free(ahd); 536 return; 537 } 538 539 if (pci_intr_map(pa, &ih)) { 540 aprint_error("%s: couldn't map interrupt\n", ahd_name(ahd)); 541 ahd_free(ahd); 542 return; 543 } 544 intrstr = pci_intr_string(pa->pa_pc, ih); 545 ahd->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahd_intr, ahd); 546 if (ahd->ih == NULL) { 547 aprint_error("%s: couldn't establish interrupt", 548 ahd_name(ahd)); 549 if (intrstr != NULL) 550 aprint_error(" at %s", intrstr); 551 aprint_error("\n"); 552 ahd_free(ahd); 553 return; 554 } 555 if (intrstr != NULL) 556 aprint_normal("%s: interrupting at %s\n", ahd_name(ahd), 557 intrstr); 558 559 /* Get the size of the cache */ 560 ahd->pci_cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 561 ahd->pci_cachesize *= 4; 562 563 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 564 /* See if we have a SEEPROM and perform auto-term */ 565 error = ahd_check_extport(ahd); 566 if (error != 0) 567 return; 568 569 /* Core initialization */ 570 error = ahd_init(ahd); 571 if (error != 0) 572 return; 573 574 /* 575 * Link this softc in with all other ahd instances. 576 */ 577 ahd_attach(ahd); 578 } 579 580 CFATTACH_DECL(ahd_pci, sizeof(struct ahd_softc), 581 ahd_pci_probe, ahd_pci_attach, NULL, NULL); 582 583 /* 584 * Perform some simple tests that should catch situations where 585 * our registers are invalidly mapped. 586 */ 587 static int 588 ahd_pci_test_register_access(struct ahd_softc *ahd) 589 { 590 uint32_t cmd; 591 struct ahd_pci_busdata *bd = ahd->bus_data; 592 u_int targpcistat; 593 uint32_t pci_status1; 594 int error; 595 uint8_t hcntrl; 596 597 error = EIO; 598 599 /* 600 * Enable PCI error interrupt status, but suppress NMIs 601 * generated by SERR raised due to target aborts. 602 */ 603 cmd = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 604 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 605 cmd & ~PCI_COMMAND_SERR_ENABLE); 606 607 /* 608 * First a simple test to see if any 609 * registers can be read. Reading 610 * HCNTRL has no side effects and has 611 * at least one bit that is guaranteed to 612 * be zero so it is a good register to 613 * use for this test. 614 */ 615 hcntrl = ahd_inb(ahd, HCNTRL); 616 if (hcntrl == 0xFF) 617 goto fail; 618 619 /* 620 * Next create a situation where write combining 621 * or read prefetching could be initiated by the 622 * CPU or host bridge. Our device does not support 623 * either, so look for data corruption and/or flaged 624 * PCI errors. First pause without causing another 625 * chip reset. 626 */ 627 hcntrl &= ~CHIPRST; 628 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 629 while (ahd_is_paused(ahd) == 0) 630 ; 631 632 /* Clear any PCI errors that occurred before our driver attached. */ 633 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 634 targpcistat = ahd_inb(ahd, TARGPCISTAT); 635 ahd_outb(ahd, TARGPCISTAT, targpcistat); 636 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 637 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, pci_status1); 638 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 639 ahd_outb(ahd, CLRINT, CLRPCIINT); 640 641 ahd_outb(ahd, SEQCTL0, PERRORDIS); 642 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 643 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 644 goto fail; 645 646 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 647 u_int trgpcistat; 648 649 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 650 trgpcistat = ahd_inb(ahd, TARGPCISTAT); 651 if ((trgpcistat & STA) != 0) 652 goto fail; 653 } 654 655 error = 0; 656 657 fail: 658 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 659 660 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 661 targpcistat = ahd_inb(ahd, TARGPCISTAT); 662 663 /* Silently clear any latched errors. */ 664 ahd_outb(ahd, TARGPCISTAT, targpcistat); 665 pci_status1 = pci_conf_read(bd->pc, bd->tag, 666 PCI_COMMAND_STATUS_REG); 667 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 668 pci_status1); 669 ahd_outb(ahd, CLRINT, CLRPCIINT); 670 } 671 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 672 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, cmd); 673 return (error); 674 } 675 676 /* 677 * Check the external port logic for a serial eeprom 678 * and termination/cable detection contrls. 679 */ 680 static int 681 ahd_check_extport(struct ahd_softc *ahd) 682 { 683 struct vpd_config vpd; 684 struct seeprom_config *sc; 685 u_int adapter_control; 686 int have_seeprom; 687 int error; 688 689 sc = ahd->seep_config; 690 have_seeprom = ahd_acquire_seeprom(ahd); 691 if (have_seeprom) { 692 u_int start_addr; 693 694 /* 695 * Fetch VPD for this function and parse it. 696 */ 697 #ifdef AHD_DEBUG 698 printf("%s: Reading VPD from SEEPROM...", 699 ahd_name(ahd)); 700 #endif 701 /* Address is always in units of 16bit words */ 702 start_addr = ((2 * sizeof(*sc)) 703 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 704 705 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 706 start_addr, sizeof(vpd)/2, 707 /*bytestream*/TRUE); 708 if (error == 0) 709 error = ahd_parse_vpddata(ahd, &vpd); 710 #ifdef AHD_DEBUG 711 printf("%s: VPD parsing %s\n", 712 ahd_name(ahd), 713 error == 0 ? "successful" : "failed"); 714 #endif 715 716 #ifdef AHD_DEBUG 717 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 718 #endif 719 720 /* Address is always in units of 16bit words */ 721 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 722 723 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 724 start_addr, sizeof(*sc)/2, 725 /*bytestream*/FALSE); 726 727 if (error != 0) { 728 #ifdef AHD_DEBUG 729 printf("Unable to read SEEPROM\n"); 730 #endif 731 have_seeprom = 0; 732 } else { 733 have_seeprom = ahd_verify_cksum(sc); 734 #ifdef AHD_DEBUG 735 if (have_seeprom == 0) 736 printf ("checksum error\n"); 737 else 738 printf ("done.\n"); 739 #endif 740 } 741 ahd_release_seeprom(ahd); 742 } 743 744 if (!have_seeprom) { 745 u_int nvram_scb; 746 747 /* 748 * Pull scratch ram settings and treat them as 749 * if they are the contents of an seeprom if 750 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 751 * in SCB 0xFF. We manually compose the data as 16bit 752 * values to avoid endian issues. 753 */ 754 ahd_set_scbptr(ahd, 0xFF); 755 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 756 if (nvram_scb != 0xFF 757 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 758 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 759 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 760 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 761 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 762 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 763 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 764 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 765 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 766 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 767 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 768 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 769 uint16_t *sc_data; 770 int i; 771 772 ahd_set_scbptr(ahd, nvram_scb); 773 sc_data = (uint16_t *)sc; 774 for (i = 0; i < 64; i += 2) 775 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 776 have_seeprom = ahd_verify_cksum(sc); 777 if (have_seeprom) 778 ahd->flags |= AHD_SCB_CONFIG_USED; 779 } 780 } 781 782 #ifdef AHD_DEBUG 783 if ((have_seeprom != 0) && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 784 uint16_t *sc_data; 785 int i; 786 787 printf("%s: Seeprom Contents:", ahd_name(ahd)); 788 sc_data = (uint16_t *)sc; 789 for (i = 0; i < (sizeof(*sc)); i += 2) 790 printf("\n\t0x%.4x", sc_data[i]); 791 printf("\n"); 792 } 793 #endif 794 795 if (!have_seeprom) { 796 aprint_error("%s: No SEEPROM available.\n", ahd_name(ahd)); 797 ahd->flags |= AHD_USEDEFAULTS; 798 error = ahd_default_config(ahd); 799 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 800 free(ahd->seep_config, M_DEVBUF); 801 ahd->seep_config = NULL; 802 } else { 803 error = ahd_parse_cfgdata(ahd, sc); 804 adapter_control = sc->adapter_control; 805 } 806 if (error != 0) 807 return (error); 808 809 ahd_configure_termination(ahd, adapter_control); 810 811 return (0); 812 } 813 814 static void 815 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 816 { 817 int error; 818 u_int sxfrctl1; 819 uint8_t termctl; 820 uint32_t devconfig; 821 struct ahd_pci_busdata *bd = ahd->bus_data; 822 823 devconfig = pci_conf_read(bd->pc, bd->tag, DEVCONFIG); 824 devconfig &= ~STPWLEVEL; 825 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 826 devconfig |= STPWLEVEL; 827 #ifdef AHD_DEBUG 828 printf("%s: STPWLEVEL is %s\n", 829 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 830 #endif 831 pci_conf_write(bd->pc, bd->tag, DEVCONFIG, devconfig); 832 833 /* Make sure current sensing is off. */ 834 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 835 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 836 } 837 838 /* 839 * Read to sense. Write to set. 840 */ 841 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 842 if ((adapter_control & CFAUTOTERM) == 0) { 843 if (bootverbose) 844 printf("%s: Manual Primary Termination\n", 845 ahd_name(ahd)); 846 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 847 if ((adapter_control & CFSTERM) != 0) 848 termctl |= FLX_TERMCTL_ENPRILOW; 849 if ((adapter_control & CFWSTERM) != 0) 850 termctl |= FLX_TERMCTL_ENPRIHIGH; 851 } else if (error != 0) { 852 if (bootverbose) 853 printf("%s: Primary Auto-Term Sensing failed! " 854 "Using Defaults.\n", ahd_name(ahd)); 855 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 856 } 857 858 if ((adapter_control & CFSEAUTOTERM) == 0) { 859 if (bootverbose) 860 printf("%s: Manual Secondary Termination\n", 861 ahd_name(ahd)); 862 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 863 if ((adapter_control & CFSELOWTERM) != 0) 864 termctl |= FLX_TERMCTL_ENSECLOW; 865 if ((adapter_control & CFSEHIGHTERM) != 0) 866 termctl |= FLX_TERMCTL_ENSECHIGH; 867 } else if (error != 0) { 868 if (bootverbose) 869 printf("%s: Secondary Auto-Term Sensing failed! " 870 "Using Defaults.\n", ahd_name(ahd)); 871 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 872 } 873 874 /* 875 * Now set the termination based on what we found. 876 */ 877 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 878 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 879 ahd->flags |= AHD_TERM_ENB_A; 880 sxfrctl1 |= STPWEN; 881 } 882 /* Must set the latch once in order to be effective. */ 883 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 884 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 885 886 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 887 if (error != 0) { 888 aprint_error("%s: Unable to set termination settings!\n", 889 ahd_name(ahd)); 890 } else { 891 if (bootverbose) { 892 printf("%s: Primary High byte termination %sabled\n", 893 ahd_name(ahd), 894 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 895 896 printf("%s: Primary Low byte termination %sabled\n", 897 ahd_name(ahd), 898 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 899 900 printf("%s: Secondary High byte termination %sabled\n", 901 ahd_name(ahd), 902 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 903 904 printf("%s: Secondary Low byte termination %sabled\n", 905 ahd_name(ahd), 906 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 907 } 908 } 909 return; 910 } 911 912 #define DPE 0x80 913 #define SSE 0x40 914 #define RMA 0x20 915 #define RTA 0x10 916 #define STA 0x08 917 #define DPR 0x01 918 919 static const char *split_status_source[] = 920 { 921 "DFF0", 922 "DFF1", 923 "OVLY", 924 "CMC", 925 }; 926 927 static const char *pci_status_source[] = 928 { 929 "DFF0", 930 "DFF1", 931 "SG", 932 "CMC", 933 "OVLY", 934 "NONE", 935 "MSI", 936 "TARG" 937 }; 938 939 static const char *split_status_strings[] = 940 { 941 "%s: Received split response in %s.\n", 942 "%s: Received split completion error message in %s\n", 943 "%s: Receive overrun in %s\n", 944 "%s: Count not complete in %s\n", 945 "%s: Split completion data bucket in %s\n", 946 "%s: Split completion address error in %s\n", 947 "%s: Split completion byte count error in %s\n", 948 "%s: Signaled Target-abort to early terminate a split in %s\n" 949 }; 950 951 static const char *pci_status_strings[] = 952 { 953 "%s: Data Parity Error has been reported via PERR# in %s\n", 954 "%s: Target initial wait state error in %s\n", 955 "%s: Split completion read data parity error in %s\n", 956 "%s: Split completion address attribute parity error in %s\n", 957 "%s: Received a Target Abort in %s\n", 958 "%s: Received a Master Abort in %s\n", 959 "%s: Signal System Error Detected in %s\n", 960 "%s: Address or Write Phase Parity Error Detected in %s.\n" 961 }; 962 963 static int 964 ahd_pci_intr(struct ahd_softc *ahd) 965 { 966 uint8_t pci_status[8]; 967 ahd_mode_state saved_modes; 968 u_int pci_status1; 969 u_int intstat; 970 u_int i; 971 u_int reg; 972 struct ahd_pci_busdata *bd = ahd->bus_data; 973 974 intstat = ahd_inb(ahd, INTSTAT); 975 976 if ((intstat & SPLTINT) != 0) 977 ahd_pci_split_intr(ahd, intstat); 978 979 if ((intstat & PCIINT) == 0) 980 return 0; 981 982 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 983 saved_modes = ahd_save_modes(ahd); 984 ahd_dump_card_state(ahd); 985 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 986 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 987 988 if (i == 5) 989 continue; 990 pci_status[i] = ahd_inb(ahd, reg); 991 /* Clear latched errors. So our interrupt deasserts. */ 992 ahd_outb(ahd, reg, pci_status[i]); 993 } 994 995 for (i = 0; i < 8; i++) { 996 u_int bit; 997 998 if (i == 5) 999 continue; 1000 1001 for (bit = 0; bit < 8; bit++) { 1002 1003 if ((pci_status[i] & (0x1 << bit)) != 0) { 1004 static const char *s; 1005 1006 s = pci_status_strings[bit]; 1007 if (i == 7/*TARG*/ && bit == 3) 1008 s = "%s: Signaled Target Abort\n"; 1009 printf(s, ahd_name(ahd), pci_status_source[i]); 1010 } 1011 } 1012 } 1013 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 1014 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG , pci_status1); 1015 1016 ahd_restore_modes(ahd, saved_modes); 1017 ahd_outb(ahd, CLRINT, CLRPCIINT); 1018 ahd_unpause(ahd); 1019 1020 return 1; 1021 } 1022 1023 static void 1024 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 1025 { 1026 uint8_t split_status[4]; 1027 uint8_t split_status1[4]; 1028 uint8_t sg_split_status[2]; 1029 uint8_t sg_split_status1[2]; 1030 ahd_mode_state saved_modes; 1031 u_int i; 1032 pcireg_t pcix_status; 1033 struct ahd_pci_busdata *bd = ahd->bus_data; 1034 1035 /* 1036 * Check for splits in all modes. Modes 0 and 1 1037 * additionally have SG engine splits to look at. 1038 */ 1039 pcix_status = pci_conf_read(bd->pc, bd->tag, 1040 bd->pcix_off + PCI_PCIX_STATUS); 1041 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 1042 ahd_name(ahd), pcix_status); 1043 1044 saved_modes = ahd_save_modes(ahd); 1045 for (i = 0; i < 4; i++) { 1046 ahd_set_modes(ahd, i, i); 1047 1048 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 1049 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 1050 /* Clear latched errors. So our interrupt deasserts. */ 1051 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 1052 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 1053 if (i > 1) 1054 continue; 1055 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 1056 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 1057 /* Clear latched errors. So our interrupt deasserts. */ 1058 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 1059 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 1060 } 1061 1062 for (i = 0; i < 4; i++) { 1063 u_int bit; 1064 1065 for (bit = 0; bit < 8; bit++) { 1066 1067 if ((split_status[i] & (0x1 << bit)) != 0) { 1068 static const char *s; 1069 1070 s = split_status_strings[bit]; 1071 printf(s, ahd_name(ahd), 1072 split_status_source[i]); 1073 } 1074 1075 if (i > 0) 1076 continue; 1077 1078 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 1079 static const char *s; 1080 1081 s = split_status_strings[bit]; 1082 printf(s, ahd_name(ahd), "SG"); 1083 } 1084 } 1085 } 1086 /* 1087 * Clear PCI-X status bits. 1088 */ 1089 pci_conf_write(bd->pc, bd->tag, bd->pcix_off + PCI_PCIX_STATUS, 1090 pcix_status); 1091 ahd_outb(ahd, CLRINT, CLRSPLTINT); 1092 ahd_restore_modes(ahd, saved_modes); 1093 } 1094 1095 static int 1096 ahd_aic7901_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1097 { 1098 1099 ahd->chip = AHD_AIC7901; 1100 ahd->features = AHD_AIC7901_FE; 1101 return (ahd_aic790X_setup(ahd, pa)); 1102 } 1103 1104 static int 1105 ahd_aic7901A_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1106 { 1107 1108 ahd->chip = AHD_AIC7901A; 1109 ahd->features = AHD_AIC7901A_FE; 1110 return (ahd_aic790X_setup(ahd, pa)); 1111 } 1112 1113 static int 1114 ahd_aic7902_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1115 { 1116 1117 ahd->chip = AHD_AIC7902; 1118 ahd->features = AHD_AIC7902_FE; 1119 return (ahd_aic790X_setup(ahd, pa)); 1120 } 1121 1122 static int 1123 ahd_aic790X_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1124 { 1125 u_int rev; 1126 1127 rev = PCI_REVISION(pa->pa_class); 1128 #ifdef AHD_DEBUG 1129 printf("\n%s: aic7902 chip revision 0x%x\n", ahd_name(ahd), rev); 1130 #endif 1131 if (rev < ID_AIC7902_PCI_REV_A4) { 1132 aprint_error("%s: Unable to attach to unsupported chip revision %d\n", 1133 ahd_name(ahd), rev); 1134 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 0); 1135 return (ENXIO); 1136 } 1137 1138 ahd->channel = (pa->pa_function == 1) ? 'B' : 'A'; 1139 if (rev < ID_AIC7902_PCI_REV_B0) { 1140 /* 1141 * Enable A series workarounds. 1142 */ 1143 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 1144 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 1145 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 1146 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 1147 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 1148 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 1149 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 1150 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 1151 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 1152 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 1153 | AHD_FAINT_LED_BUG; 1154 1155 1156 /* 1157 * IO Cell parameter setup. 1158 */ 1159 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1160 1161 if ((ahd->flags & AHD_HP_BOARD) == 0) 1162 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 1163 } else { 1164 u_int devconfig1; 1165 1166 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1167 | AHD_NEW_DFCNTRL_OPTS; 1168 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; 1169 1170 /* 1171 * Some issues have been resolved in the 7901B. 1172 */ 1173 if ((ahd->features & AHD_MULTI_FUNC) != 0) 1174 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG; 1175 1176 /* 1177 * IO Cell parameter setup. 1178 */ 1179 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1180 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1181 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1182 1183 /* 1184 * Set the PREQDIS bit for H2B which disables some workaround 1185 * that doesn't work on regular PCI busses. 1186 * XXX - Find out exactly what this does from the hardware 1187 * folks! 1188 */ 1189 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1190 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG1, devconfig1|PREQDIS); 1191 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1192 } 1193 1194 return (0); 1195 } 1196
Indexes created Sun Sep 21 20:09:37 GMT 2025