ahd_pci.c revision 1.24
1 /* $NetBSD: ahd_pci.c,v 1.24 2006/10/12 01:31:28 christos Exp $ */ 2 3 /* 4 * Product specific probe and attach routines for: 5 * aic7901 and aic7902 SCSI controllers 6 * 7 * Copyright (c) 1994-2001 Justin T. Gibbs. 8 * Copyright (c) 2000-2002 Adaptec Inc. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * substantially similar to the "NO WARRANTY" disclaimer below 19 * ("Disclaimer") and any redistribution must be conditioned upon 20 * including a substantially similar Disclaimer requirement for further 21 * binary redistribution. 22 * 3. Neither the names of the above-listed copyright holders nor the names 23 * of any contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * Alternatively, this software may be distributed under the terms of the 27 * GNU General Public License ("GPL") version 2 as published by the Free 28 * Software Foundation. 29 * 30 * NO WARRANTY 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGES. 42 * 43 * Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#80 $ 44 * 45 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx_pci.c,v 1.16 2003/06/28 04:39:49 gibbs Exp $ 46 */ 47 /* 48 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: ahd_pci.c,v 1.24 2006/10/12 01:31:28 christos Exp $"); 53 54 #define AHD_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 55 #define AHD_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 56 57 #include <dev/ic/aic79xx_osm.h> 58 #include <dev/ic/aic79xx_inline.h> 59 60 static inline uint64_t 61 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 62 { 63 uint64_t id; 64 65 id = subvendor 66 | (subdevice << 16) 67 | ((uint64_t)vendor << 32) 68 | ((uint64_t)device << 48); 69 70 return (id); 71 } 72 73 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 74 #define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull 75 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 76 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 77 #define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull 78 79 #define ID_AIC7901 0x800F9005FFFF9005ull 80 #define ID_AHA_29320A 0x8000900500609005ull 81 #define ID_AHA_29320ALP 0x8017900500449005ull 82 83 #define ID_AIC7901A 0x801E9005FFFF9005ull 84 #define ID_AHA_29320LP 0x8014900500449005ull 85 86 #define ID_AIC7902 0x801F9005FFFF9005ull 87 #define ID_AIC7902_B 0x801D9005FFFF9005ull 88 #define ID_AHA_39320 0x8010900500409005ull 89 #define ID_AHA_29320 0x8012900500429005ull 90 #define ID_AHA_29320B 0x8013900500439005ull 91 #define ID_AHA_39320_B 0x8015900500409005ull 92 #define ID_AHA_39320A 0x8016900500409005ull 93 #define ID_AHA_39320D 0x8011900500419005ull 94 #define ID_AHA_39320D_B 0x801C900500419005ull 95 #define ID_AHA_39320_B_DELL 0x8015900501681028ull 96 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull 97 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 98 #define ID_AIC7902_PCI_REV_A4 0x3 99 #define ID_AIC7902_PCI_REV_B0 0x10 100 #define SUBID_HP 0x0E11 101 102 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80) 103 104 #define DEVID_9005_TYPE(id) ((id) & 0xF) 105 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 106 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 107 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 108 109 #define DEVID_9005_MFUNC(id) ((id) & 0x10) 110 111 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 112 113 #define SUBID_9005_TYPE(id) ((id) & 0xF) 114 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 115 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 116 117 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 118 119 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 120 121 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 122 #define SUBID_9005_SEEPTYPE_NONE 0x0 123 #define SUBID_9005_SEEPTYPE_4K 0x1 124 125 static ahd_device_setup_t ahd_aic7901_setup; 126 static ahd_device_setup_t ahd_aic7901A_setup; 127 static ahd_device_setup_t ahd_aic7902_setup; 128 static ahd_device_setup_t ahd_aic790X_setup; 129 130 static struct ahd_pci_identity ahd_pci_ident_table [] = 131 { 132 /* aic7901 based controllers */ 133 { 134 ID_AHA_29320A, 135 ID_ALL_MASK, 136 "Adaptec 29320A Ultra320 SCSI adapter", 137 ahd_aic7901_setup 138 }, 139 { 140 ID_AHA_29320ALP, 141 ID_ALL_MASK, 142 "Adaptec 29320ALP Ultra320 SCSI adapter", 143 ahd_aic7901_setup 144 }, 145 /* aic7901A based controllers */ 146 { 147 ID_AHA_29320LP, 148 ID_ALL_MASK, 149 "Adaptec 29320LP Ultra320 SCSI adapter", 150 ahd_aic7901A_setup 151 }, 152 /* aic7902 based controllers */ 153 { 154 ID_AHA_39320, 155 ID_ALL_MASK, 156 "Adaptec 39320 Ultra320 SCSI adapter", 157 ahd_aic7902_setup 158 }, 159 { 160 ID_AHA_39320_B, 161 ID_ALL_MASK, 162 "Adaptec 39320 Ultra320 SCSI adapter", 163 ahd_aic7902_setup 164 }, 165 { 166 ID_AHA_39320_B_DELL, 167 ID_ALL_IROC_MASK, 168 "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter", 169 ahd_aic7902_setup 170 }, 171 { 172 ID_AHA_39320A, 173 ID_ALL_MASK, 174 "Adaptec 39320A Ultra320 SCSI adapter", 175 ahd_aic7902_setup 176 }, 177 { 178 ID_AHA_39320D, 179 ID_ALL_MASK, 180 "Adaptec 39320D Ultra320 SCSI adapter", 181 ahd_aic7902_setup 182 }, 183 { 184 ID_AHA_39320D_HP, 185 ID_ALL_MASK, 186 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 187 ahd_aic7902_setup 188 }, 189 { 190 ID_AHA_39320D_B, 191 ID_ALL_MASK, 192 "Adaptec 39320D Ultra320 SCSI adapter", 193 ahd_aic7902_setup 194 }, 195 { 196 ID_AHA_39320D_B_HP, 197 ID_ALL_MASK, 198 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 199 ahd_aic7902_setup 200 }, 201 /* Generic chip probes for devices we don't know 'exactly' */ 202 { 203 ID_AIC7901 & ID_9005_GENERIC_MASK, 204 ID_9005_GENERIC_MASK, 205 "Adaptec AIC7901 Ultra320 SCSI adapter", 206 ahd_aic7901_setup 207 }, 208 { 209 ID_AIC7901A & ID_DEV_VENDOR_MASK, 210 ID_DEV_VENDOR_MASK, 211 "Adaptec AIC7901A Ultra320 SCSI adapter", 212 ahd_aic7901A_setup 213 }, 214 { 215 ID_AIC7902 & ID_9005_GENERIC_MASK, 216 ID_9005_GENERIC_MASK, 217 "Adaptec AIC7902 Ultra320 SCSI adapter", 218 ahd_aic7902_setup 219 } 220 }; 221 222 static const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 223 224 #define DEVCONFIG 0x40 225 #define PCIXINITPAT 0x0000E000ul 226 #define PCIXINIT_PCI33_66 0x0000E000ul 227 #define PCIXINIT_PCIX50_66 0x0000C000ul 228 #define PCIXINIT_PCIX66_100 0x0000A000ul 229 #define PCIXINIT_PCIX100_133 0x00008000ul 230 #define PCI_BUS_MODES_INDEX(devconfig) \ 231 (((devconfig) & PCIXINITPAT) >> 13) 232 233 static const char *pci_bus_modes[] = 234 { 235 "PCI bus mode unknown", 236 "PCI bus mode unknown", 237 "PCI bus mode unknown", 238 "PCI bus mode unknown", 239 "PCI-X 101-133 MHz", 240 "PCI-X 67-100 MHz", 241 "PCI-X 50-66 MHz", 242 "PCI 33 or 66 MHz" 243 }; 244 245 #define TESTMODE 0x00000800ul 246 #define IRDY_RST 0x00000200ul 247 #define FRAME_RST 0x00000100ul 248 #define PCI64BIT 0x00000080ul 249 #define MRDCEN 0x00000040ul 250 #define ENDIANSEL 0x00000020ul 251 #define MIXQWENDIANEN 0x00000008ul 252 #define DACEN 0x00000004ul 253 #define STPWLEVEL 0x00000002ul 254 #define QWENDIANSEL 0x00000001ul 255 256 #define DEVCONFIG1 0x44 257 #define PREQDIS 0x01 258 259 #define LATTIME 0x0000ff00ul 260 261 static int ahd_check_extport(struct ahd_softc *ahd); 262 static void ahd_configure_termination(struct ahd_softc *ahd, 263 u_int adapter_control); 264 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 265 266 static int ahd_pci_test_register_access(struct ahd_softc *); 267 268 static int ahd_pci_intr(struct ahd_softc *); 269 270 static const struct ahd_pci_identity * 271 ahd_find_pci_device(pcireg_t id, pcireg_t subid) 272 { 273 u_int64_t full_id; 274 const struct ahd_pci_identity *entry; 275 u_int i; 276 277 full_id = ahd_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 278 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 279 280 for (i = 0; i < ahd_num_pci_devs; i++) { 281 entry = &ahd_pci_ident_table[i]; 282 if (entry->full_id == (full_id & entry->id_mask)) 283 return (entry); 284 } 285 return (NULL); 286 } 287 288 static int 289 ahd_pci_probe(struct device *parent __unused, struct cfdata *match __unused, 290 void *aux) 291 { 292 struct pci_attach_args *pa = aux; 293 const struct ahd_pci_identity *entry; 294 pcireg_t subid; 295 296 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 297 entry = ahd_find_pci_device(pa->pa_id, subid); 298 return entry != NULL ? 1 : 0; 299 } 300 301 static void 302 ahd_pci_attach(struct device *parent __unused, struct device *self, void *aux) 303 { 304 struct pci_attach_args *pa = aux; 305 struct ahd_softc *ahd = (void *)self; 306 307 const struct ahd_pci_identity *entry; 308 309 uint32_t devconfig; 310 pcireg_t command; 311 int error; 312 pcireg_t subid; 313 uint16_t subvendor; 314 pcireg_t reg; 315 int ioh_valid, ioh2_valid, memh_valid; 316 pcireg_t memtype; 317 pci_intr_handle_t ih; 318 const char *intrstr; 319 struct ahd_pci_busdata *bd; 320 321 ahd_set_name(ahd, ahd->sc_dev.dv_xname); 322 ahd->parent_dmat = pa->pa_dmat; 323 324 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 325 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 326 entry = ahd_find_pci_device(pa->pa_id, subid); 327 if (entry == NULL) 328 return; 329 330 /* Keep information about the PCI bus */ 331 bd = malloc(sizeof (struct ahd_pci_busdata), M_DEVBUF, M_NOWAIT); 332 if (bd == NULL) { 333 aprint_error("%s: unable to allocate bus-specific data\n", ahd_name(ahd)); 334 return; 335 } 336 memset(bd, 0, sizeof(struct ahd_pci_busdata)); 337 338 bd->pc = pa->pa_pc; 339 bd->tag = pa->pa_tag; 340 bd->func = pa->pa_function; 341 bd->dev = pa->pa_device; 342 343 ahd->bus_data = bd; 344 345 ahd->description = entry->name; 346 347 ahd->seep_config = malloc(sizeof(*ahd->seep_config), 348 M_DEVBUF, M_NOWAIT); 349 if (ahd->seep_config == NULL) { 350 aprint_error("%s: cannot malloc seep_config!\n", ahd_name(ahd)); 351 return; 352 } 353 memset(ahd->seep_config, 0, sizeof(*ahd->seep_config)); 354 355 LIST_INIT(&ahd->pending_scbs); 356 ahd_timer_init(&ahd->reset_timer); 357 ahd_timer_init(&ahd->stat_timer); 358 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A 359 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A; 360 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT; 361 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT; 362 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT; 363 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT; 364 ahd->int_coalescing_stop_threshold = AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT; 365 366 if (ahd_platform_alloc(ahd, NULL) != 0) { 367 ahd_free(ahd); 368 return; 369 } 370 371 /* 372 * Record if this is an HP board. 373 */ 374 subvendor = PCI_VENDOR(subid); 375 if (subvendor == SUBID_HP) 376 ahd->flags |= AHD_HP_BOARD; 377 378 error = entry->setup(ahd, pa); 379 if (error != 0) 380 return; 381 382 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 383 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 384 ahd->chip |= AHD_PCI; 385 /* Disable PCIX workarounds when running in PCI mode. */ 386 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 387 } else { 388 ahd->chip |= AHD_PCIX; 389 } 390 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 391 392 memh_valid = ioh_valid = ioh2_valid = 0; 393 394 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 395 &bd->pcix_off, NULL)) { 396 if (ahd->chip & AHD_PCIX) 397 aprint_error("%s: warning: can't find PCI-X capability\n", 398 ahd->sc_dev.dv_xname); 399 ahd->chip &= ~AHD_PCIX; 400 ahd->chip |= AHD_PCI; 401 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 402 } 403 404 /* 405 * Map PCI Registers 406 */ 407 if ((ahd->bugs & AHD_PCIX_MMAPIO_BUG) == 0) { 408 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 409 AHD_PCI_MEMADDR); 410 switch (memtype) { 411 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 412 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 413 memh_valid = (pci_mapreg_map(pa, AHD_PCI_MEMADDR, 414 memtype, 0, &ahd->tags[0], 415 &ahd->bshs[0], 416 NULL, NULL) == 0); 417 if (memh_valid) { 418 ahd->tags[1] = ahd->tags[0]; 419 bus_space_subregion(ahd->tags[0], ahd->bshs[0], 420 /*offset*/0x100, 421 /*size*/0x100, 422 &ahd->bshs[1]); 423 if (ahd_pci_test_register_access(ahd) != 0) 424 memh_valid = 0; 425 } 426 break; 427 default: 428 memh_valid = 0; 429 aprint_error("%s: unknown memory type: 0x%x\n", 430 ahd_name(ahd), memtype); 431 break; 432 } 433 434 if (memh_valid) { 435 command &= ~PCI_COMMAND_IO_ENABLE; 436 pci_conf_write(pa->pa_pc, pa->pa_tag, 437 PCI_COMMAND_STATUS_REG, command); 438 } 439 #ifdef AHD_DEBUG 440 printf("%s: doing memory mapping tag0 0x%x, tag1 0x%x, " 441 "shs0 0x%lx, shs1 0x%lx\n", 442 ahd_name(ahd), ahd->tags[0], ahd->tags[1], 443 ahd->bshs[0], ahd->bshs[1]); 444 #endif 445 } 446 447 if (command & PCI_COMMAND_IO_ENABLE) { 448 /* First BAR */ 449 ioh_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR, 450 PCI_MAPREG_TYPE_IO, 0, 451 &ahd->tags[0], &ahd->bshs[0], 452 NULL, NULL) == 0); 453 454 /* 2nd BAR */ 455 ioh2_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR1, 456 PCI_MAPREG_TYPE_IO, 0, 457 &ahd->tags[1], &ahd->bshs[1], 458 NULL, NULL) == 0); 459 460 if (ioh_valid && ioh2_valid) { 461 KASSERT(memh_valid == 0); 462 command &= ~PCI_COMMAND_MEM_ENABLE; 463 pci_conf_write(pa->pa_pc, pa->pa_tag, 464 PCI_COMMAND_STATUS_REG, command); 465 } 466 #ifdef AHD_DEBUG 467 printf("%s: doing io mapping tag0 0x%x, tag1 0x%x, " 468 "shs0 0x%lx, shs1 0x%lx\n", ahd_name(ahd), ahd->tags[0], 469 ahd->tags[1], ahd->bshs[0], ahd->bshs[1]); 470 #endif 471 472 } 473 474 if (memh_valid == 0 && (ioh_valid == 0 || ioh2_valid == 0)) { 475 aprint_error("%s: unable to map registers\n", ahd_name(ahd)); 476 return; 477 } 478 479 aprint_normal("\n"); 480 aprint_naive("\n"); 481 482 /* power up chip */ 483 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, ahd, 484 pci_activate_null)) && error != EOPNOTSUPP) { 485 aprint_error("%s: cannot activate %d\n", ahd->sc_dev.dv_xname, 486 error); 487 return; 488 } 489 /* 490 * Should we bother disabling 39Bit addressing 491 * based on installed memory? 492 */ 493 if (sizeof(bus_addr_t) > 4) 494 ahd->flags |= AHD_39BIT_ADDRESSING; 495 496 /* 497 * If we need to support high memory, enable dual 498 * address cycles. This bit must be set to enable 499 * high address bit generation even if we are on a 500 * 64bit bus (PCI64BIT set in devconfig). 501 */ 502 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 503 uint32_t dvconfig; 504 505 aprint_normal("%s: Enabling 39Bit Addressing\n", ahd_name(ahd)); 506 dvconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 507 dvconfig |= DACEN; 508 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, dvconfig); 509 } 510 511 /* Ensure busmastering is enabled */ 512 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 513 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 514 reg | PCI_COMMAND_MASTER_ENABLE); 515 516 ahd_softc_init(ahd); 517 518 /* 519 * Map the interrupt routines 520 */ 521 ahd->bus_intr = ahd_pci_intr; 522 523 error = ahd_reset(ahd, /*reinit*/FALSE); 524 if (error != 0) { 525 ahd_free(ahd); 526 return; 527 } 528 529 if (pci_intr_map(pa, &ih)) { 530 aprint_error("%s: couldn't map interrupt\n", ahd_name(ahd)); 531 ahd_free(ahd); 532 return; 533 } 534 intrstr = pci_intr_string(pa->pa_pc, ih); 535 ahd->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahd_intr, ahd); 536 if (ahd->ih == NULL) { 537 aprint_error("%s: couldn't establish interrupt", 538 ahd_name(ahd)); 539 if (intrstr != NULL) 540 aprint_error(" at %s", intrstr); 541 aprint_error("\n"); 542 ahd_free(ahd); 543 return; 544 } 545 if (intrstr != NULL) 546 aprint_normal("%s: interrupting at %s\n", ahd_name(ahd), 547 intrstr); 548 549 /* Get the size of the cache */ 550 ahd->pci_cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 551 ahd->pci_cachesize *= 4; 552 553 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 554 /* See if we have a SEEPROM and perform auto-term */ 555 error = ahd_check_extport(ahd); 556 if (error != 0) 557 return; 558 559 /* Core initialization */ 560 error = ahd_init(ahd); 561 if (error != 0) 562 return; 563 564 /* 565 * Link this softc in with all other ahd instances. 566 */ 567 ahd_attach(ahd); 568 } 569 570 CFATTACH_DECL(ahd_pci, sizeof(struct ahd_softc), 571 ahd_pci_probe, ahd_pci_attach, NULL, NULL); 572 573 /* 574 * Perform some simple tests that should catch situations where 575 * our registers are invalidly mapped. 576 */ 577 static int 578 ahd_pci_test_register_access(struct ahd_softc *ahd) 579 { 580 uint32_t cmd; 581 struct ahd_pci_busdata *bd = ahd->bus_data; 582 u_int targpcistat; 583 uint32_t pci_status1; 584 int error; 585 uint8_t hcntrl; 586 587 error = EIO; 588 589 /* 590 * Enable PCI error interrupt status, but suppress NMIs 591 * generated by SERR raised due to target aborts. 592 */ 593 cmd = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 594 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 595 cmd & ~PCI_COMMAND_SERR_ENABLE); 596 597 /* 598 * First a simple test to see if any 599 * registers can be read. Reading 600 * HCNTRL has no side effects and has 601 * at least one bit that is guaranteed to 602 * be zero so it is a good register to 603 * use for this test. 604 */ 605 hcntrl = ahd_inb(ahd, HCNTRL); 606 if (hcntrl == 0xFF) 607 goto fail; 608 609 /* 610 * Next create a situation where write combining 611 * or read prefetching could be initiated by the 612 * CPU or host bridge. Our device does not support 613 * either, so look for data corruption and/or flaged 614 * PCI errors. First pause without causing another 615 * chip reset. 616 */ 617 hcntrl &= ~CHIPRST; 618 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 619 while (ahd_is_paused(ahd) == 0) 620 ; 621 622 /* Clear any PCI errors that occurred before our driver attached. */ 623 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 624 targpcistat = ahd_inb(ahd, TARGPCISTAT); 625 ahd_outb(ahd, TARGPCISTAT, targpcistat); 626 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 627 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, pci_status1); 628 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 629 ahd_outb(ahd, CLRINT, CLRPCIINT); 630 631 ahd_outb(ahd, SEQCTL0, PERRORDIS); 632 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 633 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 634 goto fail; 635 636 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 637 u_int trgpcistat; 638 639 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 640 trgpcistat = ahd_inb(ahd, TARGPCISTAT); 641 if ((trgpcistat & STA) != 0) 642 goto fail; 643 } 644 645 error = 0; 646 647 fail: 648 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 649 650 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 651 targpcistat = ahd_inb(ahd, TARGPCISTAT); 652 653 /* Silently clear any latched errors. */ 654 ahd_outb(ahd, TARGPCISTAT, targpcistat); 655 pci_status1 = pci_conf_read(bd->pc, bd->tag, 656 PCI_COMMAND_STATUS_REG); 657 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 658 pci_status1); 659 ahd_outb(ahd, CLRINT, CLRPCIINT); 660 } 661 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 662 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, cmd); 663 return (error); 664 } 665 666 /* 667 * Check the external port logic for a serial eeprom 668 * and termination/cable detection contrls. 669 */ 670 static int 671 ahd_check_extport(struct ahd_softc *ahd) 672 { 673 struct vpd_config vpd; 674 struct seeprom_config *sc; 675 u_int adapter_control; 676 int have_seeprom; 677 int error; 678 679 sc = ahd->seep_config; 680 have_seeprom = ahd_acquire_seeprom(ahd); 681 if (have_seeprom) { 682 u_int start_addr; 683 684 /* 685 * Fetch VPD for this function and parse it. 686 */ 687 #ifdef AHD_DEBUG 688 printf("%s: Reading VPD from SEEPROM...", 689 ahd_name(ahd)); 690 #endif 691 /* Address is always in units of 16bit words */ 692 start_addr = ((2 * sizeof(*sc)) 693 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 694 695 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 696 start_addr, sizeof(vpd)/2, 697 /*bytestream*/TRUE); 698 if (error == 0) 699 error = ahd_parse_vpddata(ahd, &vpd); 700 #ifdef AHD_DEBUG 701 printf("%s: VPD parsing %s\n", 702 ahd_name(ahd), 703 error == 0 ? "successful" : "failed"); 704 #endif 705 706 #ifdef AHD_DEBUG 707 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 708 #endif 709 710 /* Address is always in units of 16bit words */ 711 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 712 713 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 714 start_addr, sizeof(*sc)/2, 715 /*bytestream*/FALSE); 716 717 if (error != 0) { 718 #ifdef AHD_DEBUG 719 printf("Unable to read SEEPROM\n"); 720 #endif 721 have_seeprom = 0; 722 } else { 723 have_seeprom = ahd_verify_cksum(sc); 724 #ifdef AHD_DEBUG 725 if (have_seeprom == 0) 726 printf ("checksum error\n"); 727 else 728 printf ("done.\n"); 729 #endif 730 } 731 ahd_release_seeprom(ahd); 732 } 733 734 if (!have_seeprom) { 735 u_int nvram_scb; 736 737 /* 738 * Pull scratch ram settings and treat them as 739 * if they are the contents of an seeprom if 740 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 741 * in SCB 0xFF. We manually compose the data as 16bit 742 * values to avoid endian issues. 743 */ 744 ahd_set_scbptr(ahd, 0xFF); 745 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 746 if (nvram_scb != 0xFF 747 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 748 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 749 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 750 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 751 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 752 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 753 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 754 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 755 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 756 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 757 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 758 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 759 uint16_t *sc_data; 760 int i; 761 762 ahd_set_scbptr(ahd, nvram_scb); 763 sc_data = (uint16_t *)sc; 764 for (i = 0; i < 64; i += 2) 765 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 766 have_seeprom = ahd_verify_cksum(sc); 767 if (have_seeprom) 768 ahd->flags |= AHD_SCB_CONFIG_USED; 769 } 770 } 771 772 #ifdef AHD_DEBUG 773 if ((have_seeprom != 0) && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 774 uint16_t *sc_data; 775 int i; 776 777 printf("%s: Seeprom Contents:", ahd_name(ahd)); 778 sc_data = (uint16_t *)sc; 779 for (i = 0; i < (sizeof(*sc)); i += 2) 780 printf("\n\t0x%.4x", sc_data[i]); 781 printf("\n"); 782 } 783 #endif 784 785 if (!have_seeprom) { 786 aprint_error("%s: No SEEPROM available.\n", ahd_name(ahd)); 787 ahd->flags |= AHD_USEDEFAULTS; 788 error = ahd_default_config(ahd); 789 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 790 free(ahd->seep_config, M_DEVBUF); 791 ahd->seep_config = NULL; 792 } else { 793 error = ahd_parse_cfgdata(ahd, sc); 794 adapter_control = sc->adapter_control; 795 } 796 if (error != 0) 797 return (error); 798 799 ahd_configure_termination(ahd, adapter_control); 800 801 return (0); 802 } 803 804 static void 805 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 806 { 807 int error; 808 u_int sxfrctl1; 809 uint8_t termctl; 810 uint32_t devconfig; 811 struct ahd_pci_busdata *bd = ahd->bus_data; 812 813 devconfig = pci_conf_read(bd->pc, bd->tag, DEVCONFIG); 814 devconfig &= ~STPWLEVEL; 815 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 816 devconfig |= STPWLEVEL; 817 #ifdef AHD_DEBUG 818 printf("%s: STPWLEVEL is %s\n", 819 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 820 #endif 821 pci_conf_write(bd->pc, bd->tag, DEVCONFIG, devconfig); 822 823 /* Make sure current sensing is off. */ 824 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 825 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 826 } 827 828 /* 829 * Read to sense. Write to set. 830 */ 831 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 832 if ((adapter_control & CFAUTOTERM) == 0) { 833 if (bootverbose) 834 printf("%s: Manual Primary Termination\n", 835 ahd_name(ahd)); 836 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 837 if ((adapter_control & CFSTERM) != 0) 838 termctl |= FLX_TERMCTL_ENPRILOW; 839 if ((adapter_control & CFWSTERM) != 0) 840 termctl |= FLX_TERMCTL_ENPRIHIGH; 841 } else if (error != 0) { 842 if (bootverbose) 843 printf("%s: Primary Auto-Term Sensing failed! " 844 "Using Defaults.\n", ahd_name(ahd)); 845 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 846 } 847 848 if ((adapter_control & CFSEAUTOTERM) == 0) { 849 if (bootverbose) 850 printf("%s: Manual Secondary Termination\n", 851 ahd_name(ahd)); 852 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 853 if ((adapter_control & CFSELOWTERM) != 0) 854 termctl |= FLX_TERMCTL_ENSECLOW; 855 if ((adapter_control & CFSEHIGHTERM) != 0) 856 termctl |= FLX_TERMCTL_ENSECHIGH; 857 } else if (error != 0) { 858 if (bootverbose) 859 printf("%s: Secondary Auto-Term Sensing failed! " 860 "Using Defaults.\n", ahd_name(ahd)); 861 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 862 } 863 864 /* 865 * Now set the termination based on what we found. 866 */ 867 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 868 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 869 ahd->flags |= AHD_TERM_ENB_A; 870 sxfrctl1 |= STPWEN; 871 } 872 /* Must set the latch once in order to be effective. */ 873 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 874 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 875 876 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 877 if (error != 0) { 878 aprint_error("%s: Unable to set termination settings!\n", 879 ahd_name(ahd)); 880 } else { 881 if (bootverbose) { 882 printf("%s: Primary High byte termination %sabled\n", 883 ahd_name(ahd), 884 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 885 886 printf("%s: Primary Low byte termination %sabled\n", 887 ahd_name(ahd), 888 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 889 890 printf("%s: Secondary High byte termination %sabled\n", 891 ahd_name(ahd), 892 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 893 894 printf("%s: Secondary Low byte termination %sabled\n", 895 ahd_name(ahd), 896 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 897 } 898 } 899 return; 900 } 901 902 #define DPE 0x80 903 #define SSE 0x40 904 #define RMA 0x20 905 #define RTA 0x10 906 #define STA 0x08 907 #define DPR 0x01 908 909 static const char *split_status_source[] = 910 { 911 "DFF0", 912 "DFF1", 913 "OVLY", 914 "CMC", 915 }; 916 917 static const char *pci_status_source[] = 918 { 919 "DFF0", 920 "DFF1", 921 "SG", 922 "CMC", 923 "OVLY", 924 "NONE", 925 "MSI", 926 "TARG" 927 }; 928 929 static const char *split_status_strings[] = 930 { 931 "%s: Received split response in %s.\n", 932 "%s: Received split completion error message in %s\n", 933 "%s: Receive overrun in %s\n", 934 "%s: Count not complete in %s\n", 935 "%s: Split completion data bucket in %s\n", 936 "%s: Split completion address error in %s\n", 937 "%s: Split completion byte count error in %s\n", 938 "%s: Signaled Target-abort to early terminate a split in %s\n" 939 }; 940 941 static const char *pci_status_strings[] = 942 { 943 "%s: Data Parity Error has been reported via PERR# in %s\n", 944 "%s: Target initial wait state error in %s\n", 945 "%s: Split completion read data parity error in %s\n", 946 "%s: Split completion address attribute parity error in %s\n", 947 "%s: Received a Target Abort in %s\n", 948 "%s: Received a Master Abort in %s\n", 949 "%s: Signal System Error Detected in %s\n", 950 "%s: Address or Write Phase Parity Error Detected in %s.\n" 951 }; 952 953 static int 954 ahd_pci_intr(struct ahd_softc *ahd) 955 { 956 uint8_t pci_status[8]; 957 ahd_mode_state saved_modes; 958 u_int pci_status1; 959 u_int intstat; 960 u_int i; 961 u_int reg; 962 struct ahd_pci_busdata *bd = ahd->bus_data; 963 964 intstat = ahd_inb(ahd, INTSTAT); 965 966 if ((intstat & SPLTINT) != 0) 967 ahd_pci_split_intr(ahd, intstat); 968 969 if ((intstat & PCIINT) == 0) 970 return 0; 971 972 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 973 saved_modes = ahd_save_modes(ahd); 974 ahd_dump_card_state(ahd); 975 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 976 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 977 978 if (i == 5) 979 continue; 980 pci_status[i] = ahd_inb(ahd, reg); 981 /* Clear latched errors. So our interrupt deasserts. */ 982 ahd_outb(ahd, reg, pci_status[i]); 983 } 984 985 for (i = 0; i < 8; i++) { 986 u_int bit; 987 988 if (i == 5) 989 continue; 990 991 for (bit = 0; bit < 8; bit++) { 992 993 if ((pci_status[i] & (0x1 << bit)) != 0) { 994 static const char *s; 995 996 s = pci_status_strings[bit]; 997 if (i == 7/*TARG*/ && bit == 3) 998 s = "%s: Signaled Target Abort\n"; 999 printf(s, ahd_name(ahd), pci_status_source[i]); 1000 } 1001 } 1002 } 1003 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 1004 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG , pci_status1); 1005 1006 ahd_restore_modes(ahd, saved_modes); 1007 ahd_outb(ahd, CLRINT, CLRPCIINT); 1008 ahd_unpause(ahd); 1009 1010 return 1; 1011 } 1012 1013 static void 1014 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat __unused) 1015 { 1016 uint8_t split_status[4]; 1017 uint8_t split_status1[4]; 1018 uint8_t sg_split_status[2]; 1019 uint8_t sg_split_status1[2]; 1020 ahd_mode_state saved_modes; 1021 u_int i; 1022 pcireg_t pcix_status; 1023 struct ahd_pci_busdata *bd = ahd->bus_data; 1024 1025 /* 1026 * Check for splits in all modes. Modes 0 and 1 1027 * additionally have SG engine splits to look at. 1028 */ 1029 pcix_status = pci_conf_read(bd->pc, bd->tag, 1030 bd->pcix_off + PCI_PCIX_STATUS); 1031 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 1032 ahd_name(ahd), pcix_status); 1033 1034 saved_modes = ahd_save_modes(ahd); 1035 for (i = 0; i < 4; i++) { 1036 ahd_set_modes(ahd, i, i); 1037 1038 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 1039 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 1040 /* Clear latched errors. So our interrupt deasserts. */ 1041 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 1042 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 1043 if (i > 1) 1044 continue; 1045 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 1046 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 1047 /* Clear latched errors. So our interrupt deasserts. */ 1048 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 1049 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 1050 } 1051 1052 for (i = 0; i < 4; i++) { 1053 u_int bit; 1054 1055 for (bit = 0; bit < 8; bit++) { 1056 1057 if ((split_status[i] & (0x1 << bit)) != 0) { 1058 static const char *s; 1059 1060 s = split_status_strings[bit]; 1061 printf(s, ahd_name(ahd), 1062 split_status_source[i]); 1063 } 1064 1065 if (i > 0) 1066 continue; 1067 1068 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 1069 static const char *s; 1070 1071 s = split_status_strings[bit]; 1072 printf(s, ahd_name(ahd), "SG"); 1073 } 1074 } 1075 } 1076 /* 1077 * Clear PCI-X status bits. 1078 */ 1079 pci_conf_write(bd->pc, bd->tag, bd->pcix_off + PCI_PCIX_STATUS, 1080 pcix_status); 1081 ahd_outb(ahd, CLRINT, CLRSPLTINT); 1082 ahd_restore_modes(ahd, saved_modes); 1083 } 1084 1085 static int 1086 ahd_aic7901_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1087 { 1088 1089 ahd->chip = AHD_AIC7901; 1090 ahd->features = AHD_AIC7901_FE; 1091 return (ahd_aic790X_setup(ahd, pa)); 1092 } 1093 1094 static int 1095 ahd_aic7901A_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1096 { 1097 1098 ahd->chip = AHD_AIC7901A; 1099 ahd->features = AHD_AIC7901A_FE; 1100 return (ahd_aic790X_setup(ahd, pa)); 1101 } 1102 1103 static int 1104 ahd_aic7902_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1105 { 1106 1107 ahd->chip = AHD_AIC7902; 1108 ahd->features = AHD_AIC7902_FE; 1109 return (ahd_aic790X_setup(ahd, pa)); 1110 } 1111 1112 static int 1113 ahd_aic790X_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1114 { 1115 u_int rev; 1116 1117 rev = PCI_REVISION(pa->pa_class); 1118 #ifdef AHD_DEBUG 1119 printf("\n%s: aic7902 chip revision 0x%x\n", ahd_name(ahd), rev); 1120 #endif 1121 if (rev < ID_AIC7902_PCI_REV_A4) { 1122 aprint_error("%s: Unable to attach to unsupported chip revision %d\n", 1123 ahd_name(ahd), rev); 1124 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 0); 1125 return (ENXIO); 1126 } 1127 1128 ahd->channel = (pa->pa_function == 1) ? 'B' : 'A'; 1129 if (rev < ID_AIC7902_PCI_REV_B0) { 1130 /* 1131 * Enable A series workarounds. 1132 */ 1133 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 1134 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 1135 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 1136 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 1137 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 1138 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 1139 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 1140 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 1141 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 1142 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 1143 | AHD_FAINT_LED_BUG; 1144 1145 1146 /* 1147 * IO Cell parameter setup. 1148 */ 1149 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1150 1151 if ((ahd->flags & AHD_HP_BOARD) == 0) 1152 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 1153 } else { 1154 u_int devconfig1; 1155 1156 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1157 | AHD_NEW_DFCNTRL_OPTS; 1158 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; 1159 1160 /* 1161 * Some issues have been resolved in the 7901B. 1162 */ 1163 if ((ahd->features & AHD_MULTI_FUNC) != 0) 1164 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG; 1165 1166 /* 1167 * IO Cell parameter setup. 1168 */ 1169 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1170 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1171 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1172 1173 /* 1174 * Set the PREQDIS bit for H2B which disables some workaround 1175 * that doesn't work on regular PCI busses. 1176 * XXX - Find out exactly what this does from the hardware 1177 * folks! 1178 */ 1179 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1180 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG1, devconfig1|PREQDIS); 1181 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1182 } 1183 1184 return (0); 1185 } 1186
Indexes created Sun Sep 21 20:09:37 GMT 2025