ahd_pci.c revision 1.7
1 /* $NetBSD: ahd_pci.c,v 1.7 2003/09/02 20:59:51 fvdl Exp $ */ 2 3 /* 4 * Product specific probe and attach routines for: 5 * aic7901 and aic7902 SCSI controllers 6 * 7 * Copyright (c) 1994-2001 Justin T. Gibbs. 8 * Copyright (c) 2000-2002 Adaptec Inc. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * substantially similar to the "NO WARRANTY" disclaimer below 19 * ("Disclaimer") and any redistribution must be conditioned upon 20 * including a substantially similar Disclaimer requirement for further 21 * binary redistribution. 22 * 3. Neither the names of the above-listed copyright holders nor the names 23 * of any contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * Alternatively, this software may be distributed under the terms of the 27 * GNU General Public License ("GPL") version 2 as published by the Free 28 * Software Foundation. 29 * 30 * NO WARRANTY 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGES. 42 * 43 * Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#76 $ 44 * 45 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx_pci.c,v 1.14 2003/06/28 04:39:49 gibbs Exp $ 46 */ 47 /* 48 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: ahd_pci.c,v 1.7 2003/09/02 20:59:51 fvdl Exp $"); 53 54 #define AHD_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 55 #define AHD_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 56 57 #include <dev/ic/aic79xx_osm.h> 58 #include <dev/ic/aic79xx_inline.h> 59 60 static __inline uint64_t 61 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 62 { 63 uint64_t id; 64 65 id = subvendor 66 | (subdevice << 16) 67 | ((uint64_t)vendor << 32) 68 | ((uint64_t)device << 48); 69 70 return (id); 71 } 72 73 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 74 #define ID_ALL_IROC_MASK 0xFFFFFF7FFFFFFFFFull 75 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 76 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 77 #define ID_9005_GENERIC_IROC_MASK 0xFFF0FF7F00000000ull 78 79 #define ID_AIC7901 0x800F9005FFFF9005ull 80 #define ID_AHA_29320A 0x8000900500609005ull 81 #define ID_AHA_29320ALP 0x8017900500449005ull 82 83 #define ID_AIC7901A 0x801E9005FFFF9005ull 84 #define ID_AHA_29320 0x8012900500429005ull 85 #define ID_AHA_29320B 0x8013900500439005ull 86 #define ID_AHA_29320LP 0x8014900500449005ull 87 88 #define ID_AIC7902 0x801F9005FFFF9005ull 89 #define ID_AIC7902_B 0x801D9005FFFF9005ull 90 #define ID_AHA_39320 0x8010900500409005ull 91 #define ID_AHA_39320_B 0x8015900500409005ull 92 #define ID_AHA_39320A 0x8016900500409005ull 93 #define ID_AHA_39320D 0x8011900500419005ull 94 #define ID_AHA_39320D_B 0x801C900500419005ull 95 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull 96 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 97 #define ID_AIC7902_PCI_REV_A4 0x3 98 #define ID_AIC7902_PCI_REV_B0 0x10 99 #define SUBID_HP 0x0E11 100 101 #define DEVID_9005_TYPE(id) ((id) & 0xF) 102 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 103 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 104 #define DEVID_9005_TYPE_IROC 0x8 /* Raid(0,1,10) Card */ 105 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 106 107 #define DEVID_9005_MFUNC(id) ((id) & 0x10) 108 109 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 110 111 #define SUBID_9005_TYPE(id) ((id) & 0xF) 112 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 113 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 114 115 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 116 117 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 118 119 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 120 #define SUBID_9005_SEEPTYPE_NONE 0x0 121 #define SUBID_9005_SEEPTYPE_4K 0x1 122 123 static ahd_device_setup_t ahd_aic7901_setup; 124 static ahd_device_setup_t ahd_aic7901A_setup; 125 static ahd_device_setup_t ahd_aic7902_setup; 126 static ahd_device_setup_t ahd_aic790X_setup; 127 128 struct ahd_pci_identity ahd_pci_ident_table [] = 129 { 130 /* aic7901 based controllers */ 131 { 132 ID_AHA_29320A, 133 ID_ALL_MASK, 134 "Adaptec 29320A Ultra320 SCSI adapter", 135 ahd_aic7901_setup 136 }, 137 { 138 ID_AHA_29320ALP, 139 ID_ALL_MASK, 140 "Adaptec 29320ALP Ultra320 SCSI adapter", 141 ahd_aic7901_setup 142 }, 143 /* aic7901A based controllers */ 144 { 145 ID_AHA_29320, 146 ID_ALL_MASK, 147 "Adaptec 29320 Ultra320 SCSI adapter", 148 ahd_aic7901A_setup 149 }, 150 { 151 ID_AHA_29320B, 152 ID_ALL_MASK, 153 "Adaptec 29320B Ultra320 SCSI adapter", 154 ahd_aic7901A_setup 155 }, 156 { 157 ID_AHA_29320LP, 158 ID_ALL_MASK, 159 "Adaptec 29320LP Ultra320 SCSI adapter", 160 ahd_aic7901A_setup 161 }, 162 /* aic7902 based controllers */ 163 { 164 ID_AHA_39320, 165 ID_ALL_MASK, 166 "Adaptec 39320 Ultra320 SCSI adapter", 167 ahd_aic7902_setup 168 }, 169 { 170 ID_AHA_39320_B, 171 ID_ALL_MASK, 172 "Adaptec 39320 Ultra320 SCSI adapter", 173 ahd_aic7902_setup 174 }, 175 { 176 ID_AHA_39320A, 177 ID_ALL_MASK, 178 "Adaptec 39320A Ultra320 SCSI adapter", 179 ahd_aic7902_setup 180 }, 181 { 182 ID_AHA_39320D, 183 ID_ALL_MASK, 184 "Adaptec 39320D Ultra320 SCSI adapter", 185 ahd_aic7902_setup 186 }, 187 { 188 ID_AHA_39320D_HP, 189 ID_ALL_MASK, 190 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 191 ahd_aic7902_setup 192 }, 193 { 194 ID_AHA_39320D_B, 195 ID_ALL_MASK, 196 "Adaptec 39320D Ultra320 SCSI adapter", 197 ahd_aic7902_setup 198 }, 199 { 200 ID_AHA_39320D_B_HP, 201 ID_ALL_MASK, 202 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 203 ahd_aic7902_setup 204 }, 205 { 206 ID_AHA_29320, 207 ID_ALL_MASK, 208 "Adaptec 29320 Ultra320 SCSI adapter", 209 ahd_aic7902_setup 210 }, 211 { 212 ID_AHA_29320B, 213 ID_ALL_MASK, 214 "Adaptec 29320B Ultra320 SCSI adapter", 215 ahd_aic7902_setup 216 }, 217 /* Generic chip probes for devices we don't know 'exactly' */ 218 { 219 ID_AIC7901 & ID_DEV_VENDOR_MASK, 220 ID_DEV_VENDOR_MASK, 221 "Adaptec AIC7901 Ultra320 SCSI adapter", 222 ahd_aic7901_setup 223 }, 224 { 225 ID_AIC7901A & ID_DEV_VENDOR_MASK, 226 ID_DEV_VENDOR_MASK, 227 "Adaptec AIC7901A Ultra320 SCSI adapter", 228 ahd_aic7901A_setup 229 }, 230 { 231 ID_AIC7902 & ID_9005_GENERIC_MASK, 232 ID_9005_GENERIC_MASK, 233 "Adaptec AIC7902 Ultra320 SCSI adapter", 234 ahd_aic7902_setup 235 } 236 }; 237 238 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 239 240 #define DEVCONFIG 0x40 241 #define PCIXINITPAT 0x0000E000ul 242 #define PCIXINIT_PCI33_66 0x0000E000ul 243 #define PCIXINIT_PCIX50_66 0x0000C000ul 244 #define PCIXINIT_PCIX66_100 0x0000A000ul 245 #define PCIXINIT_PCIX100_133 0x00008000ul 246 #define PCI_BUS_MODES_INDEX(devconfig) \ 247 (((devconfig) & PCIXINITPAT) >> 13) 248 249 static const char *pci_bus_modes[] = 250 { 251 "PCI bus mode unknown", 252 "PCI bus mode unknown", 253 "PCI bus mode unknown", 254 "PCI bus mode unknown", 255 "PCI-X 101-133Mhz", 256 "PCI-X 67-100Mhz", 257 "PCI-X 50-66Mhz", 258 "PCI 33 or 66Mhz" 259 }; 260 261 #define TESTMODE 0x00000800ul 262 #define IRDY_RST 0x00000200ul 263 #define FRAME_RST 0x00000100ul 264 #define PCI64BIT 0x00000080ul 265 #define MRDCEN 0x00000040ul 266 #define ENDIANSEL 0x00000020ul 267 #define MIXQWENDIANEN 0x00000008ul 268 #define DACEN 0x00000004ul 269 #define STPWLEVEL 0x00000002ul 270 #define QWENDIANSEL 0x00000001ul 271 272 #define DEVCONFIG1 0x44 273 #define PREQDIS 0x01 274 275 #define LATTIME 0x0000ff00ul 276 277 int ahd_pci_probe __P((struct device *, struct cfdata *, void *)); 278 void ahd_pci_attach __P((struct device *, struct device *, void *)); 279 280 CFATTACH_DECL(ahd_pci, sizeof(struct ahd_softc), 281 ahd_pci_probe, ahd_pci_attach, NULL, NULL); 282 283 static int ahd_check_extport(struct ahd_softc *ahd); 284 static void ahd_configure_termination(struct ahd_softc *ahd, 285 u_int adapter_control); 286 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 287 288 const struct ahd_pci_identity * 289 ahd_find_pci_device(id, subid) 290 pcireg_t id, subid; 291 { 292 u_int64_t full_id; 293 const struct ahd_pci_identity *entry; 294 u_int i; 295 296 full_id = ahd_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 297 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 298 299 for (i = 0; i < ahd_num_pci_devs; i++) { 300 entry = &ahd_pci_ident_table[i]; 301 if (entry->full_id == (full_id & entry->id_mask)) 302 return (entry); 303 } 304 return (NULL); 305 } 306 307 int 308 ahd_pci_probe(parent, match, aux) 309 struct device *parent; 310 struct cfdata *match; 311 void *aux; 312 { 313 struct pci_attach_args *pa = aux; 314 const struct ahd_pci_identity *entry; 315 pcireg_t subid; 316 317 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 318 entry = ahd_find_pci_device(pa->pa_id, subid); 319 return entry != NULL ? 1 : 0; 320 } 321 322 void 323 ahd_pci_attach(parent, self, aux) 324 struct device *parent, *self; 325 void *aux; 326 { 327 struct pci_attach_args *pa = aux; 328 struct ahd_softc *ahd = (void *)self; 329 330 const struct ahd_pci_identity *entry; 331 332 uint32_t devconfig; 333 pcireg_t command; 334 int error; 335 pcireg_t subid; 336 uint16_t subvendor; 337 int pci_pwrmgmt_cap_reg; 338 int pci_pwrmgmt_csr_reg; 339 pcireg_t reg; 340 int ioh_valid, ioh2_valid, memh_valid; 341 pcireg_t memtype; 342 pci_intr_handle_t ih; 343 const char *intrstr; 344 struct ahd_pci_busdata *bd; 345 346 ahd_set_name(ahd, ahd->sc_dev.dv_xname); 347 ahd->parent_dmat = pa->pa_dmat; 348 349 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 350 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 351 entry = ahd_find_pci_device(pa->pa_id, subid); 352 if (entry == NULL) 353 return; 354 355 /* Keep information about the PCI bus */ 356 bd = malloc(sizeof (struct ahd_pci_busdata), M_DEVBUF, M_NOWAIT); 357 if (bd == NULL) { 358 printf("%s: unable to allocate bus-specific data\n", ahd_name(ahd)); 359 return; 360 } 361 memset(bd, 0, sizeof(struct ahd_pci_busdata)); 362 363 bd->pc = pa->pa_pc; 364 bd->tag = pa->pa_tag; 365 bd->func = pa->pa_function; 366 bd->dev = pa->pa_device; 367 368 ahd->bus_data = bd; 369 370 ahd->description = entry->name; 371 372 ahd->seep_config = malloc(sizeof(*ahd->seep_config), 373 M_DEVBUF, M_NOWAIT); 374 if (ahd->seep_config == NULL) { 375 printf("%s: cannot malloc seep_config!\n", ahd_name(ahd)); 376 return; 377 } 378 memset(ahd->seep_config, 0, sizeof(*ahd->seep_config)); 379 380 LIST_INIT(&ahd->pending_scbs); 381 ahd_timer_init(&ahd->reset_timer); 382 ahd_timer_init(&ahd->stat_timer); 383 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT; 384 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT; 385 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT; 386 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT; 387 ahd->int_coalescing_stop_threshold = AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT; 388 389 if (ahd_platform_alloc(ahd, NULL) != 0) { 390 ahd_free(ahd); 391 return; 392 } 393 394 /* 395 * Record if this is an HP board. 396 */ 397 subvendor = PCI_VENDOR(subid); 398 if (subvendor == SUBID_HP) 399 ahd->flags |= AHD_HP_BOARD; 400 401 error = entry->setup(ahd, pa); 402 if (error != 0) 403 return; 404 405 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 406 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66 || 407 (devconfig & PCIXINITPAT) == PCIXINIT_PCIX66_100) { 408 ahd->chip |= AHD_PCI; 409 /* Disable PCIX workarounds when running in PCI mode. */ 410 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 411 } else { 412 ahd->chip |= AHD_PCIX; 413 } 414 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 415 416 memh_valid = ioh_valid = ioh2_valid = 0; 417 418 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 419 &bd->pcix_off, NULL)) { 420 if (ahd->chip & AHD_PCIX) 421 printf("%s: warning: can't find PCI-X capability\n", 422 ahd->sc_dev.dv_xname); 423 ahd->chip &= ~AHD_PCIX; 424 ahd->chip |= AHD_PCI; 425 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 426 } 427 428 /* 429 * Map PCI Registers 430 */ 431 if ((command & (PCI_COMMAND_MEM_ENABLE)) != 0) { 432 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHD_PCI_MEMADDR); 433 switch (memtype) { 434 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 435 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 436 memh_valid = (pci_mapreg_map(pa, AHD_PCI_MEMADDR, 437 memtype, 0, &ahd->tags[0], 438 &ahd->bshs[0], NULL, NULL) == 0); 439 440 ahd->tags[1] = ahd->tags[0]; 441 442 bus_space_subregion(ahd->tags[0], ahd->bshs[0], 443 /*offset*/0x100, 444 /*size*/0x100, 445 &ahd->bshs[1]); 446 break; 447 default: 448 printf("%s: unable to map memory registers\n", ahd_name(ahd)); 449 return; 450 } 451 452 if (memh_valid) { 453 command &= ~PCI_COMMAND_IO_ENABLE; 454 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 455 } 456 #ifdef AHD_DEBUG 457 printf("%s: doing memory mapping tag0 0x%x, tag1 0x%x, shs0 0x%lx, shs1 0x%lx\n", 458 ahd_name(ahd), ahd->tags[0], ahd->tags[1], ahd->bshs[0], ahd->bshs[1]); 459 #endif 460 } 461 462 if ((command & (PCI_COMMAND_IO_ENABLE)) != 0 && 463 !(ahd->bugs & AHD_PCIX_MMAPIO_BUG)) { 464 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHD_PCI_IOADDR); 465 466 /* First BAR */ 467 ioh_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR, 468 memtype, 0, &ahd->tags[0], 469 &ahd->bshs[0], NULL, NULL) == 0); 470 471 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHD_PCI_IOADDR1); 472 473 /* 2nd BAR */ 474 ioh2_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR1, 475 memtype, 0, &ahd->tags[1], 476 &ahd->bshs[1], NULL, NULL) == 0); 477 478 if (ioh_valid && ioh2_valid) { 479 command &= ~PCI_COMMAND_MEM_ENABLE; 480 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 481 } 482 #ifdef AHD_DEBUG 483 printf("%s: doing io mapping tag0 0x%x, tag1 0x%x, shs0 0x%lx, shs1 0x%lx\n", 484 ahd_name(ahd), ahd->tags[0], ahd->tags[1], ahd->bshs[0], ahd->bshs[1]); 485 #endif 486 487 } 488 489 if ((memh_valid == 0) && ((ioh_valid == 0) || (ioh2_valid == 0))) { 490 printf("%s: unable to map memory registers\n", ahd_name(ahd)); 491 return; 492 } 493 494 printf("\n"); 495 496 /* 497 * Set Power State D0. 498 */ 499 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 500 &pci_pwrmgmt_cap_reg, 0)) { 501 502 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 503 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 504 pci_pwrmgmt_csr_reg); 505 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 506 pci_conf_write(pa->pa_pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 507 (reg & ~PCI_PMCSR_STATE_MASK) | 508 PCI_PMCSR_STATE_D0); 509 } 510 } 511 512 /* 513 * Should we bother disabling 39Bit addressing 514 * based on installed memory? 515 */ 516 if (sizeof(bus_addr_t) > 4) 517 ahd->flags |= AHD_39BIT_ADDRESSING; 518 519 /* 520 * If we need to support high memory, enable dual 521 * address cycles. This bit must be set to enable 522 * high address bit generation even if we are on a 523 * 64bit bus (PCI64BIT set in devconfig). 524 */ 525 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 526 uint32_t devconfig; 527 528 printf("%s: Enabling 39Bit Addressing\n", ahd_name(ahd)); 529 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 530 devconfig |= DACEN; 531 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); 532 } 533 534 /* Ensure busmastering is enabled */ 535 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 536 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 537 reg | PCI_COMMAND_MASTER_ENABLE); 538 539 ahd_softc_init(ahd); 540 541 /* 542 * Map the interrupt routines 543 */ 544 ahd->bus_intr = ahd_pci_intr; 545 546 if (pci_intr_map(pa, &ih)) { 547 printf("%s: couldn't map interrupt\n", ahd_name(ahd)); 548 ahd_free(ahd); 549 return; 550 } 551 intrstr = pci_intr_string(pa->pa_pc, ih); 552 ahd->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahd_intr, ahd); 553 if (ahd->ih == NULL) { 554 printf("%s: couldn't establish interrupt", 555 ahd_name(ahd)); 556 if (intrstr != NULL) 557 printf(" at %s", intrstr); 558 printf("\n"); 559 ahd_free(ahd); 560 return; 561 } 562 if (intrstr != NULL) 563 printf("%s: interrupting at %s\n", ahd_name(ahd), 564 intrstr); 565 566 /* Get the size of the cache */ 567 ahd->pci_cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 568 ahd->pci_cachesize *= 4; 569 570 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 571 /* See if we have a SEEPROM and perform auto-term */ 572 error = ahd_check_extport(ahd); 573 if (error != 0) 574 return; 575 576 /* Core initialization */ 577 error = ahd_init(ahd); 578 if (error != 0) 579 return; 580 581 /* 582 * Link this softc in with all other ahd instances. 583 */ 584 ahd_attach(ahd); 585 586 return; 587 } 588 589 590 /* 591 * Check the external port logic for a serial eeprom 592 * and termination/cable detection contrls. 593 */ 594 static int 595 ahd_check_extport(struct ahd_softc *ahd) 596 { 597 struct vpd_config vpd; 598 struct seeprom_config *sc; 599 u_int adapter_control; 600 int have_seeprom; 601 int error; 602 603 sc = ahd->seep_config; 604 have_seeprom = ahd_acquire_seeprom(ahd); 605 if (have_seeprom) { 606 u_int start_addr; 607 608 /* 609 * Fetch VPD for this function and parse it. 610 */ 611 #ifdef AHD_DEBUG 612 printf("%s: Reading VPD from SEEPROM...", 613 ahd_name(ahd)); 614 #endif 615 /* Address is always in units of 16bit words */ 616 start_addr = ((2 * sizeof(*sc)) 617 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 618 619 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 620 start_addr, sizeof(vpd)/2, 621 /*bytestream*/TRUE); 622 if (error == 0) 623 error = ahd_parse_vpddata(ahd, &vpd); 624 #ifdef AHD_DEBUG 625 printf("%s: VPD parsing %s\n", 626 ahd_name(ahd), 627 error == 0 ? "successful" : "failed"); 628 #endif 629 630 #ifdef AHD_DEBUG 631 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 632 #endif 633 634 /* Address is always in units of 16bit words */ 635 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 636 637 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 638 start_addr, sizeof(*sc)/2, 639 /*bytestream*/FALSE); 640 641 if (error != 0) { 642 #ifdef AHD_DEBUG 643 printf("Unable to read SEEPROM\n"); 644 #endif 645 have_seeprom = 0; 646 } else { 647 have_seeprom = ahd_verify_cksum(sc); 648 #ifdef AHD_DEBUG 649 if (have_seeprom == 0) 650 printf ("checksum error\n"); 651 else 652 printf ("done.\n"); 653 #endif 654 } 655 ahd_release_seeprom(ahd); 656 } 657 658 if (!have_seeprom) { 659 u_int nvram_scb; 660 661 /* 662 * Pull scratch ram settings and treat them as 663 * if they are the contents of an seeprom if 664 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 665 * in SCB 0xFF. We manually compose the data as 16bit 666 * values to avoid endian issues. 667 */ 668 ahd_set_scbptr(ahd, 0xFF); 669 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 670 if (nvram_scb != 0xFF 671 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 672 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 673 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 674 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 675 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 676 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 677 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 678 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 679 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 680 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 681 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 682 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 683 uint16_t *sc_data; 684 int i; 685 686 ahd_set_scbptr(ahd, nvram_scb); 687 sc_data = (uint16_t *)sc; 688 for (i = 0; i < 64; i += 2) 689 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 690 have_seeprom = ahd_verify_cksum(sc); 691 if (have_seeprom) 692 ahd->flags |= AHD_SCB_CONFIG_USED; 693 } 694 } 695 696 #ifdef AHD_DEBUG 697 if ((have_seeprom != 0) && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 698 uint16_t *sc_data; 699 int i; 700 701 printf("%s: Seeprom Contents:", ahd_name(ahd)); 702 sc_data = (uint16_t *)sc; 703 for (i = 0; i < (sizeof(*sc)); i += 2) 704 printf("\n\t0x%.4x", sc_data[i]); 705 printf("\n"); 706 } 707 #endif 708 709 if (!have_seeprom) { 710 printf("%s: No SEEPROM available.\n", ahd_name(ahd)); 711 ahd->flags |= AHD_USEDEFAULTS; 712 error = ahd_default_config(ahd); 713 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 714 free(ahd->seep_config, M_DEVBUF); 715 ahd->seep_config = NULL; 716 } else { 717 error = ahd_parse_cfgdata(ahd, sc); 718 adapter_control = sc->adapter_control; 719 } 720 if (error != 0) 721 return (error); 722 723 ahd_configure_termination(ahd, adapter_control); 724 725 return (0); 726 } 727 728 static void 729 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 730 { 731 int error; 732 u_int sxfrctl1; 733 uint8_t termctl; 734 uint32_t devconfig; 735 struct ahd_pci_busdata *bd = ahd->bus_data; 736 737 devconfig = pci_conf_read(bd->pc, bd->tag, DEVCONFIG); 738 devconfig &= ~STPWLEVEL; 739 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 740 devconfig |= STPWLEVEL; 741 #ifdef AHD_DEBUG 742 printf("%s: STPWLEVEL is %s\n", 743 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 744 #endif 745 pci_conf_write(bd->pc, bd->tag, DEVCONFIG, devconfig); 746 747 /* Make sure current sensing is off. */ 748 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 749 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 750 } 751 752 /* 753 * Read to sense. Write to set. 754 */ 755 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 756 if ((adapter_control & CFAUTOTERM) == 0) { 757 if (bootverbose) 758 printf("%s: Manual Primary Termination\n", 759 ahd_name(ahd)); 760 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 761 if ((adapter_control & CFSTERM) != 0) 762 termctl |= FLX_TERMCTL_ENPRILOW; 763 if ((adapter_control & CFWSTERM) != 0) 764 termctl |= FLX_TERMCTL_ENPRIHIGH; 765 } else if (error != 0) { 766 if (bootverbose) 767 printf("%s: Primary Auto-Term Sensing failed! " 768 "Using Defaults.\n", ahd_name(ahd)); 769 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 770 } 771 772 if ((adapter_control & CFSEAUTOTERM) == 0) { 773 if (bootverbose) 774 printf("%s: Manual Secondary Termination\n", 775 ahd_name(ahd)); 776 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 777 if ((adapter_control & CFSELOWTERM) != 0) 778 termctl |= FLX_TERMCTL_ENSECLOW; 779 if ((adapter_control & CFSEHIGHTERM) != 0) 780 termctl |= FLX_TERMCTL_ENSECHIGH; 781 } else if (error != 0) { 782 if (bootverbose) 783 printf("%s: Secondary Auto-Term Sensing failed! " 784 "Using Defaults.\n", ahd_name(ahd)); 785 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 786 } 787 788 /* 789 * Now set the termination based on what we found. 790 */ 791 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 792 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 793 ahd->flags |= AHD_TERM_ENB_A; 794 sxfrctl1 |= STPWEN; 795 } 796 /* Must set the latch once in order to be effective. */ 797 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 798 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 799 800 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 801 if (error != 0) { 802 printf("%s: Unable to set termination settings!\n", 803 ahd_name(ahd)); 804 } else { 805 if (bootverbose) { 806 printf("%s: Primary High byte termination %sabled\n", 807 ahd_name(ahd), 808 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 809 810 printf("%s: Primary Low byte termination %sabled\n", 811 ahd_name(ahd), 812 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 813 814 printf("%s: Secondary High byte termination %sabled\n", 815 ahd_name(ahd), 816 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 817 818 printf("%s: Secondary Low byte termination %sabled\n", 819 ahd_name(ahd), 820 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 821 } 822 } 823 return; 824 } 825 826 #define DPE 0x80 827 #define SSE 0x40 828 #define RMA 0x20 829 #define RTA 0x10 830 #define STA 0x08 831 #define DPR 0x01 832 833 static const char *split_status_source[] = 834 { 835 "DFF0", 836 "DFF1", 837 "OVLY", 838 "CMC", 839 }; 840 841 static const char *pci_status_source[] = 842 { 843 "DFF0", 844 "DFF1", 845 "SG", 846 "CMC", 847 "OVLY", 848 "NONE", 849 "MSI", 850 "TARG" 851 }; 852 853 static const char *split_status_strings[] = 854 { 855 "%s: Received split response in %s.\n", 856 "%s: Received split completion error message in %s\n", 857 "%s: Receive overrun in %s\n", 858 "%s: Count not complete in %s\n", 859 "%s: Split completion data bucket in %s\n", 860 "%s: Split completion address error in %s\n", 861 "%s: Split completion byte count error in %s\n", 862 "%s: Signaled Target-abort to early terminate a split in %s\n" 863 }; 864 865 static const char *pci_status_strings[] = 866 { 867 "%s: Data Parity Error has been reported via PERR# in %s\n", 868 "%s: Target initial wait state error in %s\n", 869 "%s: Split completion read data parity error in %s\n", 870 "%s: Split completion address attribute parity error in %s\n", 871 "%s: Received a Target Abort in %s\n", 872 "%s: Received a Master Abort in %s\n", 873 "%s: Signal System Error Detected in %s\n", 874 "%s: Address or Write Phase Parity Error Detected in %s.\n" 875 }; 876 877 int 878 ahd_pci_intr(struct ahd_softc *ahd) 879 { 880 uint8_t pci_status[8]; 881 ahd_mode_state saved_modes; 882 u_int pci_status1; 883 u_int intstat; 884 u_int i; 885 u_int reg; 886 struct ahd_pci_busdata *bd = ahd->bus_data; 887 888 intstat = ahd_inb(ahd, INTSTAT); 889 890 if ((intstat & SPLTINT) != 0) 891 ahd_pci_split_intr(ahd, intstat); 892 893 if ((intstat & PCIINT) == 0) 894 return 0; 895 896 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 897 saved_modes = ahd_save_modes(ahd); 898 ahd_dump_card_state(ahd); 899 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 900 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 901 902 if (i == 5) 903 continue; 904 pci_status[i] = ahd_inb(ahd, reg); 905 /* Clear latched errors. So our interrupt deasserts. */ 906 ahd_outb(ahd, reg, pci_status[i]); 907 } 908 909 for (i = 0; i < 8; i++) { 910 u_int bit; 911 912 if (i == 5) 913 continue; 914 915 for (bit = 0; bit < 8; bit++) { 916 917 if ((pci_status[i] & (0x1 << bit)) != 0) { 918 static const char *s; 919 920 s = pci_status_strings[bit]; 921 if (i == 7/*TARG*/ && bit == 3) 922 s = "%s: Signaled Target Abort\n"; 923 printf(s, ahd_name(ahd), pci_status_source[i]); 924 } 925 } 926 } 927 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 928 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG , pci_status1); 929 930 ahd_restore_modes(ahd, saved_modes); 931 ahd_outb(ahd, CLRINT, CLRPCIINT); 932 ahd_unpause(ahd); 933 934 return 1; 935 } 936 937 static void 938 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 939 { 940 uint8_t split_status[4]; 941 uint8_t split_status1[4]; 942 uint8_t sg_split_status[2]; 943 uint8_t sg_split_status1[2]; 944 ahd_mode_state saved_modes; 945 u_int i; 946 pcireg_t pcix_status; 947 struct ahd_pci_busdata *bd = ahd->bus_data; 948 949 /* 950 * Check for splits in all modes. Modes 0 and 1 951 * additionally have SG engine splits to look at. 952 */ 953 pcix_status = pci_conf_read(bd->pc, bd->tag, 954 bd->pcix_off + PCI_PCIX_STATUS); 955 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 956 ahd_name(ahd), pcix_status); 957 958 saved_modes = ahd_save_modes(ahd); 959 for (i = 0; i < 4; i++) { 960 ahd_set_modes(ahd, i, i); 961 962 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 963 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 964 /* Clear latched errors. So our interrupt deasserts. */ 965 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 966 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 967 if (i > 1) 968 continue; 969 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 970 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 971 /* Clear latched errors. So our interrupt deasserts. */ 972 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 973 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 974 } 975 976 for (i = 0; i < 4; i++) { 977 u_int bit; 978 979 for (bit = 0; bit < 8; bit++) { 980 981 if ((split_status[i] & (0x1 << bit)) != 0) { 982 static const char *s; 983 984 s = split_status_strings[bit]; 985 printf(s, ahd_name(ahd), 986 split_status_source[i]); 987 } 988 989 if (i > 0) 990 continue; 991 992 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 993 static const char *s; 994 995 s = split_status_strings[bit]; 996 printf(s, ahd_name(ahd), "SG"); 997 } 998 } 999 } 1000 /* 1001 * Clear PCI-X status bits. 1002 */ 1003 pci_conf_write(bd->pc, bd->tag, bd->pcix_off + PCI_PCIX_STATUS, 1004 pcix_status); 1005 ahd_outb(ahd, CLRINT, CLRSPLTINT); 1006 ahd_restore_modes(ahd, saved_modes); 1007 } 1008 1009 static int 1010 ahd_aic7901_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1011 { 1012 1013 ahd->chip = AHD_AIC7901; 1014 ahd->features = AHD_AIC7901_FE; 1015 return (ahd_aic790X_setup(ahd, pa)); 1016 } 1017 1018 static int 1019 ahd_aic7901A_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1020 { 1021 1022 ahd->chip = AHD_AIC7901A; 1023 ahd->features = AHD_AIC7901A_FE; 1024 return (ahd_aic790X_setup(ahd, pa)); 1025 } 1026 1027 static int 1028 ahd_aic7902_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1029 { 1030 1031 ahd->chip = AHD_AIC7902; 1032 ahd->features = AHD_AIC7902_FE; 1033 return (ahd_aic790X_setup(ahd, pa)); 1034 } 1035 1036 static int 1037 ahd_aic790X_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1038 { 1039 u_int rev; 1040 1041 rev = PCI_REVISION(pa->pa_class); 1042 #ifdef AHD_DEBUG 1043 printf("\n%s: aic7902 chip revision 0x%x\n", ahd_name(ahd), rev); 1044 #endif 1045 if (rev < ID_AIC7902_PCI_REV_A4) { 1046 printf("%s: Unable to attach to unsupported chip revision %d\n", 1047 ahd_name(ahd), rev); 1048 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 0); 1049 return (ENXIO); 1050 } 1051 1052 ahd->channel = (pa->pa_function == 1) ? 'B' : 'A'; 1053 if (rev < ID_AIC7902_PCI_REV_B0) { 1054 /* 1055 * Enable A series workarounds. 1056 */ 1057 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 1058 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 1059 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 1060 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 1061 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 1062 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 1063 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 1064 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 1065 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 1066 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 1067 | AHD_FAINT_LED_BUG; 1068 1069 1070 /* 1071 * IO Cell paramter setup. 1072 */ 1073 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1074 1075 if ((ahd->flags & AHD_HP_BOARD) == 0) 1076 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 1077 } else { 1078 u_int devconfig1; 1079 1080 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1081 | AHD_NEW_DFCNTRL_OPTS; 1082 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; 1083 1084 /* 1085 * Some issues have been resolved in the 7901B. 1086 */ 1087 if ((ahd->features & AHD_MULTI_FUNC) != 0) 1088 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG; 1089 1090 /* 1091 * IO Cell paramter setup. 1092 */ 1093 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1094 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1095 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1096 1097 /* 1098 * Set the PREQDIS bit for H2B which disables some workaround 1099 * that doesn't work on regular PCI busses. 1100 * XXX - Find out exactly what this does from the hardware 1101 * folks! 1102 */ 1103 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1104 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG1, devconfig1|PREQDIS); 1105 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1106 } 1107 1108 return (0); 1109 } 1110 1111
Indexes created Wed Sep 24 05:09:52 GMT 2025