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alipm.c revision 1.8.4.1 
      1 /*	$NetBSD: alipm.c,v 1.8.4.1 2012/04/17 00:07:42 yamt Exp $ */
      2 /*	$OpenBSD: alipm.c,v 1.13 2007/05/03 12:19:01 dlg Exp $	*/
      3 
      4 /*
      5  * Copyright (c) 2005 Mark Kettenis
      6  *
      7  * Permission to use, copy, modify, and distribute this software for any
      8  * purpose with or without fee is hereby granted, provided that the above
      9  * copyright notice and this permission notice appear in all copies.
     10  *
     11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
     12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
     13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
     14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
     15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
     16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
     17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
     18  */
     19 
     20 #include <sys/cdefs.h>
     21 __KERNEL_RCSID(0, "$NetBSD: alipm.c,v 1.8.4.1 2012/04/17 00:07:42 yamt Exp $");
     22 
     23 #include <sys/param.h>
     24 #include <sys/device.h>
     25 #include <sys/kernel.h>
     26 #include <sys/mutex.h>
     27 #include <sys/proc.h>
     28 #include <sys/systm.h>
     29 
     30 #include <dev/i2c/i2cvar.h>
     31 
     32 #include <dev/pci/pcidevs.h>
     33 #include <dev/pci/pcireg.h>
     34 #include <dev/pci/pcivar.h>
     35 
     36 /*
     37  * Acer Labs M7101 Power register definitions.
     38  */
     39 
     40 /* PCI configuration registers. */
     41 #define ALIPM_CONF	0xd0		/* general configuration */
     42 #define ALIPM_CONF_SMBEN	0x0400		/* enable SMBus */
     43 #define ALIPM_BASE	0xe0		/* ACPI and SMBus base address */
     44 #define ALIPM_SMB_HOSTC	0xf0		/* host configuration */
     45 #define ALIPM_SMB_HOSTC_HSTEN	0x00000001	/* enable host controller */
     46 #define ALIPM_SMB_HOSTC_CLOCK	0x00e00000	/* clock speed */
     47 #define ALIPM_SMB_HOSTC_149K	0x00000000	/* 149 KHz clock */
     48 #define ALIPM_SMB_HOSTC_74K	0x00200000	/*  74 KHz clock */
     49 #define ALIPM_SMB_HOSTC_37K	0x00400000	/*  37 KHz clock */
     50 #define ALIPM_SMB_HOSTC_223K	0x00800000	/* 223 KHz clock */
     51 #define ALIPM_SMB_HOSTC_111K	0x00a00000	/* 111 KHz clock */
     52 #define ALIPM_SMB_HOSTC_55K	0x00c00000	/*  55 KHz clock */
     53 
     54 #define ALIPM_SMB_SIZE		32	/* SMBus I/O space size */
     55 
     56 /* SMBus I/O registers */
     57 #define ALIPM_SMB_HS	0x00		/* host status */
     58 #define ALIPM_SMB_HS_IDLE	0x04
     59 #define ALIPM_SMB_HS_BUSY	0x08	/* running a command */
     60 #define ALIPM_SMB_HS_DONE	0x10	/* command completed */
     61 #define ALIPM_SMB_HS_DEVERR	0x20	/* command error */
     62 #define ALIPM_SMB_HS_BUSERR	0x40	/* transaction collision */
     63 #define ALIPM_SMB_HS_FAILED	0x80	/* failed bus transaction */
     64 #define ALIPM_SMB_HS_BITS \
     65   "\020\003IDLE\004BUSY\005DONE\006DEVERR\007BUSERR\010FAILED"
     66 #define ALIPM_SMB_HC	0x01		/* host control */
     67 #define ALIPM_SMB_HC_KILL	0x04		/* kill command */
     68 #define ALIPM_SMB_HC_RESET	0x08		/* reset bus */
     69 #define ALIPM_SMB_HC_CMD_QUICK	0x00		/* QUICK command */
     70 #define ALIPM_SMB_HC_CMD_BYTE	0x10		/* BYTE command */
     71 #define ALIPM_SMB_HC_CMD_BDATA	0x20		/* BYTE DATA command */
     72 #define ALIPM_SMB_HC_CMD_WDATA	0x30		/* WORD DATA command */
     73 #define ALIPM_SMB_HC_CMD_BLOCK 0x40		/* BLOCK command */
     74 #define ALIPM_SMB_START		0x02	/* start command */
     75 #define ALIPM_SMB_TXSLVA	0x03	/* transmit slave address */
     76 #define ALIPM_SMB_TXSLVA_READ	(1 << 0)	/* read direction */
     77 #define ALIPM_SMB_TXSLVA_ADDR(x) (((x) & 0x7f) << 1) /* 7-bit address */
     78 #define ALIPM_SMB_HD0		0x04	/* host data 0 */
     79 #define ALIPM_SMB_HD1		0x05	/* host data 1 */
     80 #define ALIPM_SMB_HBDB		0x06	/* host block data byte */
     81 #define ALIPM_SMB_HCMD		0x07	/* host command */
     82 
     83 /*
     84  * Newer chips have a more standard, but different PCI configuration
     85  * register layout.
     86  */
     87 
     88 #define ALIPM_SMB_BASE	0x14		/* SMBus base address */
     89 #define ALIPM_SMB_HOSTX	0xe0		/* host configuration */
     90 
     91 #ifdef ALIPM_DEBUG
     92 #define DPRINTF(x) printf x
     93 #else
     94 #define DPRINTF(x)
     95 #endif
     96 
     97 #define ALIPM_DELAY	100
     98 #define ALIPM_TIMEOUT	1
     99 
    100 struct alipm_softc {
    101 	device_t sc_dev;
    102 
    103 	bus_space_tag_t sc_iot;
    104 	bus_space_handle_t sc_ioh;
    105 
    106 	struct i2c_controller sc_smb_tag;
    107 	kmutex_t sc_smb_mutex;
    108 };
    109 
    110 static int	alipm_match(device_t, cfdata_t, void *);
    111 static void	alipm_attach(device_t, device_t, void *);
    112 
    113 int	alipm_smb_acquire_bus(void *, int);
    114 void	alipm_smb_release_bus(void *, int);
    115 int	alipm_smb_exec(void *, i2c_op_t, i2c_addr_t, const void *,
    116 	    size_t, void *, size_t, int);
    117 
    118 CFATTACH_DECL_NEW(alipm, sizeof(struct alipm_softc),
    119 	alipm_match, alipm_attach, NULL, NULL);
    120 
    121 static int
    122 alipm_match(device_t parent, cfdata_t match, void *aux)
    123 {
    124 	struct pci_attach_args *pa = aux;
    125 
    126 	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI &&
    127 	    (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M7101))
    128 		return (1);
    129 	return (0);
    130 }
    131 
    132 static void
    133 alipm_attach(device_t parent, device_t self, void *aux)
    134 {
    135 	struct alipm_softc *sc = device_private(self);
    136 	struct pci_attach_args *pa = aux;
    137 	struct i2cbus_attach_args iba;
    138 	pcireg_t iobase, reg;
    139 	bus_size_t iosize = ALIPM_SMB_SIZE;
    140 
    141 	sc->sc_dev = self;
    142 
    143 	/* Old chips don't have the PCI 2.2 Capabilities List. */
    144 	reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
    145 	if ((reg & PCI_STATUS_CAPLIST_SUPPORT) == 0) {
    146 		/* Map I/O space */
    147 		iobase = pci_conf_read(pa->pa_pc, pa->pa_tag, ALIPM_BASE);
    148 		sc->sc_iot = pa->pa_iot;
    149 		if (iobase == 0 ||
    150 		    bus_space_map(sc->sc_iot, iobase >> 16,
    151 		    iosize, 0, &sc->sc_ioh)) {
    152 			aprint_error_dev(sc->sc_dev, "can't map I/O space\n");
    153 			return;
    154 		}
    155 
    156 		reg = pci_conf_read(pa->pa_pc, pa->pa_tag, ALIPM_CONF);
    157 		if ((reg & ALIPM_CONF_SMBEN) == 0) {
    158 			aprint_error_dev(sc->sc_dev, "SMBus disabled\n");
    159 			goto fail;
    160 		}
    161 
    162 		reg = pci_conf_read(pa->pa_pc, pa->pa_tag, ALIPM_SMB_HOSTC);
    163 		if ((reg & ALIPM_SMB_HOSTC_HSTEN) == 0) {
    164 			aprint_error_dev(sc->sc_dev, "SMBus host disabled\n");
    165 			goto fail;
    166 		}
    167 	} else {
    168 		/* Map I/O space */
    169 		if (pci_mapreg_map(pa, ALIPM_SMB_BASE, PCI_MAPREG_TYPE_IO, 0,
    170 		    &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) {
    171 			aprint_error_dev(sc->sc_dev, "can't map I/O space\n");
    172 			return;
    173 		}
    174 
    175 		reg = pci_conf_read(pa->pa_pc, pa->pa_tag, ALIPM_SMB_HOSTX);
    176 		if ((reg & ALIPM_SMB_HOSTC_HSTEN) == 0) {
    177 			aprint_error_dev(sc->sc_dev, "SMBus host disabled\n");
    178 			goto fail;
    179 		}
    180 	}
    181 
    182 	switch (reg & ALIPM_SMB_HOSTC_CLOCK) {
    183 	case ALIPM_SMB_HOSTC_149K:
    184 		aprint_normal(": 149KHz clock\n");
    185 		break;
    186 	case ALIPM_SMB_HOSTC_74K:
    187 		aprint_normal(": 74KHz clock\n");
    188 		break;
    189 	case ALIPM_SMB_HOSTC_37K:
    190 		aprint_normal(": 37KHz clock\n");
    191 		break;
    192 	case ALIPM_SMB_HOSTC_223K:
    193 		aprint_normal(": 223KHz clock\n");
    194 		break;
    195 	case ALIPM_SMB_HOSTC_111K:
    196 		aprint_normal(": 111KHz clock\n");
    197 		break;
    198 	case ALIPM_SMB_HOSTC_55K:
    199 		aprint_normal(": 55KHz clock\n");
    200 		break;
    201 	default:
    202 		aprint_normal(" unknown clock speed\n");
    203 		break;
    204 	}
    205 	aprint_naive("\n");
    206 
    207 	/* Attach I2C bus */
    208 	mutex_init(&sc->sc_smb_mutex, MUTEX_DEFAULT, IPL_NONE);
    209 	sc->sc_smb_tag.ic_cookie = sc;
    210 	sc->sc_smb_tag.ic_acquire_bus = alipm_smb_acquire_bus;
    211 	sc->sc_smb_tag.ic_release_bus = alipm_smb_release_bus;
    212 	sc->sc_smb_tag.ic_exec = alipm_smb_exec;
    213 
    214 	memset(&iba, 0, sizeof iba);
    215 	iba.iba_tag = &sc->sc_smb_tag;
    216 	(void)config_found_ia(sc->sc_dev, "i2cbus", &iba, iicbus_print);
    217 
    218 	return;
    219 
    220 fail:
    221 	bus_space_unmap(sc->sc_iot, sc->sc_ioh, iosize);
    222 }
    223 
    224 int
    225 alipm_smb_acquire_bus(void *cookie, int flags)
    226 {
    227 	struct alipm_softc *sc = cookie;
    228 
    229 	mutex_enter(&sc->sc_smb_mutex);
    230 	return 0;
    231 }
    232 
    233 void
    234 alipm_smb_release_bus(void *cookie, int flags)
    235 {
    236 	struct alipm_softc *sc = cookie;
    237 
    238 	mutex_exit(&sc->sc_smb_mutex);
    239 }
    240 
    241 int
    242 alipm_smb_exec(void *cookie, i2c_op_t op, i2c_addr_t addr,
    243     const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags)
    244 {
    245 	struct alipm_softc *sc = cookie;
    246 	u_int8_t *b;
    247 	u_int8_t ctl, st;
    248 	int retries, error = 0;
    249 
    250 	DPRINTF(("%s: exec op %d, addr 0x%x, cmdlen %d, len %d, "
    251 	    "flags 0x%x\n", device_xname(sc->sc_dev), op, addr, cmdlen,
    252 	    len, flags));
    253 
    254 	if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 ||
    255 	    (cmdlen == 0 && len > 1))
    256 		return (EOPNOTSUPP);
    257 
    258 	/* Clear status bits */
    259 	bus_space_write_1(sc->sc_iot, sc->sc_ioh, ALIPM_SMB_HS,
    260 	    ALIPM_SMB_HS_DONE | ALIPM_SMB_HS_FAILED |
    261 	    ALIPM_SMB_HS_BUSERR | ALIPM_SMB_HS_DEVERR);
    262 	bus_space_barrier(sc->sc_iot, sc->sc_ioh, ALIPM_SMB_HS, 1,
    263 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
    264 
    265 	/* Wait until bus is idle */
    266 	for (retries = 1000; retries > 0; retries--) {
    267 		st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ALIPM_SMB_HS);
    268 		bus_space_barrier(sc->sc_iot, sc->sc_ioh, ALIPM_SMB_HS, 1,
    269 		    BUS_SPACE_BARRIER_READ);
    270 		if (st & (ALIPM_SMB_HS_IDLE | ALIPM_SMB_HS_FAILED |
    271 		    ALIPM_SMB_HS_BUSERR | ALIPM_SMB_HS_DEVERR))
    272 			break;
    273 		DELAY(ALIPM_DELAY);
    274 	}
    275 	if (retries == 0) {
    276 		aprint_error_dev(sc->sc_dev, "timeout st 0x%x\n", st);
    277 		return (ETIMEDOUT);
    278 	}
    279 	if (st & (ALIPM_SMB_HS_FAILED |
    280 	    ALIPM_SMB_HS_BUSERR | ALIPM_SMB_HS_DEVERR)) {
    281 		aprint_error_dev(sc->sc_dev, "error st 0x%x\n", st);
    282 		return (EIO);
    283 	}
    284 
    285 	/* Set slave address and transfer direction. */
    286 	bus_space_write_1(sc->sc_iot, sc->sc_ioh, ALIPM_SMB_TXSLVA,
    287 	    ALIPM_SMB_TXSLVA_ADDR(addr) |
    288 	    (I2C_OP_READ_P(op) ? ALIPM_SMB_TXSLVA_READ : 0));
    289 
    290 	if (cmdlen > 0)
    291 		/* Set command byte */
    292 		bus_space_write_1(sc->sc_iot, sc->sc_ioh,
    293 		     ALIPM_SMB_HCMD, ((const u_int8_t *)cmdbuf)[0]);
    294 
    295 	if (I2C_OP_WRITE_P(op)) {
    296 		/* Write data. */
    297 		b = buf;
    298 		if (cmdlen == 0 && len == 1)
    299 			bus_space_write_1(sc->sc_iot, sc->sc_ioh,
    300 			    ALIPM_SMB_HCMD, b[0]);
    301 		else if (len > 0)
    302 			bus_space_write_1(sc->sc_iot, sc->sc_ioh,
    303 			    ALIPM_SMB_HD0, b[0]);
    304 		if (len > 1)
    305 			bus_space_write_1(sc->sc_iot, sc->sc_ioh,
    306 			    ALIPM_SMB_HD1, b[1]);
    307 	}
    308 
    309 	/* Set SMBus command */
    310 	if (cmdlen == 0) {
    311 		if (len == 0)
    312 			ctl = ALIPM_SMB_HC_CMD_QUICK;
    313 		else
    314 			ctl = ALIPM_SMB_HC_CMD_BYTE;
    315 	} else if (len == 1)
    316 		ctl = ALIPM_SMB_HC_CMD_BDATA;
    317 	else
    318 		ctl = ALIPM_SMB_HC_CMD_WDATA;
    319 	bus_space_write_1(sc->sc_iot, sc->sc_ioh, ALIPM_SMB_HC, ctl);
    320 
    321 	/* Start transaction */
    322 	bus_space_barrier(sc->sc_iot, sc->sc_ioh, 0, ALIPM_SMB_SIZE,
    323 	    BUS_SPACE_BARRIER_WRITE);
    324 	bus_space_write_1(sc->sc_iot, sc->sc_ioh, ALIPM_SMB_START, 0xff);
    325 	bus_space_barrier(sc->sc_iot, sc->sc_ioh, 0, ALIPM_SMB_SIZE,
    326 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
    327 
    328 	/* Poll for completion */
    329 	DELAY(ALIPM_DELAY);
    330 	for (retries = 1000; retries > 0; retries--) {
    331 		st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ALIPM_SMB_HS);
    332 		bus_space_barrier(sc->sc_iot, sc->sc_ioh, ALIPM_SMB_HS, 1,
    333 		    BUS_SPACE_BARRIER_READ);
    334 		if (st & (ALIPM_SMB_HS_IDLE | ALIPM_SMB_HS_FAILED |
    335 		    ALIPM_SMB_HS_BUSERR | ALIPM_SMB_HS_DEVERR))
    336 			break;
    337 		DELAY(ALIPM_DELAY);
    338 	}
    339 	if (retries == 0) {
    340 		aprint_error_dev(sc->sc_dev, "timeout st 0x%x, resetting\n",st);
    341 		bus_space_write_1(sc->sc_iot, sc->sc_ioh, ALIPM_SMB_HC,
    342 		    ALIPM_SMB_HC_RESET);
    343 		bus_space_barrier(sc->sc_iot, sc->sc_ioh, 0, ALIPM_SMB_SIZE,
    344 		     BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
    345 		st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ALIPM_SMB_HS);
    346 		bus_space_barrier(sc->sc_iot, sc->sc_ioh, ALIPM_SMB_HS, 1,
    347 		    BUS_SPACE_BARRIER_READ);
    348 		error = ETIMEDOUT;
    349 		goto done;
    350 	}
    351 
    352 	if ((st & ALIPM_SMB_HS_DONE) == 0) {
    353 		bus_space_write_1(sc->sc_iot, sc->sc_ioh, ALIPM_SMB_HC,
    354 		     ALIPM_SMB_HC_KILL);
    355 		bus_space_barrier(sc->sc_iot, sc->sc_ioh, 0, ALIPM_SMB_SIZE,
    356 		     BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
    357 		st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ALIPM_SMB_HS);
    358 		bus_space_barrier(sc->sc_iot, sc->sc_ioh, ALIPM_SMB_HS, 1,
    359 		    BUS_SPACE_BARRIER_READ);
    360 		if ((st & ALIPM_SMB_HS_FAILED) == 0)
    361 			aprint_error_dev(sc->sc_dev, "error st 0x%x\n", st);
    362 	}
    363 
    364 	/* Check for errors */
    365 	if (st & (ALIPM_SMB_HS_FAILED |
    366 	    ALIPM_SMB_HS_BUSERR | ALIPM_SMB_HS_DEVERR)) {
    367 		error = EIO;
    368 		goto done;
    369 	}
    370 
    371 	if (I2C_OP_READ_P(op)) {
    372 		/* Read data */
    373 		b = buf;
    374 		if (len > 0) {
    375 			b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh,
    376 			    ALIPM_SMB_HD0);
    377 			bus_space_barrier(sc->sc_iot, sc->sc_ioh,
    378 			    ALIPM_SMB_HD0, 1, BUS_SPACE_BARRIER_READ);
    379 		}
    380 		if (len > 1) {
    381 			b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh,
    382 			    ALIPM_SMB_HD1);
    383 			bus_space_barrier(sc->sc_iot, sc->sc_ioh,
    384 			    ALIPM_SMB_HD1, 1, BUS_SPACE_BARRIER_READ);
    385 		}
    386 	}
    387 
    388 done:
    389 	/* Clear status bits */
    390 	bus_space_write_1(sc->sc_iot, sc->sc_ioh, ALIPM_SMB_HS, st);
    391 
    392 	return (error);
    393 }
    394