amdpm_smbus.c revision 1.2.2.2
1 1.2.2.2 tron /* $NetBSD: amdpm_smbus.c,v 1.2.2.2 2006/02/20 23:00:27 tron Exp $ */ 2 1.2.2.2 tron 3 1.2.2.2 tron /* 4 1.2.2.2 tron * Copyright (c) 2005 Anil Gopinath (anil_public (at) yahoo.com) 5 1.2.2.2 tron * All rights reserved. 6 1.2.2.2 tron * 7 1.2.2.2 tron * Redistribution and use in source and binary forms, with or without 8 1.2.2.2 tron * modification, are permitted provided that the following conditions 9 1.2.2.2 tron * are met: 10 1.2.2.2 tron * 1. Redistributions of source code must retain the above copyright 11 1.2.2.2 tron * notice, this list of conditions and the following disclaimer. 12 1.2.2.2 tron * 2. Redistributions in binary form must reproduce the above copyright 13 1.2.2.2 tron * notice, this list of conditions and the following disclaimer in the 14 1.2.2.2 tron * documentation and/or other materials provided with the distribution. 15 1.2.2.2 tron * 3. The name of the author may not be used to endorse or promote products 16 1.2.2.2 tron * derived from this software without specific prior written permission. 17 1.2.2.2 tron * 18 1.2.2.2 tron * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 1.2.2.2 tron * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 1.2.2.2 tron * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 1.2.2.2 tron * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 1.2.2.2 tron * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 1.2.2.2 tron * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 1.2.2.2 tron * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 1.2.2.2 tron * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 1.2.2.2 tron * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 1.2.2.2 tron * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 1.2.2.2 tron * SUCH DAMAGE. 29 1.2.2.2 tron */ 30 1.2.2.2 tron 31 1.2.2.2 tron /* driver for SMBUS 1.0 host controller found in the 32 1.2.2.2 tron * AMD-8111 HyperTransport I/O Hub 33 1.2.2.2 tron */ 34 1.2.2.2 tron #include <sys/param.h> 35 1.2.2.2 tron #include <sys/systm.h> 36 1.2.2.2 tron #include <sys/kernel.h> 37 1.2.2.2 tron #include <sys/device.h> 38 1.2.2.2 tron #include <sys/rnd.h> 39 1.2.2.2 tron #include <dev/pci/pcireg.h> 40 1.2.2.2 tron #include <dev/pci/pcivar.h> 41 1.2.2.2 tron #include <dev/pci/pcidevs.h> 42 1.2.2.2 tron 43 1.2.2.2 tron #include <dev/i2c/i2cvar.h> 44 1.2.2.2 tron #include <dev/i2c/i2c_bitbang.h> 45 1.2.2.2 tron 46 1.2.2.2 tron #include <dev/pci/amdpmreg.h> 47 1.2.2.2 tron #include <dev/pci/amdpmvar.h> 48 1.2.2.2 tron 49 1.2.2.2 tron #include <dev/pci/amdpm_smbusreg.h> 50 1.2.2.2 tron 51 1.2.2.2 tron static int amdpm_smbus_acquire_bus(void *cookie, int flags); 52 1.2.2.2 tron static void amdpm_smbus_release_bus(void *cookie, int flags); 53 1.2.2.2 tron static int amdpm_smbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 54 1.2.2.2 tron const void *cmd, size_t cmdlen, void *vbuf, 55 1.2.2.2 tron size_t buflen, int flags); 56 1.2.2.2 tron static int amdpm_smbus_check_done(struct amdpm_softc *sc); 57 1.2.2.2 tron static void amdpm_smbus_clear_gsr(struct amdpm_softc *sc); 58 1.2.2.2 tron static u_int16_t amdpm_smbus_get_gsr(struct amdpm_softc *sc); 59 1.2.2.2 tron static int amdpm_smbus_send_1(struct amdpm_softc *sc, u_int8_t val); 60 1.2.2.2 tron static int amdpm_smbus_write_1(struct amdpm_softc *sc, u_int8_t cmd, u_int8_t data); 61 1.2.2.2 tron static int amdpm_smbus_receive_1(struct amdpm_softc *sc); 62 1.2.2.2 tron static int amdpm_smbus_read_1(struct amdpm_softc *sc, u_int8_t cmd); 63 1.2.2.2 tron 64 1.2.2.2 tron 65 1.2.2.2 tron void 66 1.2.2.2 tron amdpm_smbus_attach(struct amdpm_softc *sc) 67 1.2.2.2 tron { 68 1.2.2.2 tron struct i2cbus_attach_args iba; 69 1.2.2.2 tron 70 1.2.2.2 tron // register with iic 71 1.2.2.2 tron sc->sc_i2c.ic_cookie = sc; 72 1.2.2.2 tron sc->sc_i2c.ic_acquire_bus = amdpm_smbus_acquire_bus; 73 1.2.2.2 tron sc->sc_i2c.ic_release_bus = amdpm_smbus_release_bus; 74 1.2.2.2 tron sc->sc_i2c.ic_send_start = NULL; 75 1.2.2.2 tron sc->sc_i2c.ic_send_stop = NULL; 76 1.2.2.2 tron sc->sc_i2c.ic_initiate_xfer = NULL; 77 1.2.2.2 tron sc->sc_i2c.ic_read_byte = NULL; 78 1.2.2.2 tron sc->sc_i2c.ic_write_byte = NULL; 79 1.2.2.2 tron sc->sc_i2c.ic_exec = amdpm_smbus_exec; 80 1.2.2.2 tron 81 1.2.2.2 tron iba.iba_name = "iic"; 82 1.2.2.2 tron iba.iba_tag = &sc->sc_i2c; 83 1.2.2.2 tron (void) config_found(&sc->sc_dev, &iba, iicbus_print); 84 1.2.2.2 tron } 85 1.2.2.2 tron 86 1.2.2.2 tron static int 87 1.2.2.2 tron amdpm_smbus_acquire_bus(void *cookie, int flags) 88 1.2.2.2 tron { 89 1.2.2.2 tron return (0); 90 1.2.2.2 tron } 91 1.2.2.2 tron 92 1.2.2.2 tron static void 93 1.2.2.2 tron amdpm_smbus_release_bus(void *cookie, int flags) 94 1.2.2.2 tron { 95 1.2.2.2 tron } 96 1.2.2.2 tron 97 1.2.2.2 tron static int 98 1.2.2.2 tron amdpm_smbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmd, 99 1.2.2.2 tron size_t cmdlen, void *vbuf, size_t buflen, int flags) 100 1.2.2.2 tron { 101 1.2.2.2 tron struct amdpm_softc *sc = (struct amdpm_softc *) cookie; 102 1.2.2.2 tron sc->sc_smbus_slaveaddr = addr; 103 1.2.2.2 tron 104 1.2.2.2 tron if (I2C_OP_READ_P(op) && (cmdlen == 0) && (buflen == 1)) { 105 1.2.2.2 tron return (amdpm_smbus_receive_1(sc)); 106 1.2.2.2 tron } 107 1.2.2.2 tron 108 1.2.2.2 tron if ( (I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 1)) { 109 1.2.2.2 tron return (amdpm_smbus_read_1(sc, *(const uint8_t*)cmd)); 110 1.2.2.2 tron } 111 1.2.2.2 tron 112 1.2.2.2 tron if ( (I2C_OP_WRITE_P(op)) && (cmdlen == 0) && (buflen == 1)) { 113 1.2.2.2 tron return (amdpm_smbus_send_1(sc, *(uint8_t*)vbuf)); 114 1.2.2.2 tron } 115 1.2.2.2 tron 116 1.2.2.2 tron if ( (I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 1)) { 117 1.2.2.2 tron return (amdpm_smbus_write_1(sc, *(const uint8_t*)cmd, *(uint8_t*)vbuf)); 118 1.2.2.2 tron } 119 1.2.2.2 tron 120 1.2.2.2 tron return (-1); 121 1.2.2.2 tron } 122 1.2.2.2 tron 123 1.2.2.2 tron static int 124 1.2.2.2 tron amdpm_smbus_check_done(struct amdpm_softc *sc) 125 1.2.2.2 tron { 126 1.2.2.2 tron int i = 0; 127 1.2.2.2 tron for (i = 0; i < 1000; i++) { 128 1.2.2.2 tron /* check gsr and wait till cycle is done */ 129 1.2.2.2 tron u_int16_t data = amdpm_smbus_get_gsr(sc); 130 1.2.2.2 tron if (data & AMDPM_8111_GSR_CYCLE_DONE) { 131 1.2.2.2 tron return (0); 132 1.2.2.2 tron } 133 1.2.2.2 tron delay(1); 134 1.2.2.2 tron } 135 1.2.2.2 tron return (-1); 136 1.2.2.2 tron } 137 1.2.2.2 tron 138 1.2.2.2 tron 139 1.2.2.2 tron static void 140 1.2.2.2 tron amdpm_smbus_clear_gsr(struct amdpm_softc *sc) 141 1.2.2.2 tron { 142 1.2.2.2 tron /* clear register */ 143 1.2.2.2 tron u_int16_t data = 0xFFFF; 144 1.2.2.2 tron bus_space_write_2(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_STAT, data); 145 1.2.2.2 tron } 146 1.2.2.2 tron 147 1.2.2.2 tron static u_int16_t 148 1.2.2.2 tron amdpm_smbus_get_gsr(struct amdpm_softc *sc) 149 1.2.2.2 tron { 150 1.2.2.2 tron return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_STAT)); 151 1.2.2.2 tron } 152 1.2.2.2 tron 153 1.2.2.2 tron static int 154 1.2.2.2 tron amdpm_smbus_send_1(struct amdpm_softc *sc, u_int8_t val) 155 1.2.2.2 tron { 156 1.2.2.2 tron /* first clear gsr */ 157 1.2.2.2 tron amdpm_smbus_clear_gsr(sc); 158 1.2.2.2 tron 159 1.2.2.2 tron /* write smbus slave address to register */ 160 1.2.2.2 tron u_int16_t data = 0; 161 1.2.2.2 tron data = sc->sc_smbus_slaveaddr; 162 1.2.2.2 tron data <<= 1; 163 1.2.2.2 tron data |= AMDPM_8111_SMBUS_SEND; 164 1.2.2.2 tron bus_space_write_1(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_HOSTADDR, data); 165 1.2.2.2 tron 166 1.2.2.2 tron data = val; 167 1.2.2.2 tron /* store data */ 168 1.2.2.2 tron bus_space_write_2(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_HOSTDATA, data); 169 1.2.2.2 tron /* host start */ 170 1.2.2.2 tron bus_space_write_2(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_CTRL, 171 1.2.2.2 tron AMDPM_8111_SMBUS_GSR_SB); 172 1.2.2.2 tron return(amdpm_smbus_check_done(sc)); 173 1.2.2.2 tron } 174 1.2.2.2 tron 175 1.2.2.2 tron 176 1.2.2.2 tron static int 177 1.2.2.2 tron amdpm_smbus_write_1(struct amdpm_softc *sc, u_int8_t cmd, u_int8_t val) 178 1.2.2.2 tron { 179 1.2.2.2 tron /* first clear gsr */ 180 1.2.2.2 tron amdpm_smbus_clear_gsr(sc); 181 1.2.2.2 tron 182 1.2.2.2 tron u_int16_t data = 0; 183 1.2.2.2 tron data = sc->sc_smbus_slaveaddr; 184 1.2.2.2 tron data <<= 1; 185 1.2.2.2 tron data |= AMDPM_8111_SMBUS_WRITE; 186 1.2.2.2 tron bus_space_write_1(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_HOSTADDR, data); 187 1.2.2.2 tron 188 1.2.2.2 tron data = val; 189 1.2.2.2 tron /* store cmd */ 190 1.2.2.2 tron bus_space_write_1(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_HOSTCMD, cmd); 191 1.2.2.2 tron /* store data */ 192 1.2.2.2 tron bus_space_write_2(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_HOSTDATA, data); 193 1.2.2.2 tron /* host start */ 194 1.2.2.2 tron bus_space_write_2(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_CTRL, AMDPM_8111_SMBUS_GSR_WB); 195 1.2.2.2 tron 196 1.2.2.2 tron return (amdpm_smbus_check_done(sc)); 197 1.2.2.2 tron } 198 1.2.2.2 tron 199 1.2.2.2 tron static int 200 1.2.2.2 tron amdpm_smbus_receive_1(struct amdpm_softc *sc) 201 1.2.2.2 tron { 202 1.2.2.2 tron /* first clear gsr */ 203 1.2.2.2 tron amdpm_smbus_clear_gsr(sc); 204 1.2.2.2 tron 205 1.2.2.2 tron /* write smbus slave address to register */ 206 1.2.2.2 tron u_int16_t data = 0; 207 1.2.2.2 tron data = sc->sc_smbus_slaveaddr; 208 1.2.2.2 tron data <<= 1; 209 1.2.2.2 tron data |= AMDPM_8111_SMBUS_RX; 210 1.2.2.2 tron bus_space_write_1(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_HOSTADDR, data); 211 1.2.2.2 tron 212 1.2.2.2 tron /* start smbus cycle */ 213 1.2.2.2 tron bus_space_write_2(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_CTRL, AMDPM_8111_SMBUS_GSR_RXB); 214 1.2.2.2 tron 215 1.2.2.2 tron /* check for errors */ 216 1.2.2.2 tron if (amdpm_smbus_check_done(sc) < 0) 217 1.2.2.2 tron return (-1); 218 1.2.2.2 tron 219 1.2.2.2 tron /* read data */ 220 1.2.2.2 tron data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_HOSTDATA); 221 1.2.2.2 tron u_int8_t ret = (u_int8_t)(data & 0x00FF); 222 1.2.2.2 tron return (ret); 223 1.2.2.2 tron } 224 1.2.2.2 tron 225 1.2.2.2 tron static int 226 1.2.2.2 tron amdpm_smbus_read_1(struct amdpm_softc *sc, u_int8_t cmd) 227 1.2.2.2 tron { 228 1.2.2.2 tron /* first clear gsr */ 229 1.2.2.2 tron amdpm_smbus_clear_gsr(sc); 230 1.2.2.2 tron 231 1.2.2.2 tron /* write smbus slave address to register */ 232 1.2.2.2 tron u_int16_t data = 0; 233 1.2.2.2 tron data = sc->sc_smbus_slaveaddr; 234 1.2.2.2 tron data <<= 1; 235 1.2.2.2 tron data |= AMDPM_8111_SMBUS_READ; 236 1.2.2.2 tron bus_space_write_1(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_HOSTADDR, data); 237 1.2.2.2 tron 238 1.2.2.2 tron /* store cmd */ 239 1.2.2.2 tron bus_space_write_1(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_HOSTCMD, cmd); 240 1.2.2.2 tron /* host start */ 241 1.2.2.2 tron bus_space_write_2(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_CTRL, AMDPM_8111_SMBUS_GSR_RB); 242 1.2.2.2 tron 243 1.2.2.2 tron /* check for errors */ 244 1.2.2.2 tron if (amdpm_smbus_check_done(sc) < 0) 245 1.2.2.2 tron return (-1); 246 1.2.2.2 tron 247 1.2.2.2 tron /* store data */ 248 1.2.2.2 tron data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_HOSTDATA); 249 1.2.2.2 tron u_int8_t ret = (u_int8_t)(data & 0x00FF); 250 1.2.2.2 tron return (ret); 251 1.2.2.2 tron } 252
Indexes created Thu Oct 02 14:10:14 GMT 2025