amdpm_smbus.c revision 1.11
1 /* $NetBSD: amdpm_smbus.c,v 1.11 2007/02/06 02:07:36 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2005 Anil Gopinath (anil_public (at) yahoo.com) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* driver for SMBUS 1.0 host controller found in the 32 * AMD-8111 HyperTransport I/O Hub 33 */ 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: amdpm_smbus.c,v 1.11 2007/02/06 02:07:36 jmcneill Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 #include <sys/rnd.h> 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 46 #include <dev/i2c/i2cvar.h> 47 #include <dev/i2c/i2c_bitbang.h> 48 49 #include <dev/pci/amdpmreg.h> 50 #include <dev/pci/amdpmvar.h> 51 52 #include <dev/pci/amdpm_smbusreg.h> 53 54 #ifdef __i386__ 55 #include "opt_xbox.h" 56 #endif 57 58 #ifdef XBOX 59 extern int arch_i386_is_xbox; 60 #endif 61 62 static int amdpm_smbus_acquire_bus(void *cookie, int flags); 63 static void amdpm_smbus_release_bus(void *cookie, int flags); 64 static int amdpm_smbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 65 const void *cmd, size_t cmdlen, void *vbuf, 66 size_t buflen, int flags); 67 static int amdpm_smbus_check_done(struct amdpm_softc *sc, i2c_op_t op); 68 static void amdpm_smbus_clear_gsr(struct amdpm_softc *sc); 69 static u_int16_t amdpm_smbus_get_gsr(struct amdpm_softc *sc); 70 static int amdpm_smbus_send_1(struct amdpm_softc *sc, u_int8_t val, i2c_op_t op); 71 static int amdpm_smbus_write_1(struct amdpm_softc *sc, u_int8_t cmd, u_int8_t data, i2c_op_t op); 72 static int amdpm_smbus_receive_1(struct amdpm_softc *sc, i2c_op_t op); 73 static int amdpm_smbus_read_1(struct amdpm_softc *sc, u_int8_t cmd, i2c_op_t op); 74 75 static int amdpm_smbus_intr(void *); 76 77 void 78 amdpm_smbus_attach(struct amdpm_softc *sc) 79 { 80 struct i2cbus_attach_args iba; 81 pci_intr_handle_t ih; 82 const char *intrstr; 83 84 /* register with iic */ 85 sc->sc_i2c.ic_cookie = sc; 86 sc->sc_i2c.ic_acquire_bus = amdpm_smbus_acquire_bus; 87 sc->sc_i2c.ic_release_bus = amdpm_smbus_release_bus; 88 sc->sc_i2c.ic_send_start = NULL; 89 sc->sc_i2c.ic_send_stop = NULL; 90 sc->sc_i2c.ic_initiate_xfer = NULL; 91 sc->sc_i2c.ic_read_byte = NULL; 92 sc->sc_i2c.ic_write_byte = NULL; 93 sc->sc_i2c.ic_exec = amdpm_smbus_exec; 94 95 lockinit(&sc->sc_lock, PZERO, "amdpm_smbus", 0, 0); 96 97 #ifdef XBOX 98 #define XBOX_SMBA 0x8000 99 #define XBOX_SMSIZE 256 100 #define XBOX_INTRLINE 12 101 #define XBOX_REG_ACPI_PM1a_EN 0x02 102 #define XBOX_REG_ACPI_PM1a_EN_TIMER 0x01 103 /* XXX pci0 dev 1 function 2 "System Management" doesn't probe */ 104 if (arch_i386_is_xbox) { 105 uint16_t val; 106 sc->sc_pa->pa_intrline = XBOX_INTRLINE; 107 108 if (bus_space_map(sc->sc_iot, XBOX_SMBA, XBOX_SMSIZE, 109 0, &sc->sc_sm_ioh) == 0) { 110 aprint_normal("%s: system management at 0x%04x\n", 111 sc->sc_dev.dv_xname, XBOX_SMBA); 112 113 /* Disable PM ACPI timer SCI interrupt */ 114 val = bus_space_read_2(sc->sc_iot, sc->sc_sm_ioh, 115 XBOX_REG_ACPI_PM1a_EN); 116 bus_space_write_2(sc->sc_iot, sc->sc_sm_ioh, 117 XBOX_REG_ACPI_PM1a_EN, 118 val & ~XBOX_REG_ACPI_PM1a_EN_TIMER); 119 } 120 } 121 122 if (pci_intr_map(sc->sc_pa, &ih)) 123 aprint_error("%s: couldn't map interrupt\n", 124 sc->sc_dev.dv_xname); 125 else { 126 intrstr = pci_intr_string(sc->sc_pc, ih); 127 sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_BIO, 128 amdpm_smbus_intr, sc); 129 if (sc->sc_ih != NULL) 130 aprint_normal("%s: interrupting at %s\n", 131 sc->sc_dev.dv_xname, intrstr); 132 } 133 #endif 134 135 iba.iba_tag = &sc->sc_i2c; 136 (void) config_found_ia(&sc->sc_dev, "i2cbus", &iba, iicbus_print); 137 } 138 139 static int 140 amdpm_smbus_intr(void *cookie) 141 { 142 #ifdef XBOX 143 struct amdpm_softc *sc; 144 uint32_t status; 145 146 sc = (struct amdpm_softc *)cookie; 147 148 if (arch_i386_is_xbox) { 149 status = bus_space_read_4(sc->sc_iot, sc->sc_sm_ioh, 0x20); 150 bus_space_write_4(sc->sc_iot, sc->sc_sm_ioh, 0x20, status); 151 152 if (status & 2) 153 return iic_smbus_intr(&sc->sc_i2c); 154 } 155 #endif 156 return 0; 157 } 158 159 static int 160 amdpm_smbus_acquire_bus(void *cookie, int flags) 161 { 162 struct amdpm_softc *sc = cookie; 163 int err; 164 165 err = lockmgr(&sc->sc_lock, LK_EXCLUSIVE, NULL); 166 167 return err; 168 } 169 170 static void 171 amdpm_smbus_release_bus(void *cookie, int flags) 172 { 173 struct amdpm_softc *sc = cookie; 174 175 lockmgr(&sc->sc_lock, LK_RELEASE, NULL); 176 177 return; 178 } 179 180 static int 181 amdpm_smbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmd, 182 size_t cmdlen, void *vbuf, size_t buflen, int flags) 183 { 184 struct amdpm_softc *sc = (struct amdpm_softc *) cookie; 185 sc->sc_smbus_slaveaddr = addr; 186 u_int8_t *p = vbuf; 187 int rv; 188 189 if (I2C_OP_READ_P(op) && (cmdlen == 0) && (buflen == 1)) { 190 rv = amdpm_smbus_receive_1(sc, op); 191 if (rv == -1) 192 return -1; 193 *p = (u_int8_t)rv; 194 return 0; 195 } 196 197 if ( (I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 1)) { 198 rv = amdpm_smbus_read_1(sc, *(const uint8_t*)cmd, op); 199 if (rv == -1) 200 return -1; 201 *p = (u_int8_t)rv; 202 return 0; 203 } 204 205 if ( (I2C_OP_WRITE_P(op)) && (cmdlen == 0) && (buflen == 1)) { 206 return amdpm_smbus_send_1(sc, *(uint8_t*)vbuf, op); 207 } 208 209 if ( (I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 1)) { 210 return amdpm_smbus_write_1(sc, *(const uint8_t*)cmd, *(uint8_t*)vbuf, op); 211 } 212 213 return (-1); 214 } 215 216 static int 217 amdpm_smbus_check_done(struct amdpm_softc *sc, i2c_op_t op) 218 { 219 int i = 0; 220 for (i = 0; i < 1000; i++) { 221 /* check gsr and wait till cycle is done */ 222 u_int16_t data = amdpm_smbus_get_gsr(sc); 223 if (data & AMDPM_8111_GSR_CYCLE_DONE) { 224 return (0); 225 } 226 if (!(op & I2C_F_POLL)) 227 delay(1); 228 } 229 return (-1); 230 } 231 232 233 static void 234 amdpm_smbus_clear_gsr(struct amdpm_softc *sc) 235 { 236 /* clear register */ 237 u_int16_t data = 0xFFFF; 238 int off = (sc->sc_nforce ? 0xe0 : 0); 239 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 240 AMDPM_8111_SMBUS_STAT - off, data); 241 } 242 243 static u_int16_t 244 amdpm_smbus_get_gsr(struct amdpm_softc *sc) 245 { 246 int off = (sc->sc_nforce ? 0xe0 : 0); 247 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, 248 AMDPM_8111_SMBUS_STAT - off)); 249 } 250 251 static int 252 amdpm_smbus_send_1(struct amdpm_softc *sc, u_int8_t val, i2c_op_t op) 253 { 254 u_int16_t data = 0; 255 int off = (sc->sc_nforce ? 0xe0 : 0); 256 257 /* first clear gsr */ 258 amdpm_smbus_clear_gsr(sc); 259 260 /* write smbus slave address to register */ 261 data = sc->sc_smbus_slaveaddr; 262 data <<= 1; 263 data |= AMDPM_8111_SMBUS_SEND; 264 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 265 AMDPM_8111_SMBUS_HOSTADDR - off, data); 266 267 data = val; 268 /* store data */ 269 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 270 AMDPM_8111_SMBUS_HOSTDATA - off, data); 271 /* host start */ 272 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 273 AMDPM_8111_SMBUS_CTRL - off, 274 AMDPM_8111_SMBUS_GSR_SB); 275 276 return(amdpm_smbus_check_done(sc, op)); 277 } 278 279 280 static int 281 amdpm_smbus_write_1(struct amdpm_softc *sc, u_int8_t cmd, u_int8_t val, i2c_op_t op) 282 { 283 u_int16_t data = 0; 284 int off = (sc->sc_nforce ? 0xe0 : 0); 285 286 /* first clear gsr */ 287 amdpm_smbus_clear_gsr(sc); 288 289 data = sc->sc_smbus_slaveaddr; 290 data <<= 1; 291 data |= AMDPM_8111_SMBUS_WRITE; 292 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 293 AMDPM_8111_SMBUS_HOSTADDR - off, data); 294 295 data = val; 296 /* store cmd */ 297 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 298 AMDPM_8111_SMBUS_HOSTCMD - off, cmd); 299 /* store data */ 300 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 301 AMDPM_8111_SMBUS_HOSTDATA - off, data); 302 /* host start */ 303 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 304 AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_WB); 305 306 return (amdpm_smbus_check_done(sc, op)); 307 } 308 309 static int 310 amdpm_smbus_receive_1(struct amdpm_softc *sc, i2c_op_t op) 311 { 312 u_int16_t data = 0; 313 int off = (sc->sc_nforce ? 0xe0 : 0); 314 315 /* first clear gsr */ 316 amdpm_smbus_clear_gsr(sc); 317 318 /* write smbus slave address to register */ 319 data = sc->sc_smbus_slaveaddr; 320 data <<= 1; 321 data |= AMDPM_8111_SMBUS_RX; 322 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 323 AMDPM_8111_SMBUS_HOSTADDR - off, data); 324 325 /* start smbus cycle */ 326 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 327 AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_RXB); 328 329 /* check for errors */ 330 if (amdpm_smbus_check_done(sc, op) < 0) 331 return (-1); 332 333 /* read data */ 334 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 335 AMDPM_8111_SMBUS_HOSTDATA - off); 336 u_int8_t ret = (u_int8_t)(data & 0x00FF); 337 return (ret); 338 } 339 340 static int 341 amdpm_smbus_read_1(struct amdpm_softc *sc, u_int8_t cmd, i2c_op_t op) 342 { 343 u_int16_t data = 0; 344 u_int8_t ret; 345 int off = (sc->sc_nforce ? 0xe0 : 0); 346 347 /* first clear gsr */ 348 amdpm_smbus_clear_gsr(sc); 349 350 /* write smbus slave address to register */ 351 data = sc->sc_smbus_slaveaddr; 352 data <<= 1; 353 data |= AMDPM_8111_SMBUS_READ; 354 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 355 AMDPM_8111_SMBUS_HOSTADDR - off, data); 356 357 /* store cmd */ 358 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 359 AMDPM_8111_SMBUS_HOSTCMD - off, cmd); 360 /* host start */ 361 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 362 AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_RB); 363 364 /* check for errors */ 365 if (amdpm_smbus_check_done(sc, op) < 0) 366 return (-1); 367 368 /* store data */ 369 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 370 AMDPM_8111_SMBUS_HOSTDATA - off); 371 ret = (u_int8_t)(data & 0x00FF); 372 return (ret); 373 } 374
Indexes created Wed Oct 01 18:09:54 GMT 2025