amdpm_smbus.c revision 1.12
1 /* $NetBSD: amdpm_smbus.c,v 1.12 2007/02/06 14:39:47 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2005 Anil Gopinath (anil_public (at) yahoo.com) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* driver for SMBUS 1.0 host controller found in the 32 * AMD-8111 HyperTransport I/O Hub 33 */ 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: amdpm_smbus.c,v 1.12 2007/02/06 14:39:47 jmcneill Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 #include <sys/rnd.h> 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 46 #include <dev/i2c/i2cvar.h> 47 #include <dev/i2c/i2c_bitbang.h> 48 49 #include <dev/pci/amdpmreg.h> 50 #include <dev/pci/amdpmvar.h> 51 52 #include <dev/pci/amdpm_smbusreg.h> 53 54 #ifdef __i386__ 55 #include "opt_xbox.h" 56 #endif 57 58 #ifdef XBOX 59 extern int arch_i386_is_xbox; 60 #endif 61 62 static int amdpm_smbus_acquire_bus(void *cookie, int flags); 63 static void amdpm_smbus_release_bus(void *cookie, int flags); 64 static int amdpm_smbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 65 const void *cmd, size_t cmdlen, void *vbuf, 66 size_t buflen, int flags); 67 static int amdpm_smbus_check_done(struct amdpm_softc *sc, i2c_op_t op); 68 static void amdpm_smbus_clear_gsr(struct amdpm_softc *sc); 69 static u_int16_t amdpm_smbus_get_gsr(struct amdpm_softc *sc); 70 static int amdpm_smbus_send_1(struct amdpm_softc *sc, u_int8_t val, i2c_op_t op); 71 static int amdpm_smbus_write_1(struct amdpm_softc *sc, u_int8_t cmd, u_int8_t data, i2c_op_t op); 72 static int amdpm_smbus_receive_1(struct amdpm_softc *sc, i2c_op_t op); 73 static int amdpm_smbus_read_1(struct amdpm_softc *sc, u_int8_t cmd, i2c_op_t op); 74 75 #ifdef XBOX 76 static int amdpm_smbus_intr(void *); 77 #endif 78 79 void 80 amdpm_smbus_attach(struct amdpm_softc *sc) 81 { 82 struct i2cbus_attach_args iba; 83 #ifdef XBOX 84 pci_intr_handle_t ih; 85 const char *intrstr; 86 #endif 87 88 /* register with iic */ 89 sc->sc_i2c.ic_cookie = sc; 90 sc->sc_i2c.ic_acquire_bus = amdpm_smbus_acquire_bus; 91 sc->sc_i2c.ic_release_bus = amdpm_smbus_release_bus; 92 sc->sc_i2c.ic_send_start = NULL; 93 sc->sc_i2c.ic_send_stop = NULL; 94 sc->sc_i2c.ic_initiate_xfer = NULL; 95 sc->sc_i2c.ic_read_byte = NULL; 96 sc->sc_i2c.ic_write_byte = NULL; 97 sc->sc_i2c.ic_exec = amdpm_smbus_exec; 98 99 lockinit(&sc->sc_lock, PZERO, "amdpm_smbus", 0, 0); 100 101 #ifdef XBOX 102 #define XBOX_SMBA 0x8000 103 #define XBOX_SMSIZE 256 104 #define XBOX_INTRLINE 12 105 #define XBOX_REG_ACPI_PM1a_EN 0x02 106 #define XBOX_REG_ACPI_PM1a_EN_TIMER 0x01 107 /* XXX pci0 dev 1 function 2 "System Management" doesn't probe */ 108 if (arch_i386_is_xbox) { 109 uint16_t val; 110 sc->sc_pa->pa_intrline = XBOX_INTRLINE; 111 112 if (bus_space_map(sc->sc_iot, XBOX_SMBA, XBOX_SMSIZE, 113 0, &sc->sc_sm_ioh) == 0) { 114 aprint_normal("%s: system management at 0x%04x\n", 115 sc->sc_dev.dv_xname, XBOX_SMBA); 116 117 /* Disable PM ACPI timer SCI interrupt */ 118 val = bus_space_read_2(sc->sc_iot, sc->sc_sm_ioh, 119 XBOX_REG_ACPI_PM1a_EN); 120 bus_space_write_2(sc->sc_iot, sc->sc_sm_ioh, 121 XBOX_REG_ACPI_PM1a_EN, 122 val & ~XBOX_REG_ACPI_PM1a_EN_TIMER); 123 } 124 } 125 126 if (pci_intr_map(sc->sc_pa, &ih)) 127 aprint_error("%s: couldn't map interrupt\n", 128 sc->sc_dev.dv_xname); 129 else { 130 intrstr = pci_intr_string(sc->sc_pc, ih); 131 sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_BIO, 132 amdpm_smbus_intr, sc); 133 if (sc->sc_ih != NULL) 134 aprint_normal("%s: interrupting at %s\n", 135 sc->sc_dev.dv_xname, intrstr); 136 } 137 #endif 138 139 iba.iba_tag = &sc->sc_i2c; 140 (void) config_found_ia(&sc->sc_dev, "i2cbus", &iba, iicbus_print); 141 } 142 143 #ifdef XBOX 144 static int 145 amdpm_smbus_intr(void *cookie) 146 { 147 struct amdpm_softc *sc; 148 uint32_t status; 149 150 sc = (struct amdpm_softc *)cookie; 151 152 if (arch_i386_is_xbox) { 153 status = bus_space_read_4(sc->sc_iot, sc->sc_sm_ioh, 0x20); 154 bus_space_write_4(sc->sc_iot, sc->sc_sm_ioh, 0x20, status); 155 156 if (status & 2) 157 return iic_smbus_intr(&sc->sc_i2c); 158 } 159 160 return 0; 161 } 162 #endif 163 164 static int 165 amdpm_smbus_acquire_bus(void *cookie, int flags) 166 { 167 struct amdpm_softc *sc = cookie; 168 int err; 169 170 err = lockmgr(&sc->sc_lock, LK_EXCLUSIVE, NULL); 171 172 return err; 173 } 174 175 static void 176 amdpm_smbus_release_bus(void *cookie, int flags) 177 { 178 struct amdpm_softc *sc = cookie; 179 180 lockmgr(&sc->sc_lock, LK_RELEASE, NULL); 181 182 return; 183 } 184 185 static int 186 amdpm_smbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmd, 187 size_t cmdlen, void *vbuf, size_t buflen, int flags) 188 { 189 struct amdpm_softc *sc = (struct amdpm_softc *) cookie; 190 sc->sc_smbus_slaveaddr = addr; 191 u_int8_t *p = vbuf; 192 int rv; 193 194 if (I2C_OP_READ_P(op) && (cmdlen == 0) && (buflen == 1)) { 195 rv = amdpm_smbus_receive_1(sc, op); 196 if (rv == -1) 197 return -1; 198 *p = (u_int8_t)rv; 199 return 0; 200 } 201 202 if ( (I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 1)) { 203 rv = amdpm_smbus_read_1(sc, *(const uint8_t*)cmd, op); 204 if (rv == -1) 205 return -1; 206 *p = (u_int8_t)rv; 207 return 0; 208 } 209 210 if ( (I2C_OP_WRITE_P(op)) && (cmdlen == 0) && (buflen == 1)) { 211 return amdpm_smbus_send_1(sc, *(uint8_t*)vbuf, op); 212 } 213 214 if ( (I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 1)) { 215 return amdpm_smbus_write_1(sc, *(const uint8_t*)cmd, *(uint8_t*)vbuf, op); 216 } 217 218 return (-1); 219 } 220 221 static int 222 amdpm_smbus_check_done(struct amdpm_softc *sc, i2c_op_t op) 223 { 224 int i = 0; 225 for (i = 0; i < 1000; i++) { 226 /* check gsr and wait till cycle is done */ 227 u_int16_t data = amdpm_smbus_get_gsr(sc); 228 if (data & AMDPM_8111_GSR_CYCLE_DONE) { 229 return (0); 230 } 231 if (!(op & I2C_F_POLL)) 232 delay(1); 233 } 234 return (-1); 235 } 236 237 238 static void 239 amdpm_smbus_clear_gsr(struct amdpm_softc *sc) 240 { 241 /* clear register */ 242 u_int16_t data = 0xFFFF; 243 int off = (sc->sc_nforce ? 0xe0 : 0); 244 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 245 AMDPM_8111_SMBUS_STAT - off, data); 246 } 247 248 static u_int16_t 249 amdpm_smbus_get_gsr(struct amdpm_softc *sc) 250 { 251 int off = (sc->sc_nforce ? 0xe0 : 0); 252 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, 253 AMDPM_8111_SMBUS_STAT - off)); 254 } 255 256 static int 257 amdpm_smbus_send_1(struct amdpm_softc *sc, u_int8_t val, i2c_op_t op) 258 { 259 u_int16_t data = 0; 260 int off = (sc->sc_nforce ? 0xe0 : 0); 261 262 /* first clear gsr */ 263 amdpm_smbus_clear_gsr(sc); 264 265 /* write smbus slave address to register */ 266 data = sc->sc_smbus_slaveaddr; 267 data <<= 1; 268 data |= AMDPM_8111_SMBUS_SEND; 269 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 270 AMDPM_8111_SMBUS_HOSTADDR - off, data); 271 272 data = val; 273 /* store data */ 274 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 275 AMDPM_8111_SMBUS_HOSTDATA - off, data); 276 /* host start */ 277 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 278 AMDPM_8111_SMBUS_CTRL - off, 279 AMDPM_8111_SMBUS_GSR_SB); 280 281 return(amdpm_smbus_check_done(sc, op)); 282 } 283 284 285 static int 286 amdpm_smbus_write_1(struct amdpm_softc *sc, u_int8_t cmd, u_int8_t val, i2c_op_t op) 287 { 288 u_int16_t data = 0; 289 int off = (sc->sc_nforce ? 0xe0 : 0); 290 291 /* first clear gsr */ 292 amdpm_smbus_clear_gsr(sc); 293 294 data = sc->sc_smbus_slaveaddr; 295 data <<= 1; 296 data |= AMDPM_8111_SMBUS_WRITE; 297 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 298 AMDPM_8111_SMBUS_HOSTADDR - off, data); 299 300 data = val; 301 /* store cmd */ 302 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 303 AMDPM_8111_SMBUS_HOSTCMD - off, cmd); 304 /* store data */ 305 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 306 AMDPM_8111_SMBUS_HOSTDATA - off, data); 307 /* host start */ 308 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 309 AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_WB); 310 311 return (amdpm_smbus_check_done(sc, op)); 312 } 313 314 static int 315 amdpm_smbus_receive_1(struct amdpm_softc *sc, i2c_op_t op) 316 { 317 u_int16_t data = 0; 318 int off = (sc->sc_nforce ? 0xe0 : 0); 319 320 /* first clear gsr */ 321 amdpm_smbus_clear_gsr(sc); 322 323 /* write smbus slave address to register */ 324 data = sc->sc_smbus_slaveaddr; 325 data <<= 1; 326 data |= AMDPM_8111_SMBUS_RX; 327 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 328 AMDPM_8111_SMBUS_HOSTADDR - off, data); 329 330 /* start smbus cycle */ 331 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 332 AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_RXB); 333 334 /* check for errors */ 335 if (amdpm_smbus_check_done(sc, op) < 0) 336 return (-1); 337 338 /* read data */ 339 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 340 AMDPM_8111_SMBUS_HOSTDATA - off); 341 u_int8_t ret = (u_int8_t)(data & 0x00FF); 342 return (ret); 343 } 344 345 static int 346 amdpm_smbus_read_1(struct amdpm_softc *sc, u_int8_t cmd, i2c_op_t op) 347 { 348 u_int16_t data = 0; 349 u_int8_t ret; 350 int off = (sc->sc_nforce ? 0xe0 : 0); 351 352 /* first clear gsr */ 353 amdpm_smbus_clear_gsr(sc); 354 355 /* write smbus slave address to register */ 356 data = sc->sc_smbus_slaveaddr; 357 data <<= 1; 358 data |= AMDPM_8111_SMBUS_READ; 359 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 360 AMDPM_8111_SMBUS_HOSTADDR - off, data); 361 362 /* store cmd */ 363 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 364 AMDPM_8111_SMBUS_HOSTCMD - off, cmd); 365 /* host start */ 366 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 367 AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_RB); 368 369 /* check for errors */ 370 if (amdpm_smbus_check_done(sc, op) < 0) 371 return (-1); 372 373 /* store data */ 374 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 375 AMDPM_8111_SMBUS_HOSTDATA - off); 376 ret = (u_int8_t)(data & 0x00FF); 377 return (ret); 378 } 379
Indexes created Wed Oct 01 18:09:54 GMT 2025