amdpm_smbus.c revision 1.14
1 /* $NetBSD: amdpm_smbus.c,v 1.14 2007/08/27 15:57:13 xtraeme Exp $ */ 2 3 /* 4 * Copyright (c) 2005 Anil Gopinath (anil_public (at) yahoo.com) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* driver for SMBUS 1.0 host controller found in the 32 * AMD-8111 HyperTransport I/O Hub 33 */ 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: amdpm_smbus.c,v 1.14 2007/08/27 15:57:13 xtraeme Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 #include <sys/rnd.h> 42 #include <sys/rwlock.h> 43 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcidevs.h> 47 48 #include <dev/i2c/i2cvar.h> 49 #include <dev/i2c/i2c_bitbang.h> 50 51 #include <dev/pci/amdpmreg.h> 52 #include <dev/pci/amdpmvar.h> 53 54 #include <dev/pci/amdpm_smbusreg.h> 55 56 #ifdef __i386__ 57 #include "opt_xbox.h" 58 #endif 59 60 #ifdef XBOX 61 extern int arch_i386_is_xbox; 62 #endif 63 64 static int amdpm_smbus_acquire_bus(void *, int); 65 static void amdpm_smbus_release_bus(void *, int); 66 static int amdpm_smbus_exec(void *, i2c_op_t, i2c_addr_t, const void *, 67 size_t, void *, size_t, int); 68 static int amdpm_smbus_check_done(struct amdpm_softc *, i2c_op_t); 69 static void amdpm_smbus_clear_gsr(struct amdpm_softc *); 70 static uint16_t amdpm_smbus_get_gsr(struct amdpm_softc *); 71 static int amdpm_smbus_send_1(struct amdpm_softc *, uint8_t, i2c_op_t); 72 static int amdpm_smbus_write_1(struct amdpm_softc *, uint8_t, 73 uint8_t, i2c_op_t); 74 static int amdpm_smbus_receive_1(struct amdpm_softc *, i2c_op_t); 75 static int amdpm_smbus_read_1(struct amdpm_softc *sc, uint8_t, i2c_op_t); 76 77 #ifdef XBOX 78 static int amdpm_smbus_intr(void *); 79 #endif 80 81 void 82 amdpm_smbus_attach(struct amdpm_softc *sc) 83 { 84 struct i2cbus_attach_args iba; 85 #ifdef XBOX 86 pci_intr_handle_t ih; 87 const char *intrstr; 88 #endif 89 90 /* register with iic */ 91 sc->sc_i2c.ic_cookie = sc; 92 sc->sc_i2c.ic_acquire_bus = amdpm_smbus_acquire_bus; 93 sc->sc_i2c.ic_release_bus = amdpm_smbus_release_bus; 94 sc->sc_i2c.ic_send_start = NULL; 95 sc->sc_i2c.ic_send_stop = NULL; 96 sc->sc_i2c.ic_initiate_xfer = NULL; 97 sc->sc_i2c.ic_read_byte = NULL; 98 sc->sc_i2c.ic_write_byte = NULL; 99 sc->sc_i2c.ic_exec = amdpm_smbus_exec; 100 101 rw_init(&sc->sc_rwlock); 102 103 #ifdef XBOX 104 #define XBOX_SMBA 0x8000 105 #define XBOX_SMSIZE 256 106 #define XBOX_INTRLINE 12 107 #define XBOX_REG_ACPI_PM1a_EN 0x02 108 #define XBOX_REG_ACPI_PM1a_EN_TIMER 0x01 109 /* XXX pci0 dev 1 function 2 "System Management" doesn't probe */ 110 if (arch_i386_is_xbox) { 111 uint16_t val; 112 sc->sc_pa->pa_intrline = XBOX_INTRLINE; 113 114 if (bus_space_map(sc->sc_iot, XBOX_SMBA, XBOX_SMSIZE, 115 0, &sc->sc_sm_ioh) == 0) { 116 aprint_normal("%s: system management at 0x%04x\n", 117 sc->sc_dev.dv_xname, XBOX_SMBA); 118 119 /* Disable PM ACPI timer SCI interrupt */ 120 val = bus_space_read_2(sc->sc_iot, sc->sc_sm_ioh, 121 XBOX_REG_ACPI_PM1a_EN); 122 bus_space_write_2(sc->sc_iot, sc->sc_sm_ioh, 123 XBOX_REG_ACPI_PM1a_EN, 124 val & ~XBOX_REG_ACPI_PM1a_EN_TIMER); 125 } 126 } 127 128 if (pci_intr_map(sc->sc_pa, &ih)) 129 aprint_error("%s: couldn't map interrupt\n", 130 sc->sc_dev.dv_xname); 131 else { 132 intrstr = pci_intr_string(sc->sc_pc, ih); 133 sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_BIO, 134 amdpm_smbus_intr, sc); 135 if (sc->sc_ih != NULL) 136 aprint_normal("%s: interrupting at %s\n", 137 sc->sc_dev.dv_xname, intrstr); 138 } 139 #endif 140 141 iba.iba_tag = &sc->sc_i2c; 142 (void)config_found_ia(&sc->sc_dev, "i2cbus", &iba, iicbus_print); 143 } 144 145 #ifdef XBOX 146 static int 147 amdpm_smbus_intr(void *cookie) 148 { 149 struct amdpm_softc *sc; 150 uint32_t status; 151 152 sc = (struct amdpm_softc *)cookie; 153 154 if (arch_i386_is_xbox) { 155 status = bus_space_read_4(sc->sc_iot, sc->sc_sm_ioh, 0x20); 156 bus_space_write_4(sc->sc_iot, sc->sc_sm_ioh, 0x20, status); 157 158 if (status & 2) 159 return iic_smbus_intr(&sc->sc_i2c); 160 } 161 162 return 0; 163 } 164 #endif 165 166 static int 167 amdpm_smbus_acquire_bus(void *cookie, int flags) 168 { 169 struct amdpm_softc *sc = cookie; 170 171 rw_enter(&sc->sc_rwlock, RW_WRITER); 172 return 0; 173 } 174 175 static void 176 amdpm_smbus_release_bus(void *cookie, int flags) 177 { 178 struct amdpm_softc *sc = cookie; 179 180 rw_exit(&sc->sc_rwlock); 181 } 182 183 static int 184 amdpm_smbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmd, 185 size_t cmdlen, void *vbuf, size_t buflen, int flags) 186 { 187 struct amdpm_softc *sc = (struct amdpm_softc *) cookie; 188 sc->sc_smbus_slaveaddr = addr; 189 uint8_t *p = vbuf; 190 int rv; 191 192 if (I2C_OP_READ_P(op) && (cmdlen == 0) && (buflen == 1)) { 193 rv = amdpm_smbus_receive_1(sc, op); 194 if (rv == -1) 195 return -1; 196 *p = (uint8_t)rv; 197 return 0; 198 } 199 200 if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 1)) { 201 rv = amdpm_smbus_read_1(sc, *(const uint8_t *)cmd, op); 202 if (rv == -1) 203 return -1; 204 *p = (uint8_t)rv; 205 return 0; 206 } 207 208 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 0) && (buflen == 1)) 209 return amdpm_smbus_send_1(sc, *(uint8_t*)vbuf, op); 210 211 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 1)) 212 return amdpm_smbus_write_1(sc, 213 *(const uint8_t*)cmd, 214 *(uint8_t*)vbuf, 215 op); 216 217 return -1; 218 } 219 220 static int 221 amdpm_smbus_check_done(struct amdpm_softc *sc, i2c_op_t op) 222 { 223 int i; 224 225 for (i = 0; i < 1000; i++) { 226 /* check gsr and wait till cycle is done */ 227 uint16_t data = amdpm_smbus_get_gsr(sc); 228 if (data & AMDPM_8111_GSR_CYCLE_DONE) 229 return 0; 230 } 231 232 if (!(op & I2C_F_POLL)) 233 delay(1); 234 235 return -1; 236 } 237 238 239 static void 240 amdpm_smbus_clear_gsr(struct amdpm_softc *sc) 241 { 242 /* clear register */ 243 uint16_t data = 0xFFFF; 244 int off = (sc->sc_nforce ? 0xe0 : 0); 245 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 246 AMDPM_8111_SMBUS_STAT - off, data); 247 } 248 249 static uint16_t 250 amdpm_smbus_get_gsr(struct amdpm_softc *sc) 251 { 252 int off = (sc->sc_nforce ? 0xe0 : 0); 253 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, 254 AMDPM_8111_SMBUS_STAT - off); 255 } 256 257 static int 258 amdpm_smbus_send_1(struct amdpm_softc *sc, uint8_t val, i2c_op_t op) 259 { 260 uint16_t data = 0; 261 int off = (sc->sc_nforce ? 0xe0 : 0); 262 263 /* first clear gsr */ 264 amdpm_smbus_clear_gsr(sc); 265 266 /* write smbus slave address to register */ 267 data = sc->sc_smbus_slaveaddr; 268 data <<= 1; 269 data |= AMDPM_8111_SMBUS_SEND; 270 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 271 AMDPM_8111_SMBUS_HOSTADDR - off, data); 272 273 data = val; 274 /* store data */ 275 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 276 AMDPM_8111_SMBUS_HOSTDATA - off, data); 277 /* host start */ 278 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 279 AMDPM_8111_SMBUS_CTRL - off, 280 AMDPM_8111_SMBUS_GSR_SB); 281 282 return amdpm_smbus_check_done(sc, op); 283 } 284 285 286 static int 287 amdpm_smbus_write_1(struct amdpm_softc *sc, uint8_t cmd, uint8_t val, 288 i2c_op_t op) 289 { 290 uint16_t data = 0; 291 int off = (sc->sc_nforce ? 0xe0 : 0); 292 293 /* first clear gsr */ 294 amdpm_smbus_clear_gsr(sc); 295 296 data = sc->sc_smbus_slaveaddr; 297 data <<= 1; 298 data |= AMDPM_8111_SMBUS_WRITE; 299 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 300 AMDPM_8111_SMBUS_HOSTADDR - off, data); 301 302 data = val; 303 /* store cmd */ 304 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 305 AMDPM_8111_SMBUS_HOSTCMD - off, cmd); 306 /* store data */ 307 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 308 AMDPM_8111_SMBUS_HOSTDATA - off, data); 309 /* host start */ 310 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 311 AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_WB); 312 313 return amdpm_smbus_check_done(sc, op); 314 } 315 316 static int 317 amdpm_smbus_receive_1(struct amdpm_softc *sc, i2c_op_t op) 318 { 319 uint16_t data = 0; 320 int off = (sc->sc_nforce ? 0xe0 : 0); 321 322 /* first clear gsr */ 323 amdpm_smbus_clear_gsr(sc); 324 325 /* write smbus slave address to register */ 326 data = sc->sc_smbus_slaveaddr; 327 data <<= 1; 328 data |= AMDPM_8111_SMBUS_RX; 329 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 330 AMDPM_8111_SMBUS_HOSTADDR - off, data); 331 332 /* start smbus cycle */ 333 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 334 AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_RXB); 335 336 /* check for errors */ 337 if (amdpm_smbus_check_done(sc, op) < 0) 338 return -1; 339 340 /* read data */ 341 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 342 AMDPM_8111_SMBUS_HOSTDATA - off); 343 uint8_t ret = (uint8_t)(data & 0x00FF); 344 return ret; 345 } 346 347 static int 348 amdpm_smbus_read_1(struct amdpm_softc *sc, uint8_t cmd, i2c_op_t op) 349 { 350 uint16_t data = 0; 351 uint8_t ret; 352 int off = (sc->sc_nforce ? 0xe0 : 0); 353 354 /* first clear gsr */ 355 amdpm_smbus_clear_gsr(sc); 356 357 /* write smbus slave address to register */ 358 data = sc->sc_smbus_slaveaddr; 359 data <<= 1; 360 data |= AMDPM_8111_SMBUS_READ; 361 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 362 AMDPM_8111_SMBUS_HOSTADDR - off, data); 363 364 /* store cmd */ 365 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 366 AMDPM_8111_SMBUS_HOSTCMD - off, cmd); 367 /* host start */ 368 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 369 AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_RB); 370 371 /* check for errors */ 372 if (amdpm_smbus_check_done(sc, op) < 0) 373 return -1; 374 375 /* store data */ 376 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 377 AMDPM_8111_SMBUS_HOSTDATA - off); 378 ret = (uint8_t)(data & 0x00FF); 379 return ret; 380 } 381
Indexes created Wed Oct 01 13:09:50 GMT 2025