amdpm_smbus.c revision 1.15
1 /* $NetBSD: amdpm_smbus.c,v 1.15 2008/04/10 19:13:36 cegger Exp $ */ 2 3 /* 4 * Copyright (c) 2005 Anil Gopinath (anil_public (at) yahoo.com) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* driver for SMBUS 1.0 host controller found in the 32 * AMD-8111 HyperTransport I/O Hub 33 */ 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: amdpm_smbus.c,v 1.15 2008/04/10 19:13:36 cegger Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 #include <sys/rnd.h> 42 #include <sys/rwlock.h> 43 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcidevs.h> 47 48 #include <dev/i2c/i2cvar.h> 49 #include <dev/i2c/i2c_bitbang.h> 50 51 #include <dev/pci/amdpmreg.h> 52 #include <dev/pci/amdpmvar.h> 53 54 #include <dev/pci/amdpm_smbusreg.h> 55 56 #ifdef __i386__ 57 #include "opt_xbox.h" 58 #endif 59 60 #ifdef XBOX 61 extern int arch_i386_is_xbox; 62 #endif 63 64 static int amdpm_smbus_acquire_bus(void *, int); 65 static void amdpm_smbus_release_bus(void *, int); 66 static int amdpm_smbus_exec(void *, i2c_op_t, i2c_addr_t, const void *, 67 size_t, void *, size_t, int); 68 static int amdpm_smbus_check_done(struct amdpm_softc *, i2c_op_t); 69 static void amdpm_smbus_clear_gsr(struct amdpm_softc *); 70 static uint16_t amdpm_smbus_get_gsr(struct amdpm_softc *); 71 static int amdpm_smbus_send_1(struct amdpm_softc *, uint8_t, i2c_op_t); 72 static int amdpm_smbus_write_1(struct amdpm_softc *, uint8_t, 73 uint8_t, i2c_op_t); 74 static int amdpm_smbus_receive_1(struct amdpm_softc *, i2c_op_t); 75 static int amdpm_smbus_read_1(struct amdpm_softc *sc, uint8_t, i2c_op_t); 76 77 #ifdef XBOX 78 static int amdpm_smbus_intr(void *); 79 #endif 80 81 void 82 amdpm_smbus_attach(struct amdpm_softc *sc) 83 { 84 struct i2cbus_attach_args iba; 85 #ifdef XBOX 86 pci_intr_handle_t ih; 87 const char *intrstr; 88 #endif 89 90 /* register with iic */ 91 sc->sc_i2c.ic_cookie = sc; 92 sc->sc_i2c.ic_acquire_bus = amdpm_smbus_acquire_bus; 93 sc->sc_i2c.ic_release_bus = amdpm_smbus_release_bus; 94 sc->sc_i2c.ic_send_start = NULL; 95 sc->sc_i2c.ic_send_stop = NULL; 96 sc->sc_i2c.ic_initiate_xfer = NULL; 97 sc->sc_i2c.ic_read_byte = NULL; 98 sc->sc_i2c.ic_write_byte = NULL; 99 sc->sc_i2c.ic_exec = amdpm_smbus_exec; 100 101 rw_init(&sc->sc_rwlock); 102 103 #ifdef XBOX 104 #define XBOX_SMBA 0x8000 105 #define XBOX_SMSIZE 256 106 #define XBOX_INTRLINE 12 107 #define XBOX_REG_ACPI_PM1a_EN 0x02 108 #define XBOX_REG_ACPI_PM1a_EN_TIMER 0x01 109 /* XXX pci0 dev 1 function 2 "System Management" doesn't probe */ 110 if (arch_i386_is_xbox) { 111 uint16_t val; 112 sc->sc_pa->pa_intrline = XBOX_INTRLINE; 113 114 if (bus_space_map(sc->sc_iot, XBOX_SMBA, XBOX_SMSIZE, 115 0, &sc->sc_sm_ioh) == 0) { 116 aprint_normal_dev(&sc->sc_dev, "system management at 0x%04x\n", XBOX_SMBA); 117 118 /* Disable PM ACPI timer SCI interrupt */ 119 val = bus_space_read_2(sc->sc_iot, sc->sc_sm_ioh, 120 XBOX_REG_ACPI_PM1a_EN); 121 bus_space_write_2(sc->sc_iot, sc->sc_sm_ioh, 122 XBOX_REG_ACPI_PM1a_EN, 123 val & ~XBOX_REG_ACPI_PM1a_EN_TIMER); 124 } 125 } 126 127 if (pci_intr_map(sc->sc_pa, &ih)) 128 aprint_error_dev(&sc->sc_dev, "couldn't map interrupt\n"); 129 else { 130 intrstr = pci_intr_string(sc->sc_pc, ih); 131 sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_BIO, 132 amdpm_smbus_intr, sc); 133 if (sc->sc_ih != NULL) 134 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", 135 intrstr); 136 } 137 #endif 138 139 iba.iba_tag = &sc->sc_i2c; 140 (void)config_found_ia(&sc->sc_dev, "i2cbus", &iba, iicbus_print); 141 } 142 143 #ifdef XBOX 144 static int 145 amdpm_smbus_intr(void *cookie) 146 { 147 struct amdpm_softc *sc; 148 uint32_t status; 149 150 sc = (struct amdpm_softc *)cookie; 151 152 if (arch_i386_is_xbox) { 153 status = bus_space_read_4(sc->sc_iot, sc->sc_sm_ioh, 0x20); 154 bus_space_write_4(sc->sc_iot, sc->sc_sm_ioh, 0x20, status); 155 156 if (status & 2) 157 return iic_smbus_intr(&sc->sc_i2c); 158 } 159 160 return 0; 161 } 162 #endif 163 164 static int 165 amdpm_smbus_acquire_bus(void *cookie, int flags) 166 { 167 struct amdpm_softc *sc = cookie; 168 169 rw_enter(&sc->sc_rwlock, RW_WRITER); 170 return 0; 171 } 172 173 static void 174 amdpm_smbus_release_bus(void *cookie, int flags) 175 { 176 struct amdpm_softc *sc = cookie; 177 178 rw_exit(&sc->sc_rwlock); 179 } 180 181 static int 182 amdpm_smbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmd, 183 size_t cmdlen, void *vbuf, size_t buflen, int flags) 184 { 185 struct amdpm_softc *sc = (struct amdpm_softc *) cookie; 186 sc->sc_smbus_slaveaddr = addr; 187 uint8_t *p = vbuf; 188 int rv; 189 190 if (I2C_OP_READ_P(op) && (cmdlen == 0) && (buflen == 1)) { 191 rv = amdpm_smbus_receive_1(sc, op); 192 if (rv == -1) 193 return -1; 194 *p = (uint8_t)rv; 195 return 0; 196 } 197 198 if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 1)) { 199 rv = amdpm_smbus_read_1(sc, *(const uint8_t *)cmd, op); 200 if (rv == -1) 201 return -1; 202 *p = (uint8_t)rv; 203 return 0; 204 } 205 206 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 0) && (buflen == 1)) 207 return amdpm_smbus_send_1(sc, *(uint8_t*)vbuf, op); 208 209 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 1)) 210 return amdpm_smbus_write_1(sc, 211 *(const uint8_t*)cmd, 212 *(uint8_t*)vbuf, 213 op); 214 215 return -1; 216 } 217 218 static int 219 amdpm_smbus_check_done(struct amdpm_softc *sc, i2c_op_t op) 220 { 221 int i; 222 223 for (i = 0; i < 1000; i++) { 224 /* check gsr and wait till cycle is done */ 225 uint16_t data = amdpm_smbus_get_gsr(sc); 226 if (data & AMDPM_8111_GSR_CYCLE_DONE) 227 return 0; 228 } 229 230 if (!(op & I2C_F_POLL)) 231 delay(1); 232 233 return -1; 234 } 235 236 237 static void 238 amdpm_smbus_clear_gsr(struct amdpm_softc *sc) 239 { 240 /* clear register */ 241 uint16_t data = 0xFFFF; 242 int off = (sc->sc_nforce ? 0xe0 : 0); 243 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 244 AMDPM_8111_SMBUS_STAT - off, data); 245 } 246 247 static uint16_t 248 amdpm_smbus_get_gsr(struct amdpm_softc *sc) 249 { 250 int off = (sc->sc_nforce ? 0xe0 : 0); 251 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, 252 AMDPM_8111_SMBUS_STAT - off); 253 } 254 255 static int 256 amdpm_smbus_send_1(struct amdpm_softc *sc, uint8_t val, i2c_op_t op) 257 { 258 uint16_t data = 0; 259 int off = (sc->sc_nforce ? 0xe0 : 0); 260 261 /* first clear gsr */ 262 amdpm_smbus_clear_gsr(sc); 263 264 /* write smbus slave address to register */ 265 data = sc->sc_smbus_slaveaddr; 266 data <<= 1; 267 data |= AMDPM_8111_SMBUS_SEND; 268 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 269 AMDPM_8111_SMBUS_HOSTADDR - off, data); 270 271 data = val; 272 /* store data */ 273 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 274 AMDPM_8111_SMBUS_HOSTDATA - off, data); 275 /* host start */ 276 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 277 AMDPM_8111_SMBUS_CTRL - off, 278 AMDPM_8111_SMBUS_GSR_SB); 279 280 return amdpm_smbus_check_done(sc, op); 281 } 282 283 284 static int 285 amdpm_smbus_write_1(struct amdpm_softc *sc, uint8_t cmd, uint8_t val, 286 i2c_op_t op) 287 { 288 uint16_t data = 0; 289 int off = (sc->sc_nforce ? 0xe0 : 0); 290 291 /* first clear gsr */ 292 amdpm_smbus_clear_gsr(sc); 293 294 data = sc->sc_smbus_slaveaddr; 295 data <<= 1; 296 data |= AMDPM_8111_SMBUS_WRITE; 297 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 298 AMDPM_8111_SMBUS_HOSTADDR - off, data); 299 300 data = val; 301 /* store cmd */ 302 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 303 AMDPM_8111_SMBUS_HOSTCMD - off, cmd); 304 /* store data */ 305 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 306 AMDPM_8111_SMBUS_HOSTDATA - off, data); 307 /* host start */ 308 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 309 AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_WB); 310 311 return amdpm_smbus_check_done(sc, op); 312 } 313 314 static int 315 amdpm_smbus_receive_1(struct amdpm_softc *sc, i2c_op_t op) 316 { 317 uint16_t data = 0; 318 int off = (sc->sc_nforce ? 0xe0 : 0); 319 320 /* first clear gsr */ 321 amdpm_smbus_clear_gsr(sc); 322 323 /* write smbus slave address to register */ 324 data = sc->sc_smbus_slaveaddr; 325 data <<= 1; 326 data |= AMDPM_8111_SMBUS_RX; 327 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 328 AMDPM_8111_SMBUS_HOSTADDR - off, data); 329 330 /* start smbus cycle */ 331 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 332 AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_RXB); 333 334 /* check for errors */ 335 if (amdpm_smbus_check_done(sc, op) < 0) 336 return -1; 337 338 /* read data */ 339 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 340 AMDPM_8111_SMBUS_HOSTDATA - off); 341 uint8_t ret = (uint8_t)(data & 0x00FF); 342 return ret; 343 } 344 345 static int 346 amdpm_smbus_read_1(struct amdpm_softc *sc, uint8_t cmd, i2c_op_t op) 347 { 348 uint16_t data = 0; 349 uint8_t ret; 350 int off = (sc->sc_nforce ? 0xe0 : 0); 351 352 /* first clear gsr */ 353 amdpm_smbus_clear_gsr(sc); 354 355 /* write smbus slave address to register */ 356 data = sc->sc_smbus_slaveaddr; 357 data <<= 1; 358 data |= AMDPM_8111_SMBUS_READ; 359 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 360 AMDPM_8111_SMBUS_HOSTADDR - off, data); 361 362 /* store cmd */ 363 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 364 AMDPM_8111_SMBUS_HOSTCMD - off, cmd); 365 /* host start */ 366 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 367 AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_RB); 368 369 /* check for errors */ 370 if (amdpm_smbus_check_done(sc, op) < 0) 371 return -1; 372 373 /* store data */ 374 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 375 AMDPM_8111_SMBUS_HOSTDATA - off); 376 ret = (uint8_t)(data & 0x00FF); 377 return ret; 378 } 379
Indexes created Wed Oct 01 18:09:54 GMT 2025