amdpm_smbus.c revision 1.19
1 /* $NetBSD: amdpm_smbus.c,v 1.19 2012/10/27 17:18:28 chs Exp $ */ 2 3 /* 4 * Copyright (c) 2005 Anil Gopinath (anil_public (at) yahoo.com) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* driver for SMBUS 1.0 host controller found in the 32 * AMD-8111 HyperTransport I/O Hub 33 */ 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: amdpm_smbus.c,v 1.19 2012/10/27 17:18:28 chs Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 #include <sys/rnd.h> 42 #include <sys/mutex.h> 43 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcidevs.h> 47 48 #include <dev/i2c/i2cvar.h> 49 #include <dev/i2c/i2c_bitbang.h> 50 51 #include <dev/pci/amdpmreg.h> 52 #include <dev/pci/amdpmvar.h> 53 54 #include <dev/pci/amdpm_smbusreg.h> 55 56 static int amdpm_smbus_acquire_bus(void *, int); 57 static void amdpm_smbus_release_bus(void *, int); 58 static int amdpm_smbus_exec(void *, i2c_op_t, i2c_addr_t, const void *, 59 size_t, void *, size_t, int); 60 static int amdpm_smbus_check_done(struct amdpm_softc *, i2c_op_t); 61 static void amdpm_smbus_clear_gsr(struct amdpm_softc *); 62 static uint16_t amdpm_smbus_get_gsr(struct amdpm_softc *); 63 static int amdpm_smbus_quick(struct amdpm_softc *, i2c_op_t); 64 static int amdpm_smbus_send_1(struct amdpm_softc *, uint8_t, i2c_op_t); 65 static int amdpm_smbus_write_1(struct amdpm_softc *, uint8_t, 66 uint8_t, i2c_op_t); 67 static int amdpm_smbus_receive_1(struct amdpm_softc *, i2c_op_t); 68 static int amdpm_smbus_read_1(struct amdpm_softc *sc, uint8_t, i2c_op_t); 69 70 void 71 amdpm_smbus_attach(struct amdpm_softc *sc) 72 { 73 struct i2cbus_attach_args iba; 74 75 /* register with iic */ 76 sc->sc_i2c.ic_cookie = sc; 77 sc->sc_i2c.ic_acquire_bus = amdpm_smbus_acquire_bus; 78 sc->sc_i2c.ic_release_bus = amdpm_smbus_release_bus; 79 sc->sc_i2c.ic_send_start = NULL; 80 sc->sc_i2c.ic_send_stop = NULL; 81 sc->sc_i2c.ic_initiate_xfer = NULL; 82 sc->sc_i2c.ic_read_byte = NULL; 83 sc->sc_i2c.ic_write_byte = NULL; 84 sc->sc_i2c.ic_exec = amdpm_smbus_exec; 85 86 mutex_init(&sc->sc_mutex, MUTEX_DEFAULT, IPL_NONE); 87 88 iba.iba_tag = &sc->sc_i2c; 89 (void)config_found_ia(sc->sc_dev, "i2cbus", &iba, iicbus_print); 90 } 91 92 static int 93 amdpm_smbus_acquire_bus(void *cookie, int flags) 94 { 95 struct amdpm_softc *sc = cookie; 96 97 mutex_enter(&sc->sc_mutex); 98 return 0; 99 } 100 101 static void 102 amdpm_smbus_release_bus(void *cookie, int flags) 103 { 104 struct amdpm_softc *sc = cookie; 105 106 mutex_exit(&sc->sc_mutex); 107 } 108 109 static int 110 amdpm_smbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmd, 111 size_t cmdlen, void *vbuf, size_t buflen, int flags) 112 { 113 struct amdpm_softc *sc = (struct amdpm_softc *) cookie; 114 sc->sc_smbus_slaveaddr = addr; 115 uint8_t *p = vbuf; 116 int rv; 117 118 if ((cmdlen == 0) && (buflen == 0)) 119 return amdpm_smbus_quick(sc, op); 120 121 if (I2C_OP_READ_P(op) && (cmdlen == 0) && (buflen == 1)) { 122 rv = amdpm_smbus_receive_1(sc, op); 123 if (rv == -1) 124 return -1; 125 *p = (uint8_t)rv; 126 return 0; 127 } 128 129 if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 1)) { 130 rv = amdpm_smbus_read_1(sc, *(const uint8_t *)cmd, op); 131 if (rv == -1) 132 return -1; 133 *p = (uint8_t)rv; 134 return 0; 135 } 136 137 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 0) && (buflen == 1)) 138 return amdpm_smbus_send_1(sc, *(uint8_t*)vbuf, op); 139 140 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 1)) 141 return amdpm_smbus_write_1(sc, 142 *(const uint8_t*)cmd, 143 *(uint8_t*)vbuf, 144 op); 145 146 return -1; 147 } 148 149 static int 150 amdpm_smbus_check_done(struct amdpm_softc *sc, i2c_op_t op) 151 { 152 int i; 153 154 for (i = 0; i < 1000; i++) { 155 /* check gsr and wait till cycle is done */ 156 uint16_t data = amdpm_smbus_get_gsr(sc); 157 if (data & AMDPM_8111_GSR_CYCLE_DONE) 158 return 0; 159 } 160 161 if (!(op & I2C_F_POLL)) 162 delay(1); 163 164 return -1; 165 } 166 167 168 static void 169 amdpm_smbus_clear_gsr(struct amdpm_softc *sc) 170 { 171 /* clear register */ 172 uint16_t data = 0xFFFF; 173 int off = (sc->sc_nforce ? 0xe0 : 0); 174 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 175 AMDPM_8111_SMBUS_STAT - off, data); 176 } 177 178 static uint16_t 179 amdpm_smbus_get_gsr(struct amdpm_softc *sc) 180 { 181 int off = (sc->sc_nforce ? 0xe0 : 0); 182 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, 183 AMDPM_8111_SMBUS_STAT - off); 184 } 185 186 static int 187 amdpm_smbus_quick(struct amdpm_softc *sc, i2c_op_t op) 188 { 189 uint16_t data = 0; 190 int off = (sc->sc_nforce ? 0xe0 : 0); 191 192 /* first clear gsr */ 193 amdpm_smbus_clear_gsr(sc); 194 195 /* write smbus slave address and read/write bit to register */ 196 data = sc->sc_smbus_slaveaddr; 197 data <<= 1; 198 if (I2C_OP_READ_P(op)) 199 data |= AMDPM_8111_SMBUS_READ; 200 201 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 202 AMDPM_8111_SMBUS_HOSTADDR - off, data); 203 204 /* host start */ 205 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 206 AMDPM_8111_SMBUS_CTRL - off, 207 AMDPM_8111_SMBUS_GSR_QUICK); 208 209 return amdpm_smbus_check_done(sc, op); 210 } 211 212 static int 213 amdpm_smbus_send_1(struct amdpm_softc *sc, uint8_t val, i2c_op_t op) 214 { 215 uint16_t data = 0; 216 int off = (sc->sc_nforce ? 0xe0 : 0); 217 218 /* first clear gsr */ 219 amdpm_smbus_clear_gsr(sc); 220 221 /* write smbus slave address to register */ 222 data = sc->sc_smbus_slaveaddr; 223 data <<= 1; 224 data |= AMDPM_8111_SMBUS_SEND; 225 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 226 AMDPM_8111_SMBUS_HOSTADDR - off, data); 227 228 data = val; 229 /* store data */ 230 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 231 AMDPM_8111_SMBUS_HOSTDATA - off, data); 232 /* host start */ 233 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 234 AMDPM_8111_SMBUS_CTRL - off, 235 AMDPM_8111_SMBUS_GSR_SB); 236 237 return amdpm_smbus_check_done(sc, op); 238 } 239 240 241 static int 242 amdpm_smbus_write_1(struct amdpm_softc *sc, uint8_t cmd, uint8_t val, 243 i2c_op_t op) 244 { 245 uint16_t data = 0; 246 int off = (sc->sc_nforce ? 0xe0 : 0); 247 248 /* first clear gsr */ 249 amdpm_smbus_clear_gsr(sc); 250 251 data = sc->sc_smbus_slaveaddr; 252 data <<= 1; 253 data |= AMDPM_8111_SMBUS_WRITE; 254 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 255 AMDPM_8111_SMBUS_HOSTADDR - off, data); 256 257 data = val; 258 /* store cmd */ 259 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 260 AMDPM_8111_SMBUS_HOSTCMD - off, cmd); 261 /* store data */ 262 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 263 AMDPM_8111_SMBUS_HOSTDATA - off, data); 264 /* host start */ 265 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 266 AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_WB); 267 268 return amdpm_smbus_check_done(sc, op); 269 } 270 271 static int 272 amdpm_smbus_receive_1(struct amdpm_softc *sc, i2c_op_t op) 273 { 274 uint16_t data = 0; 275 int off = (sc->sc_nforce ? 0xe0 : 0); 276 277 /* first clear gsr */ 278 amdpm_smbus_clear_gsr(sc); 279 280 /* write smbus slave address to register */ 281 data = sc->sc_smbus_slaveaddr; 282 data <<= 1; 283 data |= AMDPM_8111_SMBUS_RX; 284 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 285 AMDPM_8111_SMBUS_HOSTADDR - off, data); 286 287 /* start smbus cycle */ 288 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 289 AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_RXB); 290 291 /* check for errors */ 292 if (amdpm_smbus_check_done(sc, op) < 0) 293 return -1; 294 295 /* read data */ 296 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 297 AMDPM_8111_SMBUS_HOSTDATA - off); 298 uint8_t ret = (uint8_t)(data & 0x00FF); 299 return ret; 300 } 301 302 static int 303 amdpm_smbus_read_1(struct amdpm_softc *sc, uint8_t cmd, i2c_op_t op) 304 { 305 uint16_t data = 0; 306 uint8_t ret; 307 int off = (sc->sc_nforce ? 0xe0 : 0); 308 309 /* first clear gsr */ 310 amdpm_smbus_clear_gsr(sc); 311 312 /* write smbus slave address to register */ 313 data = sc->sc_smbus_slaveaddr; 314 data <<= 1; 315 data |= AMDPM_8111_SMBUS_READ; 316 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 317 AMDPM_8111_SMBUS_HOSTADDR - off, data); 318 319 /* store cmd */ 320 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 321 AMDPM_8111_SMBUS_HOSTCMD - off, cmd); 322 /* host start */ 323 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 324 AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_RB); 325 326 /* check for errors */ 327 if (amdpm_smbus_check_done(sc, op) < 0) 328 return -1; 329 330 /* store data */ 331 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 332 AMDPM_8111_SMBUS_HOSTDATA - off); 333 ret = (uint8_t)(data & 0x00FF); 334 return ret; 335 } 336
Indexes created Wed Oct 01 18:09:54 GMT 2025