amdpm_smbus.c revision 1.23
1 /* $NetBSD: amdpm_smbus.c,v 1.23 2019/12/22 23:23:32 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2005 Anil Gopinath (anil_public (at) yahoo.com) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* driver for SMBUS 1.0 host controller found in the 32 * AMD-8111 HyperTransport I/O Hub 33 */ 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: amdpm_smbus.c,v 1.23 2019/12/22 23:23:32 thorpej Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 46 #include <dev/i2c/i2cvar.h> 47 #include <dev/i2c/i2c_bitbang.h> 48 49 #include <dev/pci/amdpmreg.h> 50 #include <dev/pci/amdpmvar.h> 51 52 #include <dev/pci/amdpm_smbusreg.h> 53 54 static int amdpm_smbus_exec(void *, i2c_op_t, i2c_addr_t, const void *, 55 size_t, void *, size_t, int); 56 static int amdpm_smbus_check_done(struct amdpm_softc *, i2c_op_t); 57 static void amdpm_smbus_clear_gsr(struct amdpm_softc *); 58 static uint16_t amdpm_smbus_get_gsr(struct amdpm_softc *); 59 static int amdpm_smbus_quick(struct amdpm_softc *, i2c_op_t); 60 static int amdpm_smbus_send_1(struct amdpm_softc *, uint8_t, i2c_op_t); 61 static int amdpm_smbus_write_1(struct amdpm_softc *, uint8_t, 62 uint8_t, i2c_op_t); 63 static int amdpm_smbus_receive_1(struct amdpm_softc *, i2c_op_t); 64 static int amdpm_smbus_read_1(struct amdpm_softc *sc, uint8_t, i2c_op_t); 65 66 void 67 amdpm_smbus_attach(struct amdpm_softc *sc) 68 { 69 struct i2cbus_attach_args iba; 70 71 /* register with iic */ 72 iic_tag_init(&sc->sc_i2c); 73 sc->sc_i2c.ic_cookie = sc; 74 sc->sc_i2c.ic_exec = amdpm_smbus_exec; 75 76 memset(&iba, 0, sizeof(iba)); 77 iba.iba_tag = &sc->sc_i2c; 78 (void)config_found_ia(sc->sc_dev, "i2cbus", &iba, iicbus_print); 79 } 80 81 static int 82 amdpm_smbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmd, 83 size_t cmdlen, void *vbuf, size_t buflen, int flags) 84 { 85 struct amdpm_softc *sc = (struct amdpm_softc *) cookie; 86 sc->sc_smbus_slaveaddr = addr; 87 uint8_t *p = vbuf; 88 int rv; 89 90 if ((cmdlen == 0) && (buflen == 0)) 91 return amdpm_smbus_quick(sc, op); 92 93 if (I2C_OP_READ_P(op) && (cmdlen == 0) && (buflen == 1)) { 94 rv = amdpm_smbus_receive_1(sc, op); 95 if (rv == -1) 96 return -1; 97 *p = (uint8_t)rv; 98 return 0; 99 } 100 101 if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 1)) { 102 rv = amdpm_smbus_read_1(sc, *(const uint8_t *)cmd, op); 103 if (rv == -1) 104 return -1; 105 *p = (uint8_t)rv; 106 return 0; 107 } 108 109 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 0) && (buflen == 1)) 110 return amdpm_smbus_send_1(sc, *(uint8_t*)vbuf, op); 111 112 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 1)) 113 return amdpm_smbus_write_1(sc, 114 *(const uint8_t*)cmd, 115 *(uint8_t*)vbuf, 116 op); 117 118 return -1; 119 } 120 121 static int 122 amdpm_smbus_check_done(struct amdpm_softc *sc, i2c_op_t op) 123 { 124 int i; 125 126 for (i = 0; i < 1000; i++) { 127 /* check gsr and wait till cycle is done */ 128 uint16_t data = amdpm_smbus_get_gsr(sc); 129 if (data & AMDPM_8111_GSR_CYCLE_DONE) 130 return 0; 131 } 132 133 if (!(op & I2C_F_POLL)) 134 delay(1); 135 136 return -1; 137 } 138 139 140 static void 141 amdpm_smbus_clear_gsr(struct amdpm_softc *sc) 142 { 143 /* clear register */ 144 uint16_t data = 0xFFFF; 145 int off = (sc->sc_nforce ? 0xe0 : 0); 146 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 147 AMDPM_8111_SMBUS_STAT - off, data); 148 } 149 150 static uint16_t 151 amdpm_smbus_get_gsr(struct amdpm_softc *sc) 152 { 153 int off = (sc->sc_nforce ? 0xe0 : 0); 154 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, 155 AMDPM_8111_SMBUS_STAT - off); 156 } 157 158 static int 159 amdpm_smbus_quick(struct amdpm_softc *sc, i2c_op_t op) 160 { 161 uint16_t data = 0; 162 int off = (sc->sc_nforce ? 0xe0 : 0); 163 164 /* first clear gsr */ 165 amdpm_smbus_clear_gsr(sc); 166 167 /* write smbus slave address and read/write bit to register */ 168 data = sc->sc_smbus_slaveaddr; 169 data <<= 1; 170 if (I2C_OP_READ_P(op)) 171 data |= AMDPM_8111_SMBUS_READ; 172 173 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 174 AMDPM_8111_SMBUS_HOSTADDR - off, data); 175 176 /* host start */ 177 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 178 AMDPM_8111_SMBUS_CTRL - off, 179 AMDPM_8111_SMBUS_GSR_QUICK); 180 181 return amdpm_smbus_check_done(sc, op); 182 } 183 184 static int 185 amdpm_smbus_send_1(struct amdpm_softc *sc, uint8_t val, i2c_op_t op) 186 { 187 uint16_t data = 0; 188 int off = (sc->sc_nforce ? 0xe0 : 0); 189 190 /* first clear gsr */ 191 amdpm_smbus_clear_gsr(sc); 192 193 /* write smbus slave address to register */ 194 data = sc->sc_smbus_slaveaddr; 195 data <<= 1; 196 data |= AMDPM_8111_SMBUS_SEND; 197 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 198 AMDPM_8111_SMBUS_HOSTADDR - off, data); 199 200 data = val; 201 /* store data */ 202 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 203 AMDPM_8111_SMBUS_HOSTDATA - off, data); 204 /* host start */ 205 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 206 AMDPM_8111_SMBUS_CTRL - off, 207 AMDPM_8111_SMBUS_GSR_SB); 208 209 return amdpm_smbus_check_done(sc, op); 210 } 211 212 213 static int 214 amdpm_smbus_write_1(struct amdpm_softc *sc, uint8_t cmd, uint8_t val, 215 i2c_op_t op) 216 { 217 uint16_t data = 0; 218 int off = (sc->sc_nforce ? 0xe0 : 0); 219 220 /* first clear gsr */ 221 amdpm_smbus_clear_gsr(sc); 222 223 data = sc->sc_smbus_slaveaddr; 224 data <<= 1; 225 data |= AMDPM_8111_SMBUS_WRITE; 226 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 227 AMDPM_8111_SMBUS_HOSTADDR - off, data); 228 229 data = val; 230 /* store cmd */ 231 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 232 AMDPM_8111_SMBUS_HOSTCMD - off, cmd); 233 /* store data */ 234 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 235 AMDPM_8111_SMBUS_HOSTDATA - off, data); 236 /* host start */ 237 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 238 AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_WB); 239 240 return amdpm_smbus_check_done(sc, op); 241 } 242 243 static int 244 amdpm_smbus_receive_1(struct amdpm_softc *sc, i2c_op_t op) 245 { 246 uint16_t data = 0; 247 int off = (sc->sc_nforce ? 0xe0 : 0); 248 249 /* first clear gsr */ 250 amdpm_smbus_clear_gsr(sc); 251 252 /* write smbus slave address to register */ 253 data = sc->sc_smbus_slaveaddr; 254 data <<= 1; 255 data |= AMDPM_8111_SMBUS_RX; 256 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 257 AMDPM_8111_SMBUS_HOSTADDR - off, data); 258 259 /* start smbus cycle */ 260 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 261 AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_RXB); 262 263 /* check for errors */ 264 if (amdpm_smbus_check_done(sc, op) < 0) 265 return -1; 266 267 /* read data */ 268 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 269 AMDPM_8111_SMBUS_HOSTDATA - off); 270 uint8_t ret = (uint8_t)(data & 0x00FF); 271 return ret; 272 } 273 274 static int 275 amdpm_smbus_read_1(struct amdpm_softc *sc, uint8_t cmd, i2c_op_t op) 276 { 277 uint16_t data = 0; 278 uint8_t ret; 279 int off = (sc->sc_nforce ? 0xe0 : 0); 280 281 /* first clear gsr */ 282 amdpm_smbus_clear_gsr(sc); 283 284 /* write smbus slave address to register */ 285 data = sc->sc_smbus_slaveaddr; 286 data <<= 1; 287 data |= AMDPM_8111_SMBUS_READ; 288 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 289 AMDPM_8111_SMBUS_HOSTADDR - off, data); 290 291 /* store cmd */ 292 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 293 AMDPM_8111_SMBUS_HOSTCMD - off, cmd); 294 /* host start */ 295 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 296 AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_RB); 297 298 /* check for errors */ 299 if (amdpm_smbus_check_done(sc, op) < 0) 300 return -1; 301 302 /* store data */ 303 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 304 AMDPM_8111_SMBUS_HOSTDATA - off); 305 ret = (uint8_t)(data & 0x00FF); 306 return ret; 307 } 308
Indexes created Wed Oct 01 13:09:50 GMT 2025