amdpm_smbus.c revision 1.3
1 /* $NetBSD: amdpm_smbus.c,v 1.3 2006/04/30 18:46:18 xtraeme Exp $ */ 2 3 /* 4 * Copyright (c) 2005 Anil Gopinath (anil_public (at) yahoo.com) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* driver for SMBUS 1.0 host controller found in the 32 * AMD-8111 HyperTransport I/O Hub 33 */ 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: amdpm_smbus.c,v 1.3 2006/04/30 18:46:18 xtraeme Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 #include <sys/rnd.h> 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 46 #include <dev/i2c/i2cvar.h> 47 #include <dev/i2c/i2c_bitbang.h> 48 49 #include <dev/pci/amdpmreg.h> 50 #include <dev/pci/amdpmvar.h> 51 52 #include <dev/pci/amdpm_smbusreg.h> 53 54 static int amdpm_smbus_acquire_bus(void *cookie, int flags); 55 static void amdpm_smbus_release_bus(void *cookie, int flags); 56 static int amdpm_smbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 57 const void *cmd, size_t cmdlen, void *vbuf, 58 size_t buflen, int flags); 59 static int amdpm_smbus_check_done(struct amdpm_softc *sc); 60 static void amdpm_smbus_clear_gsr(struct amdpm_softc *sc); 61 static u_int16_t amdpm_smbus_get_gsr(struct amdpm_softc *sc); 62 static int amdpm_smbus_send_1(struct amdpm_softc *sc, u_int8_t val); 63 static int amdpm_smbus_write_1(struct amdpm_softc *sc, u_int8_t cmd, u_int8_t data); 64 static int amdpm_smbus_receive_1(struct amdpm_softc *sc); 65 static int amdpm_smbus_read_1(struct amdpm_softc *sc, u_int8_t cmd); 66 67 68 void 69 amdpm_smbus_attach(struct amdpm_softc *sc) 70 { 71 struct i2cbus_attach_args iba; 72 73 // register with iic 74 sc->sc_i2c.ic_cookie = sc; 75 sc->sc_i2c.ic_acquire_bus = amdpm_smbus_acquire_bus; 76 sc->sc_i2c.ic_release_bus = amdpm_smbus_release_bus; 77 sc->sc_i2c.ic_send_start = NULL; 78 sc->sc_i2c.ic_send_stop = NULL; 79 sc->sc_i2c.ic_initiate_xfer = NULL; 80 sc->sc_i2c.ic_read_byte = NULL; 81 sc->sc_i2c.ic_write_byte = NULL; 82 sc->sc_i2c.ic_exec = amdpm_smbus_exec; 83 84 lockinit(&sc->sc_lock, PZERO, "amdpm_smbus", 0, 0); 85 86 iba.iba_name = "iic"; 87 iba.iba_tag = &sc->sc_i2c; 88 (void) config_found(&sc->sc_dev, &iba, iicbus_print); 89 } 90 91 static int 92 amdpm_smbus_acquire_bus(void *cookie, int flags) 93 { 94 struct amdpm_softc *sc = cookie; 95 int err; 96 97 err = lockmgr(&sc->sc_lock, LK_EXCLUSIVE, NULL); 98 99 return err; 100 } 101 102 static void 103 amdpm_smbus_release_bus(void *cookie, int flags) 104 { 105 struct amdpm_softc *sc = cookie; 106 107 lockmgr(&sc->sc_lock, LK_RELEASE, NULL); 108 109 return; 110 } 111 112 static int 113 amdpm_smbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmd, 114 size_t cmdlen, void *vbuf, size_t buflen, int flags) 115 { 116 struct amdpm_softc *sc = (struct amdpm_softc *) cookie; 117 sc->sc_smbus_slaveaddr = addr; 118 119 if (I2C_OP_READ_P(op) && (cmdlen == 0) && (buflen == 1)) { 120 return (amdpm_smbus_receive_1(sc)); 121 } 122 123 if ( (I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 1)) { 124 return (amdpm_smbus_read_1(sc, *(const uint8_t*)cmd)); 125 } 126 127 if ( (I2C_OP_WRITE_P(op)) && (cmdlen == 0) && (buflen == 1)) { 128 return (amdpm_smbus_send_1(sc, *(uint8_t*)vbuf)); 129 } 130 131 if ( (I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 1)) { 132 return (amdpm_smbus_write_1(sc, *(const uint8_t*)cmd, *(uint8_t*)vbuf)); 133 } 134 135 return (-1); 136 } 137 138 static int 139 amdpm_smbus_check_done(struct amdpm_softc *sc) 140 { 141 int i = 0; 142 for (i = 0; i < 1000; i++) { 143 /* check gsr and wait till cycle is done */ 144 u_int16_t data = amdpm_smbus_get_gsr(sc); 145 if (data & AMDPM_8111_GSR_CYCLE_DONE) { 146 return (0); 147 } 148 delay(1); 149 } 150 return (-1); 151 } 152 153 154 static void 155 amdpm_smbus_clear_gsr(struct amdpm_softc *sc) 156 { 157 /* clear register */ 158 u_int16_t data = 0xFFFF; 159 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_STAT, data); 160 } 161 162 static u_int16_t 163 amdpm_smbus_get_gsr(struct amdpm_softc *sc) 164 { 165 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_STAT)); 166 } 167 168 static int 169 amdpm_smbus_send_1(struct amdpm_softc *sc, u_int8_t val) 170 { 171 /* first clear gsr */ 172 amdpm_smbus_clear_gsr(sc); 173 174 /* write smbus slave address to register */ 175 u_int16_t data = 0; 176 data = sc->sc_smbus_slaveaddr; 177 data <<= 1; 178 data |= AMDPM_8111_SMBUS_SEND; 179 bus_space_write_1(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_HOSTADDR, data); 180 181 data = val; 182 /* store data */ 183 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_HOSTDATA, data); 184 /* host start */ 185 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_CTRL, 186 AMDPM_8111_SMBUS_GSR_SB); 187 return(amdpm_smbus_check_done(sc)); 188 } 189 190 191 static int 192 amdpm_smbus_write_1(struct amdpm_softc *sc, u_int8_t cmd, u_int8_t val) 193 { 194 /* first clear gsr */ 195 amdpm_smbus_clear_gsr(sc); 196 197 u_int16_t data = 0; 198 data = sc->sc_smbus_slaveaddr; 199 data <<= 1; 200 data |= AMDPM_8111_SMBUS_WRITE; 201 bus_space_write_1(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_HOSTADDR, data); 202 203 data = val; 204 /* store cmd */ 205 bus_space_write_1(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_HOSTCMD, cmd); 206 /* store data */ 207 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_HOSTDATA, data); 208 /* host start */ 209 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_CTRL, AMDPM_8111_SMBUS_GSR_WB); 210 211 return (amdpm_smbus_check_done(sc)); 212 } 213 214 static int 215 amdpm_smbus_receive_1(struct amdpm_softc *sc) 216 { 217 /* first clear gsr */ 218 amdpm_smbus_clear_gsr(sc); 219 220 /* write smbus slave address to register */ 221 u_int16_t data = 0; 222 data = sc->sc_smbus_slaveaddr; 223 data <<= 1; 224 data |= AMDPM_8111_SMBUS_RX; 225 bus_space_write_1(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_HOSTADDR, data); 226 227 /* start smbus cycle */ 228 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_CTRL, AMDPM_8111_SMBUS_GSR_RXB); 229 230 /* check for errors */ 231 if (amdpm_smbus_check_done(sc) < 0) 232 return (-1); 233 234 /* read data */ 235 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_HOSTDATA); 236 u_int8_t ret = (u_int8_t)(data & 0x00FF); 237 return (ret); 238 } 239 240 static int 241 amdpm_smbus_read_1(struct amdpm_softc *sc, u_int8_t cmd) 242 { 243 /* first clear gsr */ 244 amdpm_smbus_clear_gsr(sc); 245 246 /* write smbus slave address to register */ 247 u_int16_t data = 0; 248 data = sc->sc_smbus_slaveaddr; 249 data <<= 1; 250 data |= AMDPM_8111_SMBUS_READ; 251 bus_space_write_1(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_HOSTADDR, data); 252 253 /* store cmd */ 254 bus_space_write_1(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_HOSTCMD, cmd); 255 /* host start */ 256 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_CTRL, AMDPM_8111_SMBUS_GSR_RB); 257 258 /* check for errors */ 259 if (amdpm_smbus_check_done(sc) < 0) 260 return (-1); 261 262 /* store data */ 263 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, AMDPM_8111_SMBUS_HOSTDATA); 264 u_int8_t ret = (u_int8_t)(data & 0x00FF); 265 return (ret); 266 } 267
Indexes created Wed Oct 01 13:09:50 GMT 2025