amdpm_smbus.c revision 1.8
1 /* $NetBSD: amdpm_smbus.c,v 1.8 2007/01/06 01:20:39 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2005 Anil Gopinath (anil_public (at) yahoo.com) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* driver for SMBUS 1.0 host controller found in the 32 * AMD-8111 HyperTransport I/O Hub 33 */ 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: amdpm_smbus.c,v 1.8 2007/01/06 01:20:39 jmcneill Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 #include <sys/rnd.h> 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 46 #include <dev/i2c/i2cvar.h> 47 #include <dev/i2c/i2c_bitbang.h> 48 49 #include <dev/pci/amdpmreg.h> 50 #include <dev/pci/amdpmvar.h> 51 52 #include <dev/pci/amdpm_smbusreg.h> 53 54 static int amdpm_smbus_acquire_bus(void *cookie, int flags); 55 static void amdpm_smbus_release_bus(void *cookie, int flags); 56 static int amdpm_smbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 57 const void *cmd, size_t cmdlen, void *vbuf, 58 size_t buflen, int flags); 59 static int amdpm_smbus_check_done(struct amdpm_softc *sc); 60 static void amdpm_smbus_clear_gsr(struct amdpm_softc *sc); 61 static u_int16_t amdpm_smbus_get_gsr(struct amdpm_softc *sc); 62 static int amdpm_smbus_send_1(struct amdpm_softc *sc, u_int8_t val); 63 static int amdpm_smbus_write_1(struct amdpm_softc *sc, u_int8_t cmd, u_int8_t data); 64 static int amdpm_smbus_receive_1(struct amdpm_softc *sc); 65 static int amdpm_smbus_read_1(struct amdpm_softc *sc, u_int8_t cmd); 66 67 68 void 69 amdpm_smbus_attach(struct amdpm_softc *sc) 70 { 71 struct i2cbus_attach_args iba; 72 73 /* register with iic */ 74 sc->sc_i2c.ic_cookie = sc; 75 sc->sc_i2c.ic_acquire_bus = amdpm_smbus_acquire_bus; 76 sc->sc_i2c.ic_release_bus = amdpm_smbus_release_bus; 77 sc->sc_i2c.ic_send_start = NULL; 78 sc->sc_i2c.ic_send_stop = NULL; 79 sc->sc_i2c.ic_initiate_xfer = NULL; 80 sc->sc_i2c.ic_read_byte = NULL; 81 sc->sc_i2c.ic_write_byte = NULL; 82 sc->sc_i2c.ic_exec = amdpm_smbus_exec; 83 84 lockinit(&sc->sc_lock, PZERO, "amdpm_smbus", 0, 0); 85 86 iba.iba_tag = &sc->sc_i2c; 87 (void) config_found_ia(&sc->sc_dev, "i2cbus", &iba, iicbus_print); 88 } 89 90 static int 91 amdpm_smbus_acquire_bus(void *cookie, int flags) 92 { 93 struct amdpm_softc *sc = cookie; 94 int err; 95 96 err = lockmgr(&sc->sc_lock, LK_EXCLUSIVE, NULL); 97 98 return err; 99 } 100 101 static void 102 amdpm_smbus_release_bus(void *cookie, int flags) 103 { 104 struct amdpm_softc *sc = cookie; 105 106 lockmgr(&sc->sc_lock, LK_RELEASE, NULL); 107 108 return; 109 } 110 111 static int 112 amdpm_smbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmd, 113 size_t cmdlen, void *vbuf, size_t buflen, int flags) 114 { 115 struct amdpm_softc *sc = (struct amdpm_softc *) cookie; 116 sc->sc_smbus_slaveaddr = addr; 117 118 if (I2C_OP_READ_P(op) && (cmdlen == 0) && (buflen == 1)) { 119 return (amdpm_smbus_receive_1(sc)); 120 } 121 122 if ( (I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 1)) { 123 return (amdpm_smbus_read_1(sc, *(const uint8_t*)cmd)); 124 } 125 126 if ( (I2C_OP_WRITE_P(op)) && (cmdlen == 0) && (buflen == 1)) { 127 return (amdpm_smbus_send_1(sc, *(uint8_t*)vbuf)); 128 } 129 130 if ( (I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 1)) { 131 return (amdpm_smbus_write_1(sc, *(const uint8_t*)cmd, *(uint8_t*)vbuf)); 132 } 133 134 return (-1); 135 } 136 137 static int 138 amdpm_smbus_check_done(struct amdpm_softc *sc) 139 { 140 int i = 0; 141 for (i = 0; i < 1000; i++) { 142 /* check gsr and wait till cycle is done */ 143 u_int16_t data = amdpm_smbus_get_gsr(sc); 144 if (data & AMDPM_8111_GSR_CYCLE_DONE) { 145 return (0); 146 } 147 delay(1); 148 } 149 return (-1); 150 } 151 152 153 static void 154 amdpm_smbus_clear_gsr(struct amdpm_softc *sc) 155 { 156 /* clear register */ 157 u_int16_t data = 0xFFFF; 158 int off = (sc->sc_nforce ? 0xe0 : 0); 159 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 160 AMDPM_8111_SMBUS_STAT - off, data); 161 } 162 163 static u_int16_t 164 amdpm_smbus_get_gsr(struct amdpm_softc *sc) 165 { 166 int off = (sc->sc_nforce ? 0xe0 : 0); 167 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, 168 AMDPM_8111_SMBUS_STAT - off)); 169 } 170 171 static int 172 amdpm_smbus_send_1(struct amdpm_softc *sc, u_int8_t val) 173 { 174 u_int16_t data = 0; 175 int off = (sc->sc_nforce ? 0xe0 : 0); 176 177 /* first clear gsr */ 178 amdpm_smbus_clear_gsr(sc); 179 180 /* write smbus slave address to register */ 181 data = sc->sc_smbus_slaveaddr; 182 data <<= 1; 183 data |= AMDPM_8111_SMBUS_SEND; 184 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 185 AMDPM_8111_SMBUS_HOSTADDR - off, data); 186 187 data = val; 188 /* store data */ 189 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 190 AMDPM_8111_SMBUS_HOSTDATA - off, data); 191 /* host start */ 192 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 193 AMDPM_8111_SMBUS_CTRL - off, 194 AMDPM_8111_SMBUS_GSR_SB); 195 196 return(amdpm_smbus_check_done(sc)); 197 } 198 199 200 static int 201 amdpm_smbus_write_1(struct amdpm_softc *sc, u_int8_t cmd, u_int8_t val) 202 { 203 u_int16_t data = 0; 204 int off = (sc->sc_nforce ? 0xe0 : 0); 205 206 /* first clear gsr */ 207 amdpm_smbus_clear_gsr(sc); 208 209 data = sc->sc_smbus_slaveaddr; 210 data <<= 1; 211 data |= AMDPM_8111_SMBUS_WRITE; 212 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 213 AMDPM_8111_SMBUS_HOSTADDR - off, data); 214 215 data = val; 216 /* store cmd */ 217 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 218 AMDPM_8111_SMBUS_HOSTCMD - off, cmd); 219 /* store data */ 220 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 221 AMDPM_8111_SMBUS_HOSTDATA - off, data); 222 /* host start */ 223 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 224 AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_WB); 225 226 return (amdpm_smbus_check_done(sc)); 227 } 228 229 static int 230 amdpm_smbus_receive_1(struct amdpm_softc *sc) 231 { 232 u_int16_t data = 0; 233 int off = (sc->sc_nforce ? 0xe0 : 0); 234 235 /* first clear gsr */ 236 amdpm_smbus_clear_gsr(sc); 237 238 /* write smbus slave address to register */ 239 data = sc->sc_smbus_slaveaddr; 240 data <<= 1; 241 data |= AMDPM_8111_SMBUS_RX; 242 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 243 AMDPM_8111_SMBUS_HOSTADDR - off, data); 244 245 /* start smbus cycle */ 246 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 247 AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_RXB); 248 249 /* check for errors */ 250 if (amdpm_smbus_check_done(sc) < 0) 251 return (-1); 252 253 /* read data */ 254 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 255 AMDPM_8111_SMBUS_HOSTDATA - off); 256 u_int8_t ret = (u_int8_t)(data & 0x00FF); 257 return (ret); 258 } 259 260 static int 261 amdpm_smbus_read_1(struct amdpm_softc *sc, u_int8_t cmd) 262 { 263 u_int16_t data = 0; 264 int off = (sc->sc_nforce ? 0xe0 : 0); 265 266 /* first clear gsr */ 267 amdpm_smbus_clear_gsr(sc); 268 269 /* write smbus slave address to register */ 270 data = sc->sc_smbus_slaveaddr; 271 data <<= 1; 272 data |= AMDPM_8111_SMBUS_READ; 273 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 274 AMDPM_8111_SMBUS_HOSTADDR - off, data); 275 276 /* store cmd */ 277 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 278 AMDPM_8111_SMBUS_HOSTCMD - off, cmd); 279 /* host start */ 280 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 281 AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_RB); 282 283 /* check for errors */ 284 if (amdpm_smbus_check_done(sc) < 0) 285 return (-1); 286 287 /* store data */ 288 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 289 AMDPM_8111_SMBUS_HOSTDATA - off); 290 u_int8_t ret = (u_int8_t)(data & 0x00FF); 291 return (ret); 292 } 293
Indexes created Wed Oct 01 13:09:50 GMT 2025