amdpm_smbus.c revision 1.9
1 /* $NetBSD: amdpm_smbus.c,v 1.9 2007/01/06 02:16:22 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2005 Anil Gopinath (anil_public (at) yahoo.com) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* driver for SMBUS 1.0 host controller found in the 32 * AMD-8111 HyperTransport I/O Hub 33 */ 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: amdpm_smbus.c,v 1.9 2007/01/06 02:16:22 jmcneill Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 #include <sys/rnd.h> 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 46 #include <dev/i2c/i2cvar.h> 47 #include <dev/i2c/i2c_bitbang.h> 48 49 #include <dev/pci/amdpmreg.h> 50 #include <dev/pci/amdpmvar.h> 51 52 #include <dev/pci/amdpm_smbusreg.h> 53 54 static int amdpm_smbus_acquire_bus(void *cookie, int flags); 55 static void amdpm_smbus_release_bus(void *cookie, int flags); 56 static int amdpm_smbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 57 const void *cmd, size_t cmdlen, void *vbuf, 58 size_t buflen, int flags); 59 static int amdpm_smbus_check_done(struct amdpm_softc *sc); 60 static void amdpm_smbus_clear_gsr(struct amdpm_softc *sc); 61 static u_int16_t amdpm_smbus_get_gsr(struct amdpm_softc *sc); 62 static int amdpm_smbus_send_1(struct amdpm_softc *sc, u_int8_t val); 63 static int amdpm_smbus_write_1(struct amdpm_softc *sc, u_int8_t cmd, u_int8_t data); 64 static int amdpm_smbus_receive_1(struct amdpm_softc *sc); 65 static int amdpm_smbus_read_1(struct amdpm_softc *sc, u_int8_t cmd); 66 67 68 void 69 amdpm_smbus_attach(struct amdpm_softc *sc) 70 { 71 struct i2cbus_attach_args iba; 72 73 /* register with iic */ 74 sc->sc_i2c.ic_cookie = sc; 75 sc->sc_i2c.ic_acquire_bus = amdpm_smbus_acquire_bus; 76 sc->sc_i2c.ic_release_bus = amdpm_smbus_release_bus; 77 sc->sc_i2c.ic_send_start = NULL; 78 sc->sc_i2c.ic_send_stop = NULL; 79 sc->sc_i2c.ic_initiate_xfer = NULL; 80 sc->sc_i2c.ic_read_byte = NULL; 81 sc->sc_i2c.ic_write_byte = NULL; 82 sc->sc_i2c.ic_exec = amdpm_smbus_exec; 83 84 lockinit(&sc->sc_lock, PZERO, "amdpm_smbus", 0, 0); 85 86 iba.iba_tag = &sc->sc_i2c; 87 (void) config_found_ia(&sc->sc_dev, "i2cbus", &iba, iicbus_print); 88 } 89 90 static int 91 amdpm_smbus_acquire_bus(void *cookie, int flags) 92 { 93 struct amdpm_softc *sc = cookie; 94 int err; 95 96 err = lockmgr(&sc->sc_lock, LK_EXCLUSIVE, NULL); 97 98 return err; 99 } 100 101 static void 102 amdpm_smbus_release_bus(void *cookie, int flags) 103 { 104 struct amdpm_softc *sc = cookie; 105 106 lockmgr(&sc->sc_lock, LK_RELEASE, NULL); 107 108 return; 109 } 110 111 static int 112 amdpm_smbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmd, 113 size_t cmdlen, void *vbuf, size_t buflen, int flags) 114 { 115 struct amdpm_softc *sc = (struct amdpm_softc *) cookie; 116 sc->sc_smbus_slaveaddr = addr; 117 u_int8_t *p = vbuf; 118 int rv; 119 120 if (I2C_OP_READ_P(op) && (cmdlen == 0) && (buflen == 1)) { 121 rv = amdpm_smbus_receive_1(sc); 122 if (rv == -1) 123 return -1; 124 *p = (u_int8_t)rv; 125 return 0; 126 } 127 128 if ( (I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 1)) { 129 rv = amdpm_smbus_read_1(sc, *(const uint8_t*)cmd); 130 if (rv == -1) 131 return -1; 132 *p = (u_int8_t)rv; 133 return 0; 134 } 135 136 if ( (I2C_OP_WRITE_P(op)) && (cmdlen == 0) && (buflen == 1)) { 137 return amdpm_smbus_send_1(sc, *(uint8_t*)vbuf); 138 } 139 140 if ( (I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 1)) { 141 return amdpm_smbus_write_1(sc, *(const uint8_t*)cmd, *(uint8_t*)vbuf); 142 } 143 144 return (-1); 145 } 146 147 static int 148 amdpm_smbus_check_done(struct amdpm_softc *sc) 149 { 150 int i = 0; 151 for (i = 0; i < 1000; i++) { 152 /* check gsr and wait till cycle is done */ 153 u_int16_t data = amdpm_smbus_get_gsr(sc); 154 if (data & AMDPM_8111_GSR_CYCLE_DONE) { 155 return (0); 156 } 157 delay(1); 158 } 159 return (-1); 160 } 161 162 163 static void 164 amdpm_smbus_clear_gsr(struct amdpm_softc *sc) 165 { 166 /* clear register */ 167 u_int16_t data = 0xFFFF; 168 int off = (sc->sc_nforce ? 0xe0 : 0); 169 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 170 AMDPM_8111_SMBUS_STAT - off, data); 171 } 172 173 static u_int16_t 174 amdpm_smbus_get_gsr(struct amdpm_softc *sc) 175 { 176 int off = (sc->sc_nforce ? 0xe0 : 0); 177 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, 178 AMDPM_8111_SMBUS_STAT - off)); 179 } 180 181 static int 182 amdpm_smbus_send_1(struct amdpm_softc *sc, u_int8_t val) 183 { 184 u_int16_t data = 0; 185 int off = (sc->sc_nforce ? 0xe0 : 0); 186 187 /* first clear gsr */ 188 amdpm_smbus_clear_gsr(sc); 189 190 /* write smbus slave address to register */ 191 data = sc->sc_smbus_slaveaddr; 192 data <<= 1; 193 data |= AMDPM_8111_SMBUS_SEND; 194 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 195 AMDPM_8111_SMBUS_HOSTADDR - off, data); 196 197 data = val; 198 /* store data */ 199 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 200 AMDPM_8111_SMBUS_HOSTDATA - off, data); 201 /* host start */ 202 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 203 AMDPM_8111_SMBUS_CTRL - off, 204 AMDPM_8111_SMBUS_GSR_SB); 205 206 return(amdpm_smbus_check_done(sc)); 207 } 208 209 210 static int 211 amdpm_smbus_write_1(struct amdpm_softc *sc, u_int8_t cmd, u_int8_t val) 212 { 213 u_int16_t data = 0; 214 int off = (sc->sc_nforce ? 0xe0 : 0); 215 216 /* first clear gsr */ 217 amdpm_smbus_clear_gsr(sc); 218 219 data = sc->sc_smbus_slaveaddr; 220 data <<= 1; 221 data |= AMDPM_8111_SMBUS_WRITE; 222 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 223 AMDPM_8111_SMBUS_HOSTADDR - off, data); 224 225 data = val; 226 /* store cmd */ 227 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 228 AMDPM_8111_SMBUS_HOSTCMD - off, cmd); 229 /* store data */ 230 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 231 AMDPM_8111_SMBUS_HOSTDATA - off, data); 232 /* host start */ 233 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 234 AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_WB); 235 236 return (amdpm_smbus_check_done(sc)); 237 } 238 239 static int 240 amdpm_smbus_receive_1(struct amdpm_softc *sc) 241 { 242 u_int16_t data = 0; 243 int off = (sc->sc_nforce ? 0xe0 : 0); 244 245 /* first clear gsr */ 246 amdpm_smbus_clear_gsr(sc); 247 248 /* write smbus slave address to register */ 249 data = sc->sc_smbus_slaveaddr; 250 data <<= 1; 251 data |= AMDPM_8111_SMBUS_RX; 252 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 253 AMDPM_8111_SMBUS_HOSTADDR - off, data); 254 255 /* start smbus cycle */ 256 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 257 AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_RXB); 258 259 /* check for errors */ 260 if (amdpm_smbus_check_done(sc) < 0) 261 return (-1); 262 263 /* read data */ 264 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 265 AMDPM_8111_SMBUS_HOSTDATA - off); 266 u_int8_t ret = (u_int8_t)(data & 0x00FF); 267 return (ret); 268 } 269 270 static int 271 amdpm_smbus_read_1(struct amdpm_softc *sc, u_int8_t cmd) 272 { 273 u_int16_t data = 0; 274 u_int8_t ret; 275 int off = (sc->sc_nforce ? 0xe0 : 0); 276 277 /* first clear gsr */ 278 amdpm_smbus_clear_gsr(sc); 279 280 /* write smbus slave address to register */ 281 data = sc->sc_smbus_slaveaddr; 282 data <<= 1; 283 data |= AMDPM_8111_SMBUS_READ; 284 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 285 AMDPM_8111_SMBUS_HOSTADDR - off, data); 286 287 /* store cmd */ 288 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 289 AMDPM_8111_SMBUS_HOSTCMD - off, cmd); 290 /* host start */ 291 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 292 AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_RB); 293 294 /* check for errors */ 295 if (amdpm_smbus_check_done(sc) < 0) 296 return (-1); 297 298 /* store data */ 299 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 300 AMDPM_8111_SMBUS_HOSTDATA - off); 301 ret = (u_int8_t)(data & 0x00FF); 302 return (ret); 303 } 304
Indexes created Wed Oct 01 13:09:50 GMT 2025