1 1.3 andvar /* $NetBSD: amdpm_smbusreg.h,v 1.3 2021/09/16 21:29:41 andvar Exp $ */ 2 1.1 tls 3 1.1 tls /* 4 1.1 tls * Copyright (c) 2005 Anil Gopinath (anil_public (at) yahoo.com) 5 1.1 tls * All rights reserved. 6 1.1 tls * 7 1.1 tls * Redistribution and use in source and binary forms, with or without 8 1.1 tls * modification, are permitted provided that the following conditions 9 1.1 tls * are met: 10 1.1 tls * 1. Redistributions of source code must retain the above copyright 11 1.1 tls * notice, this list of conditions and the following disclaimer. 12 1.1 tls * 2. Redistributions in binary form must reproduce the above copyright 13 1.1 tls * notice, this list of conditions and the following disclaimer in the 14 1.1 tls * documentation and/or other materials provided with the distribution. 15 1.1 tls * 3. The name of the author may not be used to endorse or promote products 16 1.1 tls * derived from this software without specific prior written permission. 17 1.1 tls * 18 1.1 tls * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 1.1 tls * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 1.1 tls * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 1.1 tls * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 1.1 tls * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 1.1 tls * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 1.1 tls * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 1.1 tls * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 1.1 tls * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 1.1 tls * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 1.1 tls * SUCH DAMAGE. 29 1.1 tls */ 30 1.1 tls 31 1.1 tls /* driver for SMBUS 1.0 host controller found in the 32 1.1 tls * AMD-8111 HyperTransport I/O Hub 33 1.1 tls */ 34 1.1 tls 35 1.1 tls #ifndef _DEV_PCI_AMDPMSMBUSREG_H_ 36 1.1 tls #define _DEV_PCI_AMDPMSMBUSREG_H_ 37 1.1 tls 38 1.1 tls #define AMDPM_8111_SMBUS_STAT 0xE0 /* SMBus 1.x global status register */ 39 1.1 tls #define AMDPM_8111_SMBUS_CTRL 0xE2 /* SMBus 1.x global control register */ 40 1.1 tls #define AMDPM_8111_SMBUS_HOSTADDR 0xE4 /* SMBus 1.x Host address register */ 41 1.1 tls #define AMDPM_8111_SMBUS_HOSTDATA 0xE6 /* SMBus 1.x Host data register */ 42 1.1 tls #define AMDPM_8111_SMBUS_HOSTCMD 0xE8 /* SMBus 1.x Host command field register */ 43 1.1 tls 44 1.2 pgoyette #define AMDPM_8111_SMBUS_GSR_QUICK 0x0008 /* GSR contents for quick op */ 45 1.1 tls #define AMDPM_8111_SMBUS_GSR_SB 0x0009 /* GSR contents to send a byte */ 46 1.1 tls #define AMDPM_8111_SMBUS_GSR_RXB 0x0009 /* GSR contents to receive a byte */ 47 1.1 tls #define AMDPM_8111_SMBUS_GSR_RB 0x000A /* GSR contents to read a byte */ 48 1.1 tls #define AMDPM_8111_SMBUS_GSR_WB 0x000A /* GSR contents to write a byte */ 49 1.1 tls 50 1.3 andvar #define AMDPM_8111_GSR_CYCLE_DONE 0x0010 /* indicates cycle done successfully */ 51 1.1 tls 52 1.1 tls #define AMDPM_8111_SMBUS_READ 0x0001 /* smbus read cycle indicator */ 53 1.1 tls #define AMDPM_8111_SMBUS_RX 0x0001 /* smbus receive cycle indicator */ 54 1.1 tls #define AMDPM_8111_SMBUS_WRITE 0x0000 /* smbus write cycle indicator */ 55 1.1 tls #define AMDPM_8111_SMBUS_SEND 0x0000 /* smbus send cycle indicator */ 56 1.1 tls 57 1.1 tls void amdpm_smbus_attach(struct amdpm_softc *sc); 58 1.1 tls 59 1.1 tls #endif 60
Indexes created Wed Oct 01 13:09:50 GMT 2025