amr.c revision 1.12
1 /* $NetBSD: amr.c,v 1.12 2003/09/26 16:31:08 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999,2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: amr_pci.c,v 1.5 2000/08/30 07:52:40 msmith Exp 66 * from FreeBSD: amr.c,v 1.16 2000/08/30 07:52:40 msmith Exp 67 */ 68 69 /* 70 * Driver for AMI RAID controllers. 71 */ 72 73 #include <sys/cdefs.h> 74 __KERNEL_RCSID(0, "$NetBSD: amr.c,v 1.12 2003/09/26 16:31:08 matt Exp $"); 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/device.h> 80 #include <sys/queue.h> 81 #include <sys/proc.h> 82 #include <sys/buf.h> 83 #include <sys/malloc.h> 84 #include <sys/kthread.h> 85 86 #include <uvm/uvm_extern.h> 87 88 #include <machine/endian.h> 89 #include <machine/bus.h> 90 91 #include <dev/pci/pcidevs.h> 92 #include <dev/pci/pcivar.h> 93 #include <dev/pci/amrreg.h> 94 #include <dev/pci/amrvar.h> 95 96 void amr_attach(struct device *, struct device *, void *); 97 void amr_ccb_dump(struct amr_softc *, struct amr_ccb *); 98 void *amr_enquire(struct amr_softc *, u_int8_t, u_int8_t, u_int8_t, void *); 99 int amr_init(struct amr_softc *, const char *, 100 struct pci_attach_args *pa); 101 int amr_intr(void *); 102 int amr_match(struct device *, struct cfdata *, void *); 103 int amr_print(void *, const char *); 104 void amr_shutdown(void *); 105 int amr_submatch(struct device *, struct cfdata *, void *); 106 void amr_teardown(struct amr_softc *); 107 void amr_thread(void *); 108 void amr_thread_create(void *); 109 110 int amr_mbox_wait(struct amr_softc *); 111 int amr_quartz_get_work(struct amr_softc *, struct amr_mailbox_resp *); 112 int amr_quartz_submit(struct amr_softc *, struct amr_ccb *); 113 int amr_std_get_work(struct amr_softc *, struct amr_mailbox_resp *); 114 int amr_std_submit(struct amr_softc *, struct amr_ccb *); 115 116 static inline u_int8_t amr_inb(struct amr_softc *, int); 117 static inline u_int32_t amr_inl(struct amr_softc *, int); 118 static inline void amr_outb(struct amr_softc *, int, u_int8_t); 119 static inline void amr_outl(struct amr_softc *, int, u_int32_t); 120 121 CFATTACH_DECL(amr, sizeof(struct amr_softc), 122 amr_match, amr_attach, NULL, NULL); 123 124 #define AT_QUARTZ 0x01 /* `Quartz' chipset */ 125 #define AT_SIG 0x02 /* Check for signature */ 126 127 struct amr_pci_type { 128 u_short apt_vendor; 129 u_short apt_product; 130 u_short apt_flags; 131 } const amr_pci_type[] = { 132 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID, 0 }, 133 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID2, 0 }, 134 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ | AT_SIG }, 136 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI, AT_QUARTZ }, 137 }; 138 139 struct amr_typestr { 140 const char *at_str; 141 int at_sig; 142 } const amr_typestr[] = { 143 { "Series 431", AMR_SIG_431 }, 144 { "Series 438", AMR_SIG_438 }, 145 { "Series 466", AMR_SIG_466 }, 146 { "Series 467", AMR_SIG_467 }, 147 { "Series 490", AMR_SIG_490 }, 148 { "Series 762", AMR_SIG_762 }, 149 { "HP NetRAID (T5)", AMR_SIG_T5 }, 150 { "HP NetRAID (T7)", AMR_SIG_T7 }, 151 }; 152 153 struct { 154 const char *ds_descr; 155 int ds_happy; 156 } const amr_dstate[] = { 157 { "offline", 0 }, 158 { "degraded", 1 }, 159 { "optimal", 1 }, 160 { "online", 1 }, 161 { "failed", 0 }, 162 { "rebuilding", 1 }, 163 { "hotspare", 0 }, 164 }; 165 166 void *amr_sdh; 167 int amr_max_segs; 168 int amr_max_xfer; 169 170 static inline u_int8_t 171 amr_inb(struct amr_softc *amr, int off) 172 { 173 174 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 175 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 176 return (bus_space_read_1(amr->amr_iot, amr->amr_ioh, off)); 177 } 178 179 static inline u_int32_t 180 amr_inl(struct amr_softc *amr, int off) 181 { 182 183 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 184 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 185 return (bus_space_read_4(amr->amr_iot, amr->amr_ioh, off)); 186 } 187 188 static inline void 189 amr_outb(struct amr_softc *amr, int off, u_int8_t val) 190 { 191 192 bus_space_write_1(amr->amr_iot, amr->amr_ioh, off, val); 193 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 194 BUS_SPACE_BARRIER_WRITE); 195 } 196 197 static inline void 198 amr_outl(struct amr_softc *amr, int off, u_int32_t val) 199 { 200 201 bus_space_write_4(amr->amr_iot, amr->amr_ioh, off, val); 202 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 203 BUS_SPACE_BARRIER_WRITE); 204 } 205 206 /* 207 * Match a supported device. 208 */ 209 int 210 amr_match(struct device *parent, struct cfdata *match, void *aux) 211 { 212 struct pci_attach_args *pa; 213 pcireg_t s; 214 int i; 215 216 pa = (struct pci_attach_args *)aux; 217 218 /* 219 * Don't match the device if it's operating in I2O mode. In this 220 * case it should be handled by the `iop' driver. 221 */ 222 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 223 return (0); 224 225 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 226 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 227 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 228 break; 229 230 if (i == sizeof(amr_pci_type) / sizeof(amr_pci_type[0])) 231 return (0); 232 233 if ((amr_pci_type[i].apt_flags & AT_SIG) == 0) 234 return (1); 235 236 s = pci_conf_read(pa->pa_pc, pa->pa_tag, AMR_QUARTZ_SIG_REG) & 0xffff; 237 return (s == AMR_QUARTZ_SIG0 || s == AMR_QUARTZ_SIG1); 238 } 239 240 /* 241 * Attach a supported device. 242 */ 243 void 244 amr_attach(struct device *parent, struct device *self, void *aux) 245 { 246 bus_space_tag_t memt, iot; 247 bus_space_handle_t memh, ioh; 248 struct pci_attach_args *pa; 249 struct amr_attach_args amra; 250 const struct amr_pci_type *apt; 251 struct amr_softc *amr; 252 pci_chipset_tag_t pc; 253 pci_intr_handle_t ih; 254 const char *intrstr; 255 pcireg_t reg; 256 int rseg, i, j, size, rv, memreg, ioreg; 257 bus_size_t memsize, iosize; 258 struct amr_ccb *ac; 259 260 aprint_naive(": RAID controller\n"); 261 262 amr = (struct amr_softc *)self; 263 pa = (struct pci_attach_args *)aux; 264 pc = pa->pa_pc; 265 266 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 267 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 268 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 269 break; 270 apt = amr_pci_type + i; 271 272 memreg = ioreg = 0; 273 for (i = 0x10; i <= 0x14; i += 4) { 274 reg = pci_conf_read(pc, pa->pa_tag, i); 275 switch (PCI_MAPREG_TYPE(reg)) { 276 case PCI_MAPREG_TYPE_MEM: 277 if ((memsize = PCI_MAPREG_MEM_SIZE(reg)) != 0) 278 memreg = i; 279 break; 280 case PCI_MAPREG_TYPE_IO: 281 if ((iosize = PCI_MAPREG_IO_SIZE(reg)) != 0) 282 ioreg = i; 283 break; 284 } 285 } 286 287 if (memreg != 0) 288 if (pci_mapreg_map(pa, memreg, PCI_MAPREG_TYPE_MEM, 0, 289 &memt, &memh, NULL, NULL)) 290 memreg = 0; 291 if (ioreg != 0) 292 if (pci_mapreg_map(pa, ioreg, PCI_MAPREG_TYPE_IO, 0, 293 &iot, &ioh, NULL, NULL)) 294 ioreg = 0; 295 296 if (memreg) { 297 amr->amr_iot = memt; 298 amr->amr_ioh = memh; 299 amr->amr_ios = memsize; 300 } else if (ioreg) { 301 amr->amr_iot = iot; 302 amr->amr_ioh = ioh; 303 amr->amr_ios = iosize; 304 } else { 305 aprint_error("can't map control registers\n"); 306 amr_teardown(amr); 307 return; 308 } 309 310 amr->amr_flags |= AMRF_PCI_REGS; 311 amr->amr_dmat = pa->pa_dmat; 312 amr->amr_pc = pa->pa_pc; 313 314 /* Enable the device. */ 315 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 316 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 317 reg | PCI_COMMAND_MASTER_ENABLE); 318 319 /* Map and establish the interrupt. */ 320 if (pci_intr_map(pa, &ih)) { 321 aprint_error("can't map interrupt\n"); 322 amr_teardown(amr); 323 return; 324 } 325 intrstr = pci_intr_string(pc, ih); 326 amr->amr_ih = pci_intr_establish(pc, ih, IPL_BIO, amr_intr, amr); 327 if (amr->amr_ih == NULL) { 328 aprint_error("can't establish interrupt"); 329 if (intrstr != NULL) 330 aprint_normal(" at %s", intrstr); 331 aprint_normal("\n"); 332 amr_teardown(amr); 333 return; 334 } 335 amr->amr_flags |= AMRF_PCI_INTR; 336 337 /* 338 * Allocate space for the mailbox and S/G lists. Some controllers 339 * don't like S/G lists to be located below 0x2000, so we allocate 340 * enough slop to enable us to compensate. 341 * 342 * The standard mailbox structure needs to be aligned on a 16-byte 343 * boundary. The 64-bit mailbox has one extra field, 4 bytes in 344 * size, which preceeds the standard mailbox. 345 */ 346 size = AMR_SGL_SIZE * AMR_MAX_CMDS + 0x2000; 347 amr->amr_dmasize = size; 348 349 if ((rv = bus_dmamem_alloc(amr->amr_dmat, size, PAGE_SIZE, NULL, 350 &amr->amr_dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 351 aprint_error("%s: unable to allocate buffer, rv = %d\n", 352 amr->amr_dv.dv_xname, rv); 353 amr_teardown(amr); 354 return; 355 } 356 amr->amr_flags |= AMRF_DMA_ALLOC; 357 358 if ((rv = bus_dmamem_map(amr->amr_dmat, &amr->amr_dmaseg, rseg, size, 359 (caddr_t *)&amr->amr_mbox, 360 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 361 aprint_error("%s: unable to map buffer, rv = %d\n", 362 amr->amr_dv.dv_xname, rv); 363 amr_teardown(amr); 364 return; 365 } 366 amr->amr_flags |= AMRF_DMA_MAP; 367 368 if ((rv = bus_dmamap_create(amr->amr_dmat, size, 1, size, 0, 369 BUS_DMA_NOWAIT, &amr->amr_dmamap)) != 0) { 370 aprint_error("%s: unable to create buffer DMA map, rv = %d\n", 371 amr->amr_dv.dv_xname, rv); 372 amr_teardown(amr); 373 return; 374 } 375 amr->amr_flags |= AMRF_DMA_CREATE; 376 377 if ((rv = bus_dmamap_load(amr->amr_dmat, amr->amr_dmamap, 378 amr->amr_mbox, size, NULL, BUS_DMA_NOWAIT)) != 0) { 379 aprint_error("%s: unable to load buffer DMA map, rv = %d\n", 380 amr->amr_dv.dv_xname, rv); 381 amr_teardown(amr); 382 return; 383 } 384 amr->amr_flags |= AMRF_DMA_LOAD; 385 386 memset(amr->amr_mbox, 0, size); 387 388 amr->amr_mbox_paddr = amr->amr_dmamap->dm_segs[0].ds_addr; 389 amr->amr_sgls_paddr = (amr->amr_mbox_paddr + 0x1fff) & ~0x1fff; 390 amr->amr_sgls = (struct amr_sgentry *)((caddr_t)amr->amr_mbox + 391 amr->amr_sgls_paddr - amr->amr_dmamap->dm_segs[0].ds_addr); 392 393 /* 394 * Allocate and initalise the command control blocks. 395 */ 396 ac = malloc(sizeof(*ac) * AMR_MAX_CMDS, M_DEVBUF, M_NOWAIT | M_ZERO); 397 amr->amr_ccbs = ac; 398 SLIST_INIT(&amr->amr_ccb_freelist); 399 TAILQ_INIT(&amr->amr_ccb_active); 400 amr->amr_flags |= AMRF_CCBS; 401 402 if (amr_max_xfer == 0) { 403 amr_max_xfer = min(((AMR_MAX_SEGS - 1) * PAGE_SIZE), MAXPHYS); 404 amr_max_segs = (amr_max_xfer + (PAGE_SIZE * 2) - 1) / PAGE_SIZE; 405 } 406 407 for (i = 0; i < AMR_MAX_CMDS; i++, ac++) { 408 rv = bus_dmamap_create(amr->amr_dmat, amr_max_xfer, 409 amr_max_segs, amr_max_xfer, 0, 410 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ac->ac_xfer_map); 411 if (rv != 0) 412 break; 413 414 ac->ac_ident = i; 415 amr_ccb_free(amr, ac); 416 } 417 if (i != AMR_MAX_CMDS) { 418 aprint_error("%s: memory exhausted\n", amr->amr_dv.dv_xname); 419 amr_teardown(amr); 420 return; 421 } 422 423 /* 424 * Take care of model-specific tasks. 425 */ 426 if ((apt->apt_flags & AT_QUARTZ) != 0) { 427 amr->amr_submit = amr_quartz_submit; 428 amr->amr_get_work = amr_quartz_get_work; 429 } else { 430 amr->amr_submit = amr_std_submit; 431 amr->amr_get_work = amr_std_get_work; 432 433 /* Notify the controller of the mailbox location. */ 434 amr_outl(amr, AMR_SREG_MBOX, (u_int32_t)amr->amr_mbox_paddr + 16); 435 amr_outb(amr, AMR_SREG_MBOX_ENABLE, AMR_SMBOX_ENABLE_ADDR); 436 437 /* Clear outstanding interrupts and enable interrupts. */ 438 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 439 amr_outb(amr, AMR_SREG_TOGL, 440 amr_inb(amr, AMR_SREG_TOGL) | AMR_STOGL_ENABLE); 441 } 442 443 /* 444 * Retrieve parameters, and tell the world about us. 445 */ 446 amr->amr_enqbuf = malloc(AMR_ENQUIRY_BUFSIZE, M_DEVBUF, M_NOWAIT); 447 amr->amr_flags |= AMRF_ENQBUF; 448 amr->amr_maxqueuecnt = i; 449 aprint_normal(": AMI RAID "); 450 if (amr_init(amr, intrstr, pa) != 0) { 451 amr_teardown(amr); 452 return; 453 } 454 455 /* 456 * Cap the maximum number of outstanding commands. AMI's Linux 457 * driver doesn't trust the controller's reported value, and lockups 458 * have been seen when we do. 459 */ 460 amr->amr_maxqueuecnt = min(amr->amr_maxqueuecnt, AMR_MAX_CMDS); 461 if (amr->amr_maxqueuecnt > i) 462 amr->amr_maxqueuecnt = i; 463 464 /* Set our `shutdownhook' before we start any device activity. */ 465 if (amr_sdh == NULL) 466 amr_sdh = shutdownhook_establish(amr_shutdown, NULL); 467 468 /* Attach sub-devices. */ 469 for (j = 0; j < amr->amr_numdrives; j++) { 470 if (amr->amr_drive[j].al_size == 0) 471 continue; 472 amra.amra_unit = j; 473 amr->amr_drive[j].al_dv = config_found_sm(&amr->amr_dv, &amra, 474 amr_print, amr_submatch); 475 } 476 477 SIMPLEQ_INIT(&amr->amr_ccb_queue); 478 kthread_create(amr_thread_create, amr); 479 } 480 481 /* 482 * Free up resources. 483 */ 484 void 485 amr_teardown(struct amr_softc *amr) 486 { 487 struct amr_ccb *ac; 488 int fl; 489 490 fl = amr->amr_flags; 491 492 if ((fl & AMRF_THREAD) != 0) { 493 amr->amr_flags |= AMRF_THREAD_EXIT; 494 wakeup(amr_thread); 495 while ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) 496 tsleep(&amr->amr_flags, PWAIT, "amrexit", 0); 497 } 498 if ((fl & AMRF_CCBS) != 0) { 499 SLIST_FOREACH(ac, &amr->amr_ccb_freelist, ac_chain.slist) { 500 bus_dmamap_destroy(amr->amr_dmat, ac->ac_xfer_map); 501 } 502 free(amr->amr_ccbs, M_DEVBUF); 503 } 504 if ((fl & AMRF_ENQBUF) != 0) 505 free(amr->amr_enqbuf, M_DEVBUF); 506 if ((fl & AMRF_DMA_LOAD) != 0) 507 bus_dmamap_unload(amr->amr_dmat, amr->amr_dmamap); 508 if ((fl & AMRF_DMA_MAP) != 0) 509 bus_dmamem_unmap(amr->amr_dmat, (caddr_t)amr->amr_mbox, 510 amr->amr_dmasize); 511 if ((fl & AMRF_DMA_ALLOC) != 0) 512 bus_dmamem_free(amr->amr_dmat, &amr->amr_dmaseg, 1); 513 if ((fl & AMRF_DMA_CREATE) != 0) 514 bus_dmamap_destroy(amr->amr_dmat, amr->amr_dmamap); 515 if ((fl & AMRF_PCI_INTR) != 0) 516 pci_intr_disestablish(amr->amr_pc, amr->amr_ih); 517 if ((fl & AMRF_PCI_REGS) != 0) 518 bus_space_unmap(amr->amr_iot, amr->amr_ioh, amr->amr_ios); 519 } 520 521 /* 522 * Print autoconfiguration message for a sub-device. 523 */ 524 int 525 amr_print(void *aux, const char *pnp) 526 { 527 struct amr_attach_args *amra; 528 529 amra = (struct amr_attach_args *)aux; 530 531 if (pnp != NULL) 532 aprint_normal("block device at %s", pnp); 533 aprint_normal(" unit %d", amra->amra_unit); 534 return (UNCONF); 535 } 536 537 /* 538 * Match a sub-device. 539 */ 540 int 541 amr_submatch(struct device *parent, struct cfdata *cf, void *aux) 542 { 543 struct amr_attach_args *amra; 544 545 amra = (struct amr_attach_args *)aux; 546 547 if (cf->amracf_unit != AMRCF_UNIT_DEFAULT && 548 cf->amracf_unit != amra->amra_unit) 549 return (0); 550 551 return (config_match(parent, cf, aux)); 552 } 553 554 /* 555 * Retrieve operational parameters and describe the controller. 556 */ 557 int 558 amr_init(struct amr_softc *amr, const char *intrstr, 559 struct pci_attach_args *pa) 560 { 561 struct amr_adapter_info *aa; 562 struct amr_prodinfo *ap; 563 struct amr_enquiry *ae; 564 struct amr_enquiry3 *aex; 565 const char *prodstr; 566 u_int i, sig, ishp; 567 char buf[64]; 568 569 /* 570 * Try to get 40LD product info, which tells us what the card is 571 * labelled as. 572 */ 573 ap = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_PRODUCT_INFO, 0, 574 amr->amr_enqbuf); 575 if (ap != NULL) { 576 aprint_normal("<%.80s>\n", ap->ap_product); 577 if (intrstr != NULL) 578 aprint_normal("%s: interrupting at %s\n", 579 amr->amr_dv.dv_xname, intrstr); 580 aprint_normal("%s: firmware %.16s, BIOS %.16s, %dMB RAM\n", 581 amr->amr_dv.dv_xname, ap->ap_firmware, ap->ap_bios, 582 le16toh(ap->ap_memsize)); 583 584 amr->amr_maxqueuecnt = ap->ap_maxio; 585 586 /* 587 * Fetch and record state of logical drives. 588 */ 589 aex = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_ENQ3, 590 AMR_CONFIG_ENQ3_SOLICITED_FULL, amr->amr_enqbuf); 591 if (aex == NULL) { 592 aprint_error("%s ENQUIRY3 failed\n", 593 amr->amr_dv.dv_xname); 594 return (-1); 595 } 596 597 if (aex->ae_numldrives > AMR_MAX_UNITS) { 598 aprint_error( 599 "%s: adjust AMR_MAX_UNITS to %d (currently %d)" 600 "\n", amr->amr_dv.dv_xname, 601 ae->ae_ldrv.al_numdrives, AMR_MAX_UNITS); 602 amr->amr_numdrives = AMR_MAX_UNITS; 603 } else 604 amr->amr_numdrives = aex->ae_numldrives; 605 606 for (i = 0; i < amr->amr_numdrives; i++) { 607 amr->amr_drive[i].al_size = 608 le32toh(aex->ae_drivesize[i]); 609 amr->amr_drive[i].al_state = aex->ae_drivestate[i]; 610 amr->amr_drive[i].al_properties = aex->ae_driveprop[i]; 611 } 612 613 return (0); 614 } 615 616 /* 617 * Try 8LD extended ENQUIRY to get the controller signature. Once 618 * found, search for a product description. 619 */ 620 ae = amr_enquire(amr, AMR_CMD_EXT_ENQUIRY2, 0, 0, amr->amr_enqbuf); 621 if (ae != NULL) { 622 i = 0; 623 sig = le32toh(ae->ae_signature); 624 625 while (i < sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 626 if (amr_typestr[i].at_sig == sig) 627 break; 628 i++; 629 } 630 if (i == sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 631 sprintf(buf, "unknown ENQUIRY2 sig (0x%08x)", sig); 632 prodstr = buf; 633 } else 634 prodstr = amr_typestr[i].at_str; 635 } else { 636 ae = amr_enquire(amr, AMR_CMD_ENQUIRY, 0, 0, amr->amr_enqbuf); 637 if (ae == NULL) { 638 aprint_error("%s: unsupported controller\n", 639 amr->amr_dv.dv_xname); 640 return (-1); 641 } 642 643 switch (PCI_PRODUCT(pa->pa_id)) { 644 case PCI_PRODUCT_AMI_MEGARAID: 645 prodstr = "Series 428"; 646 break; 647 case PCI_PRODUCT_AMI_MEGARAID2: 648 prodstr = "Series 434"; 649 break; 650 default: 651 sprintf(buf, "unknown PCI dev (0x%04x)", 652 PCI_PRODUCT(pa->pa_id)); 653 prodstr = buf; 654 break; 655 } 656 } 657 658 /* 659 * HP NetRaid controllers have a special encoding of the firmware 660 * and BIOS versions. The AMI version seems to have it as strings 661 * whereas the HP version does it with a leading uppercase character 662 * and two binary numbers. 663 */ 664 aa = &ae->ae_adapter; 665 666 if (aa->aa_firmware[2] >= 'A' && aa->aa_firmware[2] <= 'Z' && 667 aa->aa_firmware[1] < ' ' && aa->aa_firmware[0] < ' ' && 668 aa->aa_bios[2] >= 'A' && aa->aa_bios[2] <= 'Z' && 669 aa->aa_bios[1] < ' ' && aa->aa_bios[0] < ' ') { 670 if (le32toh(ae->ae_signature) == AMR_SIG_438) { 671 /* The AMI 438 is a NetRaid 3si in HP-land. */ 672 prodstr = "HP NetRaid 3si"; 673 } 674 ishp = 1; 675 } else 676 ishp = 0; 677 678 aprint_normal("<%s>\n", prodstr); 679 if (intrstr != NULL) 680 aprint_normal("%s: interrupting at %s\n", amr->amr_dv.dv_xname, 681 intrstr); 682 683 if (ishp) 684 aprint_normal("%s: firmware <%c.%02d.%02d>, BIOS <%c.%02d.%02d>" 685 ", %dMB RAM\n", amr->amr_dv.dv_xname, aa->aa_firmware[2], 686 aa->aa_firmware[1], aa->aa_firmware[0], aa->aa_bios[2], 687 aa->aa_bios[1], aa->aa_bios[0], aa->aa_memorysize); 688 else 689 aprint_normal("%s: firmware <%.4s>, BIOS <%.4s>, %dMB RAM\n", 690 amr->amr_dv.dv_xname, aa->aa_firmware, aa->aa_bios, 691 aa->aa_memorysize); 692 693 amr->amr_maxqueuecnt = aa->aa_maxio; 694 695 /* 696 * Record state of logical drives. 697 */ 698 if (ae->ae_ldrv.al_numdrives > AMR_MAX_UNITS) { 699 aprint_error("%s: adjust AMR_MAX_UNITS to %d (currently %d)\n", 700 amr->amr_dv.dv_xname, ae->ae_ldrv.al_numdrives, 701 AMR_MAX_UNITS); 702 amr->amr_numdrives = AMR_MAX_UNITS; 703 } else 704 amr->amr_numdrives = ae->ae_ldrv.al_numdrives; 705 706 for (i = 0; i < AMR_MAX_UNITS; i++) { 707 amr->amr_drive[i].al_size = le32toh(ae->ae_ldrv.al_size[i]); 708 amr->amr_drive[i].al_state = ae->ae_ldrv.al_state[i]; 709 amr->amr_drive[i].al_properties = ae->ae_ldrv.al_properties[i]; 710 } 711 712 return (0); 713 } 714 715 /* 716 * Flush the internal cache on each configured controller. Called at 717 * shutdown time. 718 */ 719 void 720 amr_shutdown(void *cookie) 721 { 722 extern struct cfdriver amr_cd; 723 struct amr_softc *amr; 724 struct amr_ccb *ac; 725 int i, rv, s; 726 727 for (i = 0; i < amr_cd.cd_ndevs; i++) { 728 if ((amr = device_lookup(&amr_cd, i)) == NULL) 729 continue; 730 731 if ((rv = amr_ccb_alloc(amr, &ac)) == 0) { 732 ac->ac_cmd.mb_command = AMR_CMD_FLUSH; 733 s = splbio(); 734 rv = amr_ccb_poll(amr, ac, 30000); 735 splx(s); 736 amr_ccb_free(amr, ac); 737 } 738 if (rv != 0) 739 printf("%s: unable to flush cache (%d)\n", 740 amr->amr_dv.dv_xname, rv); 741 } 742 } 743 744 /* 745 * Interrupt service routine. 746 */ 747 int 748 amr_intr(void *cookie) 749 { 750 struct amr_softc *amr; 751 struct amr_ccb *ac; 752 struct amr_mailbox_resp mbox; 753 u_int i, forus, idx; 754 755 amr = cookie; 756 forus = 0; 757 758 while ((*amr->amr_get_work)(amr, &mbox) == 0) { 759 /* Iterate over completed commands in this result. */ 760 for (i = 0; i < mbox.mb_nstatus; i++) { 761 idx = mbox.mb_completed[i] - 1; 762 ac = amr->amr_ccbs + idx; 763 764 if (idx >= amr->amr_maxqueuecnt) { 765 printf("%s: bad status (bogus ID: %u=%u)\n", 766 amr->amr_dv.dv_xname, i, idx); 767 continue; 768 } 769 770 if ((ac->ac_flags & AC_ACTIVE) == 0) { 771 printf("%s: bad status (not active; 0x04%x)\n", 772 amr->amr_dv.dv_xname, ac->ac_flags); 773 continue; 774 } 775 776 ac->ac_status = mbox.mb_status; 777 ac->ac_flags = (ac->ac_flags & ~AC_ACTIVE) | 778 AC_COMPLETE; 779 TAILQ_REMOVE(&amr->amr_ccb_active, ac, ac_chain.tailq); 780 781 if ((ac->ac_flags & AC_MOAN) != 0) 782 printf("%s: ccb %d completed\n", 783 amr->amr_dv.dv_xname, ac->ac_ident); 784 785 /* Pass notification to upper layers. */ 786 if (ac->ac_handler != NULL) 787 (*ac->ac_handler)(ac); 788 else 789 wakeup(ac); 790 } 791 forus = 1; 792 } 793 794 if (forus) 795 amr_ccb_enqueue(amr, NULL); 796 797 return (forus); 798 } 799 800 /* 801 * Create the watchdog thread. 802 */ 803 void 804 amr_thread_create(void *cookie) 805 { 806 struct amr_softc *amr; 807 int rv; 808 809 amr = cookie; 810 811 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 812 amr->amr_flags ^= AMRF_THREAD_EXIT; 813 wakeup(&amr->amr_flags); 814 return; 815 } 816 817 rv = kthread_create1(amr_thread, amr, &amr->amr_thread, "%s", 818 amr->amr_dv.dv_xname); 819 if (rv != 0) 820 aprint_error("%s: unable to create thread (%d)", 821 amr->amr_dv.dv_xname, rv); 822 else 823 amr->amr_flags |= AMRF_THREAD; 824 } 825 826 /* 827 * Watchdog thread. 828 */ 829 void 830 amr_thread(void *cookie) 831 { 832 struct amr_softc *amr; 833 struct amr_ccb *ac; 834 struct amr_logdrive *al; 835 struct amr_enquiry *ae; 836 time_t curtime; 837 int rv, i, s; 838 839 amr = cookie; 840 ae = amr->amr_enqbuf; 841 842 for (;;) { 843 tsleep(amr_thread, PWAIT, "amrwdog", AMR_WDOG_TICKS); 844 845 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 846 amr->amr_flags ^= AMRF_THREAD_EXIT; 847 wakeup(&amr->amr_flags); 848 kthread_exit(0); 849 } 850 851 s = splbio(); 852 amr_intr(cookie); 853 curtime = (time_t)mono_time.tv_sec; 854 if ((ac = TAILQ_FIRST(&amr->amr_ccb_active)) != NULL) { 855 if (ac->ac_start_time + AMR_TIMEOUT > curtime) 856 break; 857 if ((ac->ac_flags & AC_MOAN) == 0) { 858 printf("%s: ccb %d timed out; mailbox:\n", 859 amr->amr_dv.dv_xname, ac->ac_ident); 860 amr_ccb_dump(amr, ac); 861 ac->ac_flags |= AC_MOAN; 862 } 863 } 864 splx(s); 865 866 if ((rv = amr_ccb_alloc(amr, &ac)) != 0) { 867 printf("%s: ccb_alloc failed (%d)\n", 868 amr->amr_dv.dv_xname, rv); 869 continue; 870 } 871 872 ac->ac_cmd.mb_command = AMR_CMD_ENQUIRY; 873 874 rv = amr_ccb_map(amr, ac, amr->amr_enqbuf, 875 AMR_ENQUIRY_BUFSIZE, 0); 876 if (rv != 0) { 877 printf("%s: ccb_map failed (%d)\n", 878 amr->amr_dv.dv_xname, rv); 879 amr_ccb_free(amr, ac); 880 continue; 881 } 882 883 rv = amr_ccb_wait(amr, ac); 884 amr_ccb_unmap(amr, ac); 885 if (rv != 0) { 886 printf("%s: enquiry failed (st=%d)\n", 887 amr->amr_dv.dv_xname, ac->ac_status); 888 continue; 889 } 890 amr_ccb_free(amr, ac); 891 892 al = amr->amr_drive; 893 for (i = 0; i < AMR_MAX_UNITS; i++, al++) { 894 if (al->al_dv == NULL) 895 continue; 896 if (al->al_state == ae->ae_ldrv.al_state[i]) 897 continue; 898 899 printf("%s: state changed: %s -> %s\n", 900 al->al_dv->dv_xname, 901 amr_drive_state(al->al_state, NULL), 902 amr_drive_state(ae->ae_ldrv.al_state[i], NULL)); 903 904 al->al_state = ae->ae_ldrv.al_state[i]; 905 } 906 } 907 } 908 909 /* 910 * Return a text description of a logical drive's current state. 911 */ 912 const char * 913 amr_drive_state(int state, int *happy) 914 { 915 const char *str; 916 917 state = AMR_DRV_CURSTATE(state); 918 if (state >= sizeof(amr_dstate) / sizeof(amr_dstate[0])) { 919 if (happy) 920 *happy = 1; 921 str = "status unknown"; 922 } else { 923 if (happy) 924 *happy = amr_dstate[state].ds_happy; 925 str = amr_dstate[state].ds_descr; 926 } 927 928 return (str); 929 } 930 931 /* 932 * Run a generic enquiry-style command. 933 */ 934 void * 935 amr_enquire(struct amr_softc *amr, u_int8_t cmd, u_int8_t cmdsub, 936 u_int8_t cmdqual, void *buf) 937 { 938 struct amr_ccb *ac; 939 u_int8_t *mb; 940 int rv; 941 942 if (amr_ccb_alloc(amr, &ac) != 0) 943 return (NULL); 944 945 /* Build the command proper. */ 946 mb = (u_int8_t *)&ac->ac_cmd; 947 mb[0] = cmd; 948 mb[2] = cmdsub; 949 mb[3] = cmdqual; 950 951 rv = amr_ccb_map(amr, ac, buf, AMR_ENQUIRY_BUFSIZE, 0); 952 if (rv == 0) { 953 rv = amr_ccb_poll(amr, ac, 2000); 954 amr_ccb_unmap(amr, ac); 955 } 956 amr_ccb_free(amr, ac); 957 958 return (rv ? NULL : buf); 959 } 960 961 /* 962 * Allocate and initialise a CCB. 963 */ 964 int 965 amr_ccb_alloc(struct amr_softc *amr, struct amr_ccb **acp) 966 { 967 int s; 968 969 s = splbio(); 970 if ((*acp = SLIST_FIRST(&amr->amr_ccb_freelist)) == NULL) { 971 splx(s); 972 return (EAGAIN); 973 } 974 SLIST_REMOVE_HEAD(&amr->amr_ccb_freelist, ac_chain.slist); 975 splx(s); 976 977 return (0); 978 } 979 980 /* 981 * Free a CCB. 982 */ 983 void 984 amr_ccb_free(struct amr_softc *amr, struct amr_ccb *ac) 985 { 986 int s; 987 988 memset(&ac->ac_cmd, 0, sizeof(ac->ac_cmd)); 989 ac->ac_cmd.mb_ident = ac->ac_ident + 1; 990 ac->ac_cmd.mb_busy = 1; 991 ac->ac_handler = NULL; 992 ac->ac_flags = 0; 993 994 s = splbio(); 995 SLIST_INSERT_HEAD(&amr->amr_ccb_freelist, ac, ac_chain.slist); 996 splx(s); 997 } 998 999 /* 1000 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 1001 * the order that they were enqueued and try to submit their command blocks 1002 * to the controller for execution. 1003 */ 1004 void 1005 amr_ccb_enqueue(struct amr_softc *amr, struct amr_ccb *ac) 1006 { 1007 int s; 1008 1009 s = splbio(); 1010 1011 if (ac != NULL) 1012 SIMPLEQ_INSERT_TAIL(&amr->amr_ccb_queue, ac, ac_chain.simpleq); 1013 1014 while ((ac = SIMPLEQ_FIRST(&amr->amr_ccb_queue)) != NULL) { 1015 if ((*amr->amr_submit)(amr, ac) != 0) 1016 break; 1017 SIMPLEQ_REMOVE_HEAD(&amr->amr_ccb_queue, ac_chain.simpleq); 1018 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1019 } 1020 1021 splx(s); 1022 } 1023 1024 /* 1025 * Map the specified CCB's data buffer onto the bus, and fill the 1026 * scatter-gather list. 1027 */ 1028 int 1029 amr_ccb_map(struct amr_softc *amr, struct amr_ccb *ac, void *data, int size, 1030 int out) 1031 { 1032 struct amr_sgentry *sge; 1033 struct amr_mailbox_cmd *mb; 1034 int nsegs, i, rv, sgloff; 1035 bus_dmamap_t xfer; 1036 1037 xfer = ac->ac_xfer_map; 1038 1039 rv = bus_dmamap_load(amr->amr_dmat, xfer, data, size, NULL, 1040 BUS_DMA_NOWAIT); 1041 if (rv != 0) 1042 return (rv); 1043 1044 mb = &ac->ac_cmd; 1045 ac->ac_xfer_size = size; 1046 ac->ac_flags |= (out ? AC_XFER_OUT : AC_XFER_IN); 1047 sgloff = AMR_SGL_SIZE * ac->ac_ident; 1048 1049 /* We don't need to use a scatter/gather list for just 1 segment. */ 1050 nsegs = xfer->dm_nsegs; 1051 if (nsegs == 1) { 1052 mb->mb_nsgelem = 0; 1053 mb->mb_physaddr = htole32(xfer->dm_segs[0].ds_addr); 1054 ac->ac_flags |= AC_NOSGL; 1055 } else { 1056 mb->mb_nsgelem = nsegs; 1057 mb->mb_physaddr = htole32(amr->amr_sgls_paddr + sgloff); 1058 1059 sge = (struct amr_sgentry *)((caddr_t)amr->amr_sgls + sgloff); 1060 for (i = 0; i < nsegs; i++, sge++) { 1061 sge->sge_addr = htole32(xfer->dm_segs[i].ds_addr); 1062 sge->sge_count = htole32(xfer->dm_segs[i].ds_len); 1063 } 1064 } 1065 1066 bus_dmamap_sync(amr->amr_dmat, xfer, 0, ac->ac_xfer_size, 1067 out ? BUS_DMASYNC_PREWRITE : BUS_DMASYNC_PREREAD); 1068 1069 if ((ac->ac_flags & AC_NOSGL) == 0) 1070 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, sgloff, 1071 AMR_SGL_SIZE, BUS_DMASYNC_PREWRITE); 1072 1073 return (0); 1074 } 1075 1076 /* 1077 * Unmap the specified CCB's data buffer. 1078 */ 1079 void 1080 amr_ccb_unmap(struct amr_softc *amr, struct amr_ccb *ac) 1081 { 1082 1083 if ((ac->ac_flags & AC_NOSGL) == 0) 1084 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 1085 AMR_SGL_SIZE * ac->ac_ident, AMR_SGL_SIZE, 1086 BUS_DMASYNC_POSTWRITE); 1087 bus_dmamap_sync(amr->amr_dmat, ac->ac_xfer_map, 0, ac->ac_xfer_size, 1088 (ac->ac_flags & AC_XFER_IN) != 0 ? 1089 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1090 bus_dmamap_unload(amr->amr_dmat, ac->ac_xfer_map); 1091 } 1092 1093 /* 1094 * Submit a command to the controller and poll on completion. Return 1095 * non-zero on timeout or error. Must be called with interrupts blocked. 1096 */ 1097 int 1098 amr_ccb_poll(struct amr_softc *amr, struct amr_ccb *ac, int timo) 1099 { 1100 int rv; 1101 1102 if ((rv = (*amr->amr_submit)(amr, ac)) != 0) 1103 return (rv); 1104 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1105 1106 for (timo *= 10; timo != 0; timo--) { 1107 amr_intr(amr); 1108 if ((ac->ac_flags & AC_COMPLETE) != 0) 1109 break; 1110 DELAY(100); 1111 } 1112 1113 return (timo == 0 || ac->ac_status != 0 ? EIO : 0); 1114 } 1115 1116 /* 1117 * Submit a command to the controller and sleep on completion. Return 1118 * non-zero on error. 1119 */ 1120 int 1121 amr_ccb_wait(struct amr_softc *amr, struct amr_ccb *ac) 1122 { 1123 int s; 1124 1125 s = splbio(); 1126 amr_ccb_enqueue(amr, ac); 1127 tsleep(ac, PRIBIO, "amrcmd", 0); 1128 splx(s); 1129 1130 return (ac->ac_status != 0 ? EIO : 0); 1131 } 1132 1133 /* 1134 * Wait for the mailbox to become available. 1135 */ 1136 int 1137 amr_mbox_wait(struct amr_softc *amr) 1138 { 1139 int timo; 1140 1141 for (timo = 10000; timo != 0; timo--) { 1142 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1143 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1144 if (amr->amr_mbox->mb_cmd.mb_busy == 0) 1145 break; 1146 DELAY(100); 1147 } 1148 1149 if (timo == 0) 1150 printf("%s: controller wedged\n", amr->amr_dv.dv_xname); 1151 1152 return (timo != 0 ? 0 : EAGAIN); 1153 } 1154 1155 /* 1156 * Tell the controller that the mailbox contains a valid command. Must be 1157 * called with interrupts blocked. 1158 */ 1159 int 1160 amr_quartz_submit(struct amr_softc *amr, struct amr_ccb *ac) 1161 { 1162 u_int32_t v; 1163 1164 amr->amr_mbox->mb_poll = 0; 1165 amr->amr_mbox->mb_ack = 0; 1166 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1167 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1168 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1169 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1170 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1171 return (EAGAIN); 1172 1173 v = amr_inl(amr, AMR_QREG_IDB); 1174 if ((v & (AMR_QIDB_SUBMIT | AMR_QIDB_ACK)) != 0) { 1175 amr->amr_mbox->mb_cmd.mb_busy = 0; 1176 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1177 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1178 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1179 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1180 return (EAGAIN); 1181 } 1182 1183 amr->amr_mbox->mb_segment = 0; 1184 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1185 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1186 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1187 1188 ac->ac_start_time = (time_t)mono_time.tv_sec; 1189 ac->ac_flags |= AC_ACTIVE; 1190 amr_outl(amr, AMR_QREG_IDB, amr->amr_mbox_paddr | AMR_QIDB_SUBMIT); 1191 return (0); 1192 } 1193 1194 int 1195 amr_std_submit(struct amr_softc *amr, struct amr_ccb *ac) 1196 { 1197 1198 amr->amr_mbox->mb_poll = 0; 1199 amr->amr_mbox->mb_ack = 0; 1200 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1201 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1202 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1203 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1204 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1205 return (EAGAIN); 1206 1207 if ((amr_inb(amr, AMR_SREG_MBOX_BUSY) & AMR_SMBOX_BUSY_FLAG) != 0) { 1208 amr->amr_mbox->mb_cmd.mb_busy = 0; 1209 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1210 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1211 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1212 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1213 return (EAGAIN); 1214 } 1215 1216 amr->amr_mbox->mb_segment = 0; 1217 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1218 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1219 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1220 1221 ac->ac_start_time = (time_t)mono_time.tv_sec; 1222 ac->ac_flags |= AC_ACTIVE; 1223 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_POST); 1224 return (0); 1225 } 1226 1227 /* 1228 * Claim any work that the controller has completed; acknowledge completion, 1229 * save details of the completion in (mbsave). Must be called with 1230 * interrupts blocked. 1231 */ 1232 int 1233 amr_quartz_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1234 { 1235 1236 /* Work waiting for us? */ 1237 if (amr_inl(amr, AMR_QREG_ODB) != AMR_QODB_READY) 1238 return (-1); 1239 1240 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1241 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1242 1243 /* Save the mailbox, which contains a list of completed commands. */ 1244 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1245 1246 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1247 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1248 1249 /* Ack the interrupt and mailbox transfer. */ 1250 amr_outl(amr, AMR_QREG_ODB, AMR_QODB_READY); 1251 amr_outl(amr, AMR_QREG_IDB, (amr->amr_mbox_paddr+16) | AMR_QIDB_ACK); 1252 1253 /* 1254 * This waits for the controller to notice that we've taken the 1255 * command from it. It's very inefficient, and we shouldn't do it, 1256 * but if we remove this code, we stop completing commands under 1257 * load. 1258 * 1259 * Peter J says we shouldn't do this. The documentation says we 1260 * should. Who is right? 1261 */ 1262 while ((amr_inl(amr, AMR_QREG_IDB) & AMR_QIDB_ACK) != 0) 1263 ; 1264 1265 return (0); 1266 } 1267 1268 int 1269 amr_std_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1270 { 1271 u_int8_t istat; 1272 1273 /* Check for valid interrupt status. */ 1274 if (((istat = amr_inb(amr, AMR_SREG_INTR)) & AMR_SINTR_VALID) == 0) 1275 return (-1); 1276 1277 /* Ack the interrupt. */ 1278 amr_outb(amr, AMR_SREG_INTR, istat); 1279 1280 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1281 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1282 1283 /* Save mailbox, which contains a list of completed commands. */ 1284 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1285 1286 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1287 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1288 1289 /* Ack mailbox transfer. */ 1290 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 1291 1292 return (0); 1293 } 1294 1295 void 1296 amr_ccb_dump(struct amr_softc *amr, struct amr_ccb *ac) 1297 { 1298 int i; 1299 1300 printf("%s: ", amr->amr_dv.dv_xname); 1301 for (i = 0; i < 4; i++) 1302 printf("%08x ", ((u_int32_t *)&ac->ac_cmd)[i]); 1303 printf("\n"); 1304 } 1305
Indexes created Thu Oct 02 14:10:14 GMT 2025