amr.c revision 1.14
1 /* $NetBSD: amr.c,v 1.14 2003/10/14 11:33:36 martti Exp $ */ 2 3 /*- 4 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999,2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: amr_pci.c,v 1.5 2000/08/30 07:52:40 msmith Exp 66 * from FreeBSD: amr.c,v 1.16 2000/08/30 07:52:40 msmith Exp 67 */ 68 69 /* 70 * Driver for AMI RAID controllers. 71 */ 72 73 #include <sys/cdefs.h> 74 __KERNEL_RCSID(0, "$NetBSD: amr.c,v 1.14 2003/10/14 11:33:36 martti Exp $"); 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/device.h> 80 #include <sys/queue.h> 81 #include <sys/proc.h> 82 #include <sys/buf.h> 83 #include <sys/malloc.h> 84 #include <sys/kthread.h> 85 86 #include <uvm/uvm_extern.h> 87 88 #include <machine/endian.h> 89 #include <machine/bus.h> 90 91 #include <dev/pci/pcidevs.h> 92 #include <dev/pci/pcivar.h> 93 #include <dev/pci/amrreg.h> 94 #include <dev/pci/amrvar.h> 95 96 void amr_attach(struct device *, struct device *, void *); 97 void amr_ccb_dump(struct amr_softc *, struct amr_ccb *); 98 void *amr_enquire(struct amr_softc *, u_int8_t, u_int8_t, u_int8_t, void *); 99 int amr_init(struct amr_softc *, const char *, 100 struct pci_attach_args *pa); 101 int amr_intr(void *); 102 int amr_match(struct device *, struct cfdata *, void *); 103 int amr_print(void *, const char *); 104 void amr_shutdown(void *); 105 int amr_submatch(struct device *, struct cfdata *, void *); 106 void amr_teardown(struct amr_softc *); 107 void amr_thread(void *); 108 void amr_thread_create(void *); 109 110 int amr_mbox_wait(struct amr_softc *); 111 int amr_quartz_get_work(struct amr_softc *, struct amr_mailbox_resp *); 112 int amr_quartz_submit(struct amr_softc *, struct amr_ccb *); 113 int amr_std_get_work(struct amr_softc *, struct amr_mailbox_resp *); 114 int amr_std_submit(struct amr_softc *, struct amr_ccb *); 115 116 static inline u_int8_t amr_inb(struct amr_softc *, int); 117 static inline u_int32_t amr_inl(struct amr_softc *, int); 118 static inline void amr_outb(struct amr_softc *, int, u_int8_t); 119 static inline void amr_outl(struct amr_softc *, int, u_int32_t); 120 121 CFATTACH_DECL(amr, sizeof(struct amr_softc), 122 amr_match, amr_attach, NULL, NULL); 123 124 #define AT_QUARTZ 0x01 /* `Quartz' chipset */ 125 #define AT_SIG 0x02 /* Check for signature */ 126 127 struct amr_pci_type { 128 u_short apt_vendor; 129 u_short apt_product; 130 u_short apt_flags; 131 } const amr_pci_type[] = { 132 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID, 0 }, 133 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID2, 0 }, 134 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ | AT_SIG }, 136 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI, AT_QUARTZ }, 137 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI_2, AT_QUARTZ }, 138 }; 139 140 struct amr_typestr { 141 const char *at_str; 142 int at_sig; 143 } const amr_typestr[] = { 144 { "Series 431", AMR_SIG_431 }, 145 { "Series 438", AMR_SIG_438 }, 146 { "Series 466", AMR_SIG_466 }, 147 { "Series 467", AMR_SIG_467 }, 148 { "Series 490", AMR_SIG_490 }, 149 { "Series 762", AMR_SIG_762 }, 150 { "HP NetRAID (T5)", AMR_SIG_T5 }, 151 { "HP NetRAID (T7)", AMR_SIG_T7 }, 152 }; 153 154 struct { 155 const char *ds_descr; 156 int ds_happy; 157 } const amr_dstate[] = { 158 { "offline", 0 }, 159 { "degraded", 1 }, 160 { "optimal", 1 }, 161 { "online", 1 }, 162 { "failed", 0 }, 163 { "rebuilding", 1 }, 164 { "hotspare", 0 }, 165 }; 166 167 void *amr_sdh; 168 int amr_max_segs; 169 int amr_max_xfer; 170 171 static inline u_int8_t 172 amr_inb(struct amr_softc *amr, int off) 173 { 174 175 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 176 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 177 return (bus_space_read_1(amr->amr_iot, amr->amr_ioh, off)); 178 } 179 180 static inline u_int32_t 181 amr_inl(struct amr_softc *amr, int off) 182 { 183 184 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 185 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 186 return (bus_space_read_4(amr->amr_iot, amr->amr_ioh, off)); 187 } 188 189 static inline void 190 amr_outb(struct amr_softc *amr, int off, u_int8_t val) 191 { 192 193 bus_space_write_1(amr->amr_iot, amr->amr_ioh, off, val); 194 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 195 BUS_SPACE_BARRIER_WRITE); 196 } 197 198 static inline void 199 amr_outl(struct amr_softc *amr, int off, u_int32_t val) 200 { 201 202 bus_space_write_4(amr->amr_iot, amr->amr_ioh, off, val); 203 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 204 BUS_SPACE_BARRIER_WRITE); 205 } 206 207 /* 208 * Match a supported device. 209 */ 210 int 211 amr_match(struct device *parent, struct cfdata *match, void *aux) 212 { 213 struct pci_attach_args *pa; 214 pcireg_t s; 215 int i; 216 217 pa = (struct pci_attach_args *)aux; 218 219 /* 220 * Don't match the device if it's operating in I2O mode. In this 221 * case it should be handled by the `iop' driver. 222 */ 223 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 224 return (0); 225 226 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 227 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 228 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 229 break; 230 231 if (i == sizeof(amr_pci_type) / sizeof(amr_pci_type[0])) 232 return (0); 233 234 if ((amr_pci_type[i].apt_flags & AT_SIG) == 0) 235 return (1); 236 237 s = pci_conf_read(pa->pa_pc, pa->pa_tag, AMR_QUARTZ_SIG_REG) & 0xffff; 238 return (s == AMR_QUARTZ_SIG0 || s == AMR_QUARTZ_SIG1); 239 } 240 241 /* 242 * Attach a supported device. 243 */ 244 void 245 amr_attach(struct device *parent, struct device *self, void *aux) 246 { 247 bus_space_tag_t memt, iot; 248 bus_space_handle_t memh, ioh; 249 struct pci_attach_args *pa; 250 struct amr_attach_args amra; 251 const struct amr_pci_type *apt; 252 struct amr_softc *amr; 253 pci_chipset_tag_t pc; 254 pci_intr_handle_t ih; 255 const char *intrstr; 256 pcireg_t reg; 257 int rseg, i, j, size, rv, memreg, ioreg; 258 bus_size_t memsize, iosize; 259 struct amr_ccb *ac; 260 261 aprint_naive(": RAID controller\n"); 262 263 amr = (struct amr_softc *)self; 264 pa = (struct pci_attach_args *)aux; 265 pc = pa->pa_pc; 266 267 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 268 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 269 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 270 break; 271 apt = amr_pci_type + i; 272 273 memreg = ioreg = 0; 274 for (i = 0x10; i <= 0x14; i += 4) { 275 reg = pci_conf_read(pc, pa->pa_tag, i); 276 switch (PCI_MAPREG_TYPE(reg)) { 277 case PCI_MAPREG_TYPE_MEM: 278 if ((memsize = PCI_MAPREG_MEM_SIZE(reg)) != 0) 279 memreg = i; 280 break; 281 case PCI_MAPREG_TYPE_IO: 282 if ((iosize = PCI_MAPREG_IO_SIZE(reg)) != 0) 283 ioreg = i; 284 break; 285 } 286 } 287 288 if (memreg != 0) 289 if (pci_mapreg_map(pa, memreg, PCI_MAPREG_TYPE_MEM, 0, 290 &memt, &memh, NULL, NULL)) 291 memreg = 0; 292 if (ioreg != 0) 293 if (pci_mapreg_map(pa, ioreg, PCI_MAPREG_TYPE_IO, 0, 294 &iot, &ioh, NULL, NULL)) 295 ioreg = 0; 296 297 if (memreg) { 298 amr->amr_iot = memt; 299 amr->amr_ioh = memh; 300 amr->amr_ios = memsize; 301 } else if (ioreg) { 302 amr->amr_iot = iot; 303 amr->amr_ioh = ioh; 304 amr->amr_ios = iosize; 305 } else { 306 aprint_error("can't map control registers\n"); 307 amr_teardown(amr); 308 return; 309 } 310 311 amr->amr_flags |= AMRF_PCI_REGS; 312 amr->amr_dmat = pa->pa_dmat; 313 amr->amr_pc = pa->pa_pc; 314 315 /* Enable the device. */ 316 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 317 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 318 reg | PCI_COMMAND_MASTER_ENABLE); 319 320 /* Map and establish the interrupt. */ 321 if (pci_intr_map(pa, &ih)) { 322 aprint_error("can't map interrupt\n"); 323 amr_teardown(amr); 324 return; 325 } 326 intrstr = pci_intr_string(pc, ih); 327 amr->amr_ih = pci_intr_establish(pc, ih, IPL_BIO, amr_intr, amr); 328 if (amr->amr_ih == NULL) { 329 aprint_error("can't establish interrupt"); 330 if (intrstr != NULL) 331 aprint_normal(" at %s", intrstr); 332 aprint_normal("\n"); 333 amr_teardown(amr); 334 return; 335 } 336 amr->amr_flags |= AMRF_PCI_INTR; 337 338 /* 339 * Allocate space for the mailbox and S/G lists. Some controllers 340 * don't like S/G lists to be located below 0x2000, so we allocate 341 * enough slop to enable us to compensate. 342 * 343 * The standard mailbox structure needs to be aligned on a 16-byte 344 * boundary. The 64-bit mailbox has one extra field, 4 bytes in 345 * size, which preceeds the standard mailbox. 346 */ 347 size = AMR_SGL_SIZE * AMR_MAX_CMDS + 0x2000; 348 amr->amr_dmasize = size; 349 350 if ((rv = bus_dmamem_alloc(amr->amr_dmat, size, PAGE_SIZE, NULL, 351 &amr->amr_dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 352 aprint_error("%s: unable to allocate buffer, rv = %d\n", 353 amr->amr_dv.dv_xname, rv); 354 amr_teardown(amr); 355 return; 356 } 357 amr->amr_flags |= AMRF_DMA_ALLOC; 358 359 if ((rv = bus_dmamem_map(amr->amr_dmat, &amr->amr_dmaseg, rseg, size, 360 (caddr_t *)&amr->amr_mbox, 361 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 362 aprint_error("%s: unable to map buffer, rv = %d\n", 363 amr->amr_dv.dv_xname, rv); 364 amr_teardown(amr); 365 return; 366 } 367 amr->amr_flags |= AMRF_DMA_MAP; 368 369 if ((rv = bus_dmamap_create(amr->amr_dmat, size, 1, size, 0, 370 BUS_DMA_NOWAIT, &amr->amr_dmamap)) != 0) { 371 aprint_error("%s: unable to create buffer DMA map, rv = %d\n", 372 amr->amr_dv.dv_xname, rv); 373 amr_teardown(amr); 374 return; 375 } 376 amr->amr_flags |= AMRF_DMA_CREATE; 377 378 if ((rv = bus_dmamap_load(amr->amr_dmat, amr->amr_dmamap, 379 amr->amr_mbox, size, NULL, BUS_DMA_NOWAIT)) != 0) { 380 aprint_error("%s: unable to load buffer DMA map, rv = %d\n", 381 amr->amr_dv.dv_xname, rv); 382 amr_teardown(amr); 383 return; 384 } 385 amr->amr_flags |= AMRF_DMA_LOAD; 386 387 memset(amr->amr_mbox, 0, size); 388 389 amr->amr_mbox_paddr = amr->amr_dmamap->dm_segs[0].ds_addr; 390 amr->amr_sgls_paddr = (amr->amr_mbox_paddr + 0x1fff) & ~0x1fff; 391 amr->amr_sgls = (struct amr_sgentry *)((caddr_t)amr->amr_mbox + 392 amr->amr_sgls_paddr - amr->amr_dmamap->dm_segs[0].ds_addr); 393 394 /* 395 * Allocate and initalise the command control blocks. 396 */ 397 ac = malloc(sizeof(*ac) * AMR_MAX_CMDS, M_DEVBUF, M_NOWAIT | M_ZERO); 398 amr->amr_ccbs = ac; 399 SLIST_INIT(&amr->amr_ccb_freelist); 400 TAILQ_INIT(&amr->amr_ccb_active); 401 amr->amr_flags |= AMRF_CCBS; 402 403 if (amr_max_xfer == 0) { 404 amr_max_xfer = min(((AMR_MAX_SEGS - 1) * PAGE_SIZE), MAXPHYS); 405 amr_max_segs = (amr_max_xfer + (PAGE_SIZE * 2) - 1) / PAGE_SIZE; 406 } 407 408 for (i = 0; i < AMR_MAX_CMDS; i++, ac++) { 409 rv = bus_dmamap_create(amr->amr_dmat, amr_max_xfer, 410 amr_max_segs, amr_max_xfer, 0, 411 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ac->ac_xfer_map); 412 if (rv != 0) 413 break; 414 415 ac->ac_ident = i; 416 amr_ccb_free(amr, ac); 417 } 418 if (i != AMR_MAX_CMDS) { 419 aprint_error("%s: memory exhausted\n", amr->amr_dv.dv_xname); 420 amr_teardown(amr); 421 return; 422 } 423 424 /* 425 * Take care of model-specific tasks. 426 */ 427 if ((apt->apt_flags & AT_QUARTZ) != 0) { 428 amr->amr_submit = amr_quartz_submit; 429 amr->amr_get_work = amr_quartz_get_work; 430 } else { 431 amr->amr_submit = amr_std_submit; 432 amr->amr_get_work = amr_std_get_work; 433 434 /* Notify the controller of the mailbox location. */ 435 amr_outl(amr, AMR_SREG_MBOX, (u_int32_t)amr->amr_mbox_paddr + 16); 436 amr_outb(amr, AMR_SREG_MBOX_ENABLE, AMR_SMBOX_ENABLE_ADDR); 437 438 /* Clear outstanding interrupts and enable interrupts. */ 439 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 440 amr_outb(amr, AMR_SREG_TOGL, 441 amr_inb(amr, AMR_SREG_TOGL) | AMR_STOGL_ENABLE); 442 } 443 444 /* 445 * Retrieve parameters, and tell the world about us. 446 */ 447 amr->amr_enqbuf = malloc(AMR_ENQUIRY_BUFSIZE, M_DEVBUF, M_NOWAIT); 448 amr->amr_flags |= AMRF_ENQBUF; 449 amr->amr_maxqueuecnt = i; 450 aprint_normal(": AMI RAID "); 451 if (amr_init(amr, intrstr, pa) != 0) { 452 amr_teardown(amr); 453 return; 454 } 455 456 /* 457 * Cap the maximum number of outstanding commands. AMI's Linux 458 * driver doesn't trust the controller's reported value, and lockups 459 * have been seen when we do. 460 */ 461 amr->amr_maxqueuecnt = min(amr->amr_maxqueuecnt, AMR_MAX_CMDS); 462 if (amr->amr_maxqueuecnt > i) 463 amr->amr_maxqueuecnt = i; 464 465 /* Set our `shutdownhook' before we start any device activity. */ 466 if (amr_sdh == NULL) 467 amr_sdh = shutdownhook_establish(amr_shutdown, NULL); 468 469 /* Attach sub-devices. */ 470 for (j = 0; j < amr->amr_numdrives; j++) { 471 if (amr->amr_drive[j].al_size == 0) 472 continue; 473 amra.amra_unit = j; 474 amr->amr_drive[j].al_dv = config_found_sm(&amr->amr_dv, &amra, 475 amr_print, amr_submatch); 476 } 477 478 SIMPLEQ_INIT(&amr->amr_ccb_queue); 479 480 /* XXX This doesn't work for newer boards yet. */ 481 if ((apt->apt_flags & AT_QUARTZ) == 0) 482 kthread_create(amr_thread_create, amr); 483 } 484 485 /* 486 * Free up resources. 487 */ 488 void 489 amr_teardown(struct amr_softc *amr) 490 { 491 struct amr_ccb *ac; 492 int fl; 493 494 fl = amr->amr_flags; 495 496 if ((fl & AMRF_THREAD) != 0) { 497 amr->amr_flags |= AMRF_THREAD_EXIT; 498 wakeup(amr_thread); 499 while ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) 500 tsleep(&amr->amr_flags, PWAIT, "amrexit", 0); 501 } 502 if ((fl & AMRF_CCBS) != 0) { 503 SLIST_FOREACH(ac, &amr->amr_ccb_freelist, ac_chain.slist) { 504 bus_dmamap_destroy(amr->amr_dmat, ac->ac_xfer_map); 505 } 506 free(amr->amr_ccbs, M_DEVBUF); 507 } 508 if ((fl & AMRF_ENQBUF) != 0) 509 free(amr->amr_enqbuf, M_DEVBUF); 510 if ((fl & AMRF_DMA_LOAD) != 0) 511 bus_dmamap_unload(amr->amr_dmat, amr->amr_dmamap); 512 if ((fl & AMRF_DMA_MAP) != 0) 513 bus_dmamem_unmap(amr->amr_dmat, (caddr_t)amr->amr_mbox, 514 amr->amr_dmasize); 515 if ((fl & AMRF_DMA_ALLOC) != 0) 516 bus_dmamem_free(amr->amr_dmat, &amr->amr_dmaseg, 1); 517 if ((fl & AMRF_DMA_CREATE) != 0) 518 bus_dmamap_destroy(amr->amr_dmat, amr->amr_dmamap); 519 if ((fl & AMRF_PCI_INTR) != 0) 520 pci_intr_disestablish(amr->amr_pc, amr->amr_ih); 521 if ((fl & AMRF_PCI_REGS) != 0) 522 bus_space_unmap(amr->amr_iot, amr->amr_ioh, amr->amr_ios); 523 } 524 525 /* 526 * Print autoconfiguration message for a sub-device. 527 */ 528 int 529 amr_print(void *aux, const char *pnp) 530 { 531 struct amr_attach_args *amra; 532 533 amra = (struct amr_attach_args *)aux; 534 535 if (pnp != NULL) 536 aprint_normal("block device at %s", pnp); 537 aprint_normal(" unit %d", amra->amra_unit); 538 return (UNCONF); 539 } 540 541 /* 542 * Match a sub-device. 543 */ 544 int 545 amr_submatch(struct device *parent, struct cfdata *cf, void *aux) 546 { 547 struct amr_attach_args *amra; 548 549 amra = (struct amr_attach_args *)aux; 550 551 if (cf->amracf_unit != AMRCF_UNIT_DEFAULT && 552 cf->amracf_unit != amra->amra_unit) 553 return (0); 554 555 return (config_match(parent, cf, aux)); 556 } 557 558 /* 559 * Retrieve operational parameters and describe the controller. 560 */ 561 int 562 amr_init(struct amr_softc *amr, const char *intrstr, 563 struct pci_attach_args *pa) 564 { 565 struct amr_adapter_info *aa; 566 struct amr_prodinfo *ap; 567 struct amr_enquiry *ae; 568 struct amr_enquiry3 *aex; 569 const char *prodstr; 570 u_int i, sig, ishp; 571 char buf[64]; 572 573 /* 574 * Try to get 40LD product info, which tells us what the card is 575 * labelled as. 576 */ 577 ap = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_PRODUCT_INFO, 0, 578 amr->amr_enqbuf); 579 if (ap != NULL) { 580 aprint_normal("<%.80s>\n", ap->ap_product); 581 if (intrstr != NULL) 582 aprint_normal("%s: interrupting at %s\n", 583 amr->amr_dv.dv_xname, intrstr); 584 aprint_normal("%s: firmware %.16s, BIOS %.16s, %dMB RAM\n", 585 amr->amr_dv.dv_xname, ap->ap_firmware, ap->ap_bios, 586 le16toh(ap->ap_memsize)); 587 588 amr->amr_maxqueuecnt = ap->ap_maxio; 589 590 /* 591 * Fetch and record state of logical drives. 592 */ 593 aex = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_ENQ3, 594 AMR_CONFIG_ENQ3_SOLICITED_FULL, amr->amr_enqbuf); 595 if (aex == NULL) { 596 aprint_error("%s ENQUIRY3 failed\n", 597 amr->amr_dv.dv_xname); 598 return (-1); 599 } 600 601 if (aex->ae_numldrives > AMR_MAX_UNITS) { 602 aprint_error( 603 "%s: adjust AMR_MAX_UNITS to %d (currently %d)" 604 "\n", amr->amr_dv.dv_xname, 605 ae->ae_ldrv.al_numdrives, AMR_MAX_UNITS); 606 amr->amr_numdrives = AMR_MAX_UNITS; 607 } else 608 amr->amr_numdrives = aex->ae_numldrives; 609 610 for (i = 0; i < amr->amr_numdrives; i++) { 611 amr->amr_drive[i].al_size = 612 le32toh(aex->ae_drivesize[i]); 613 amr->amr_drive[i].al_state = aex->ae_drivestate[i]; 614 amr->amr_drive[i].al_properties = aex->ae_driveprop[i]; 615 } 616 617 return (0); 618 } 619 620 /* 621 * Try 8LD extended ENQUIRY to get the controller signature. Once 622 * found, search for a product description. 623 */ 624 ae = amr_enquire(amr, AMR_CMD_EXT_ENQUIRY2, 0, 0, amr->amr_enqbuf); 625 if (ae != NULL) { 626 i = 0; 627 sig = le32toh(ae->ae_signature); 628 629 while (i < sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 630 if (amr_typestr[i].at_sig == sig) 631 break; 632 i++; 633 } 634 if (i == sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 635 sprintf(buf, "unknown ENQUIRY2 sig (0x%08x)", sig); 636 prodstr = buf; 637 } else 638 prodstr = amr_typestr[i].at_str; 639 } else { 640 ae = amr_enquire(amr, AMR_CMD_ENQUIRY, 0, 0, amr->amr_enqbuf); 641 if (ae == NULL) { 642 aprint_error("%s: unsupported controller\n", 643 amr->amr_dv.dv_xname); 644 return (-1); 645 } 646 647 switch (PCI_PRODUCT(pa->pa_id)) { 648 case PCI_PRODUCT_AMI_MEGARAID: 649 prodstr = "Series 428"; 650 break; 651 case PCI_PRODUCT_AMI_MEGARAID2: 652 prodstr = "Series 434"; 653 break; 654 default: 655 sprintf(buf, "unknown PCI dev (0x%04x)", 656 PCI_PRODUCT(pa->pa_id)); 657 prodstr = buf; 658 break; 659 } 660 } 661 662 /* 663 * HP NetRaid controllers have a special encoding of the firmware 664 * and BIOS versions. The AMI version seems to have it as strings 665 * whereas the HP version does it with a leading uppercase character 666 * and two binary numbers. 667 */ 668 aa = &ae->ae_adapter; 669 670 if (aa->aa_firmware[2] >= 'A' && aa->aa_firmware[2] <= 'Z' && 671 aa->aa_firmware[1] < ' ' && aa->aa_firmware[0] < ' ' && 672 aa->aa_bios[2] >= 'A' && aa->aa_bios[2] <= 'Z' && 673 aa->aa_bios[1] < ' ' && aa->aa_bios[0] < ' ') { 674 if (le32toh(ae->ae_signature) == AMR_SIG_438) { 675 /* The AMI 438 is a NetRaid 3si in HP-land. */ 676 prodstr = "HP NetRaid 3si"; 677 } 678 ishp = 1; 679 } else 680 ishp = 0; 681 682 aprint_normal("<%s>\n", prodstr); 683 if (intrstr != NULL) 684 aprint_normal("%s: interrupting at %s\n", amr->amr_dv.dv_xname, 685 intrstr); 686 687 if (ishp) 688 aprint_normal("%s: firmware <%c.%02d.%02d>, BIOS <%c.%02d.%02d>" 689 ", %dMB RAM\n", amr->amr_dv.dv_xname, aa->aa_firmware[2], 690 aa->aa_firmware[1], aa->aa_firmware[0], aa->aa_bios[2], 691 aa->aa_bios[1], aa->aa_bios[0], aa->aa_memorysize); 692 else 693 aprint_normal("%s: firmware <%.4s>, BIOS <%.4s>, %dMB RAM\n", 694 amr->amr_dv.dv_xname, aa->aa_firmware, aa->aa_bios, 695 aa->aa_memorysize); 696 697 amr->amr_maxqueuecnt = aa->aa_maxio; 698 699 /* 700 * Record state of logical drives. 701 */ 702 if (ae->ae_ldrv.al_numdrives > AMR_MAX_UNITS) { 703 aprint_error("%s: adjust AMR_MAX_UNITS to %d (currently %d)\n", 704 amr->amr_dv.dv_xname, ae->ae_ldrv.al_numdrives, 705 AMR_MAX_UNITS); 706 amr->amr_numdrives = AMR_MAX_UNITS; 707 } else 708 amr->amr_numdrives = ae->ae_ldrv.al_numdrives; 709 710 for (i = 0; i < AMR_MAX_UNITS; i++) { 711 amr->amr_drive[i].al_size = le32toh(ae->ae_ldrv.al_size[i]); 712 amr->amr_drive[i].al_state = ae->ae_ldrv.al_state[i]; 713 amr->amr_drive[i].al_properties = ae->ae_ldrv.al_properties[i]; 714 } 715 716 return (0); 717 } 718 719 /* 720 * Flush the internal cache on each configured controller. Called at 721 * shutdown time. 722 */ 723 void 724 amr_shutdown(void *cookie) 725 { 726 extern struct cfdriver amr_cd; 727 struct amr_softc *amr; 728 struct amr_ccb *ac; 729 int i, rv, s; 730 731 for (i = 0; i < amr_cd.cd_ndevs; i++) { 732 if ((amr = device_lookup(&amr_cd, i)) == NULL) 733 continue; 734 735 if ((rv = amr_ccb_alloc(amr, &ac)) == 0) { 736 ac->ac_cmd.mb_command = AMR_CMD_FLUSH; 737 s = splbio(); 738 rv = amr_ccb_poll(amr, ac, 30000); 739 splx(s); 740 amr_ccb_free(amr, ac); 741 } 742 if (rv != 0) 743 printf("%s: unable to flush cache (%d)\n", 744 amr->amr_dv.dv_xname, rv); 745 } 746 } 747 748 /* 749 * Interrupt service routine. 750 */ 751 int 752 amr_intr(void *cookie) 753 { 754 struct amr_softc *amr; 755 struct amr_ccb *ac; 756 struct amr_mailbox_resp mbox; 757 u_int i, forus, idx; 758 759 amr = cookie; 760 forus = 0; 761 762 while ((*amr->amr_get_work)(amr, &mbox) == 0) { 763 /* Iterate over completed commands in this result. */ 764 for (i = 0; i < mbox.mb_nstatus; i++) { 765 idx = mbox.mb_completed[i] - 1; 766 ac = amr->amr_ccbs + idx; 767 768 if (idx >= amr->amr_maxqueuecnt) { 769 printf("%s: bad status (bogus ID: %u=%u)\n", 770 amr->amr_dv.dv_xname, i, idx); 771 continue; 772 } 773 774 if ((ac->ac_flags & AC_ACTIVE) == 0) { 775 printf("%s: bad status (not active; 0x04%x)\n", 776 amr->amr_dv.dv_xname, ac->ac_flags); 777 continue; 778 } 779 780 ac->ac_status = mbox.mb_status; 781 ac->ac_flags = (ac->ac_flags & ~AC_ACTIVE) | 782 AC_COMPLETE; 783 TAILQ_REMOVE(&amr->amr_ccb_active, ac, ac_chain.tailq); 784 785 if ((ac->ac_flags & AC_MOAN) != 0) 786 printf("%s: ccb %d completed\n", 787 amr->amr_dv.dv_xname, ac->ac_ident); 788 789 /* Pass notification to upper layers. */ 790 if (ac->ac_handler != NULL) 791 (*ac->ac_handler)(ac); 792 else 793 wakeup(ac); 794 } 795 forus = 1; 796 } 797 798 if (forus) 799 amr_ccb_enqueue(amr, NULL); 800 801 return (forus); 802 } 803 804 /* 805 * Create the watchdog thread. 806 */ 807 void 808 amr_thread_create(void *cookie) 809 { 810 struct amr_softc *amr; 811 int rv; 812 813 amr = cookie; 814 815 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 816 amr->amr_flags ^= AMRF_THREAD_EXIT; 817 wakeup(&amr->amr_flags); 818 return; 819 } 820 821 rv = kthread_create1(amr_thread, amr, &amr->amr_thread, "%s", 822 amr->amr_dv.dv_xname); 823 if (rv != 0) 824 aprint_error("%s: unable to create thread (%d)", 825 amr->amr_dv.dv_xname, rv); 826 else 827 amr->amr_flags |= AMRF_THREAD; 828 } 829 830 /* 831 * Watchdog thread. 832 */ 833 void 834 amr_thread(void *cookie) 835 { 836 struct amr_softc *amr; 837 struct amr_ccb *ac; 838 struct amr_logdrive *al; 839 struct amr_enquiry *ae; 840 time_t curtime; 841 int rv, i, s; 842 843 amr = cookie; 844 ae = amr->amr_enqbuf; 845 846 for (;;) { 847 tsleep(amr_thread, PWAIT, "amrwdog", AMR_WDOG_TICKS); 848 849 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 850 amr->amr_flags ^= AMRF_THREAD_EXIT; 851 wakeup(&amr->amr_flags); 852 kthread_exit(0); 853 } 854 855 s = splbio(); 856 amr_intr(cookie); 857 curtime = (time_t)mono_time.tv_sec; 858 ac = TAILQ_FIRST(&amr->amr_ccb_active); 859 while (ac != NULL) { 860 if (ac->ac_start_time + AMR_TIMEOUT > curtime) 861 break; 862 if ((ac->ac_flags & AC_MOAN) == 0) { 863 printf("%s: ccb %d timed out; mailbox:\n", 864 amr->amr_dv.dv_xname, ac->ac_ident); 865 amr_ccb_dump(amr, ac); 866 ac->ac_flags |= AC_MOAN; 867 } 868 ac = TAILQ_NEXT(ac, ac_chain.tailq); 869 } 870 splx(s); 871 872 if ((rv = amr_ccb_alloc(amr, &ac)) != 0) { 873 printf("%s: ccb_alloc failed (%d)\n", 874 amr->amr_dv.dv_xname, rv); 875 continue; 876 } 877 878 ac->ac_cmd.mb_command = AMR_CMD_ENQUIRY; 879 880 rv = amr_ccb_map(amr, ac, amr->amr_enqbuf, 881 AMR_ENQUIRY_BUFSIZE, 0); 882 if (rv != 0) { 883 printf("%s: ccb_map failed (%d)\n", 884 amr->amr_dv.dv_xname, rv); 885 amr_ccb_free(amr, ac); 886 continue; 887 } 888 889 rv = amr_ccb_wait(amr, ac); 890 amr_ccb_unmap(amr, ac); 891 if (rv != 0) { 892 printf("%s: enquiry failed (st=%d)\n", 893 amr->amr_dv.dv_xname, ac->ac_status); 894 continue; 895 } 896 amr_ccb_free(amr, ac); 897 898 al = amr->amr_drive; 899 for (i = 0; i < AMR_MAX_UNITS; i++, al++) { 900 if (al->al_dv == NULL) 901 continue; 902 if (al->al_state == ae->ae_ldrv.al_state[i]) 903 continue; 904 905 printf("%s: state changed: %s -> %s\n", 906 al->al_dv->dv_xname, 907 amr_drive_state(al->al_state, NULL), 908 amr_drive_state(ae->ae_ldrv.al_state[i], NULL)); 909 910 al->al_state = ae->ae_ldrv.al_state[i]; 911 } 912 } 913 } 914 915 /* 916 * Return a text description of a logical drive's current state. 917 */ 918 const char * 919 amr_drive_state(int state, int *happy) 920 { 921 const char *str; 922 923 state = AMR_DRV_CURSTATE(state); 924 if (state >= sizeof(amr_dstate) / sizeof(amr_dstate[0])) { 925 if (happy) 926 *happy = 1; 927 str = "status unknown"; 928 } else { 929 if (happy) 930 *happy = amr_dstate[state].ds_happy; 931 str = amr_dstate[state].ds_descr; 932 } 933 934 return (str); 935 } 936 937 /* 938 * Run a generic enquiry-style command. 939 */ 940 void * 941 amr_enquire(struct amr_softc *amr, u_int8_t cmd, u_int8_t cmdsub, 942 u_int8_t cmdqual, void *buf) 943 { 944 struct amr_ccb *ac; 945 u_int8_t *mb; 946 int rv; 947 948 if (amr_ccb_alloc(amr, &ac) != 0) 949 return (NULL); 950 951 /* Build the command proper. */ 952 mb = (u_int8_t *)&ac->ac_cmd; 953 mb[0] = cmd; 954 mb[2] = cmdsub; 955 mb[3] = cmdqual; 956 957 rv = amr_ccb_map(amr, ac, buf, AMR_ENQUIRY_BUFSIZE, 0); 958 if (rv == 0) { 959 rv = amr_ccb_poll(amr, ac, 2000); 960 amr_ccb_unmap(amr, ac); 961 } 962 amr_ccb_free(amr, ac); 963 964 return (rv ? NULL : buf); 965 } 966 967 /* 968 * Allocate and initialise a CCB. 969 */ 970 int 971 amr_ccb_alloc(struct amr_softc *amr, struct amr_ccb **acp) 972 { 973 int s; 974 975 s = splbio(); 976 if ((*acp = SLIST_FIRST(&amr->amr_ccb_freelist)) == NULL) { 977 splx(s); 978 return (EAGAIN); 979 } 980 SLIST_REMOVE_HEAD(&amr->amr_ccb_freelist, ac_chain.slist); 981 splx(s); 982 983 return (0); 984 } 985 986 /* 987 * Free a CCB. 988 */ 989 void 990 amr_ccb_free(struct amr_softc *amr, struct amr_ccb *ac) 991 { 992 int s; 993 994 memset(&ac->ac_cmd, 0, sizeof(ac->ac_cmd)); 995 ac->ac_cmd.mb_ident = ac->ac_ident + 1; 996 ac->ac_cmd.mb_busy = 1; 997 ac->ac_handler = NULL; 998 ac->ac_flags = 0; 999 1000 s = splbio(); 1001 SLIST_INSERT_HEAD(&amr->amr_ccb_freelist, ac, ac_chain.slist); 1002 splx(s); 1003 } 1004 1005 /* 1006 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 1007 * the order that they were enqueued and try to submit their command blocks 1008 * to the controller for execution. 1009 */ 1010 void 1011 amr_ccb_enqueue(struct amr_softc *amr, struct amr_ccb *ac) 1012 { 1013 int s; 1014 1015 s = splbio(); 1016 1017 if (ac != NULL) 1018 SIMPLEQ_INSERT_TAIL(&amr->amr_ccb_queue, ac, ac_chain.simpleq); 1019 1020 while ((ac = SIMPLEQ_FIRST(&amr->amr_ccb_queue)) != NULL) { 1021 if ((*amr->amr_submit)(amr, ac) != 0) 1022 break; 1023 SIMPLEQ_REMOVE_HEAD(&amr->amr_ccb_queue, ac_chain.simpleq); 1024 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1025 } 1026 1027 splx(s); 1028 } 1029 1030 /* 1031 * Map the specified CCB's data buffer onto the bus, and fill the 1032 * scatter-gather list. 1033 */ 1034 int 1035 amr_ccb_map(struct amr_softc *amr, struct amr_ccb *ac, void *data, int size, 1036 int out) 1037 { 1038 struct amr_sgentry *sge; 1039 struct amr_mailbox_cmd *mb; 1040 int nsegs, i, rv, sgloff; 1041 bus_dmamap_t xfer; 1042 1043 xfer = ac->ac_xfer_map; 1044 1045 rv = bus_dmamap_load(amr->amr_dmat, xfer, data, size, NULL, 1046 BUS_DMA_NOWAIT); 1047 if (rv != 0) 1048 return (rv); 1049 1050 mb = &ac->ac_cmd; 1051 ac->ac_xfer_size = size; 1052 ac->ac_flags |= (out ? AC_XFER_OUT : AC_XFER_IN); 1053 sgloff = AMR_SGL_SIZE * ac->ac_ident; 1054 1055 /* We don't need to use a scatter/gather list for just 1 segment. */ 1056 nsegs = xfer->dm_nsegs; 1057 if (nsegs == 1) { 1058 mb->mb_nsgelem = 0; 1059 mb->mb_physaddr = htole32(xfer->dm_segs[0].ds_addr); 1060 ac->ac_flags |= AC_NOSGL; 1061 } else { 1062 mb->mb_nsgelem = nsegs; 1063 mb->mb_physaddr = htole32(amr->amr_sgls_paddr + sgloff); 1064 1065 sge = (struct amr_sgentry *)((caddr_t)amr->amr_sgls + sgloff); 1066 for (i = 0; i < nsegs; i++, sge++) { 1067 sge->sge_addr = htole32(xfer->dm_segs[i].ds_addr); 1068 sge->sge_count = htole32(xfer->dm_segs[i].ds_len); 1069 } 1070 } 1071 1072 bus_dmamap_sync(amr->amr_dmat, xfer, 0, ac->ac_xfer_size, 1073 out ? BUS_DMASYNC_PREWRITE : BUS_DMASYNC_PREREAD); 1074 1075 if ((ac->ac_flags & AC_NOSGL) == 0) 1076 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, sgloff, 1077 AMR_SGL_SIZE, BUS_DMASYNC_PREWRITE); 1078 1079 return (0); 1080 } 1081 1082 /* 1083 * Unmap the specified CCB's data buffer. 1084 */ 1085 void 1086 amr_ccb_unmap(struct amr_softc *amr, struct amr_ccb *ac) 1087 { 1088 1089 if ((ac->ac_flags & AC_NOSGL) == 0) 1090 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 1091 AMR_SGL_SIZE * ac->ac_ident, AMR_SGL_SIZE, 1092 BUS_DMASYNC_POSTWRITE); 1093 bus_dmamap_sync(amr->amr_dmat, ac->ac_xfer_map, 0, ac->ac_xfer_size, 1094 (ac->ac_flags & AC_XFER_IN) != 0 ? 1095 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1096 bus_dmamap_unload(amr->amr_dmat, ac->ac_xfer_map); 1097 } 1098 1099 /* 1100 * Submit a command to the controller and poll on completion. Return 1101 * non-zero on timeout or error. Must be called with interrupts blocked. 1102 */ 1103 int 1104 amr_ccb_poll(struct amr_softc *amr, struct amr_ccb *ac, int timo) 1105 { 1106 int rv; 1107 1108 if ((rv = (*amr->amr_submit)(amr, ac)) != 0) 1109 return (rv); 1110 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1111 1112 for (timo *= 10; timo != 0; timo--) { 1113 amr_intr(amr); 1114 if ((ac->ac_flags & AC_COMPLETE) != 0) 1115 break; 1116 DELAY(100); 1117 } 1118 1119 return (timo == 0 || ac->ac_status != 0 ? EIO : 0); 1120 } 1121 1122 /* 1123 * Submit a command to the controller and sleep on completion. Return 1124 * non-zero on error. 1125 */ 1126 int 1127 amr_ccb_wait(struct amr_softc *amr, struct amr_ccb *ac) 1128 { 1129 int s; 1130 1131 s = splbio(); 1132 amr_ccb_enqueue(amr, ac); 1133 tsleep(ac, PRIBIO, "amrcmd", 0); 1134 splx(s); 1135 1136 return (ac->ac_status != 0 ? EIO : 0); 1137 } 1138 1139 /* 1140 * Wait for the mailbox to become available. 1141 */ 1142 int 1143 amr_mbox_wait(struct amr_softc *amr) 1144 { 1145 int timo; 1146 1147 for (timo = 10000; timo != 0; timo--) { 1148 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1149 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1150 if (amr->amr_mbox->mb_cmd.mb_busy == 0) 1151 break; 1152 DELAY(100); 1153 } 1154 1155 if (timo == 0) 1156 printf("%s: controller wedged\n", amr->amr_dv.dv_xname); 1157 1158 return (timo != 0 ? 0 : EAGAIN); 1159 } 1160 1161 /* 1162 * Tell the controller that the mailbox contains a valid command. Must be 1163 * called with interrupts blocked. 1164 */ 1165 int 1166 amr_quartz_submit(struct amr_softc *amr, struct amr_ccb *ac) 1167 { 1168 u_int32_t v; 1169 1170 amr->amr_mbox->mb_poll = 0; 1171 amr->amr_mbox->mb_ack = 0; 1172 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1173 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1174 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1175 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1176 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1177 return (EAGAIN); 1178 1179 v = amr_inl(amr, AMR_QREG_IDB); 1180 if ((v & AMR_QIDB_SUBMIT) != 0) { 1181 amr->amr_mbox->mb_cmd.mb_busy = 0; 1182 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1183 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1184 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1185 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1186 return (EAGAIN); 1187 } 1188 1189 amr->amr_mbox->mb_segment = 0; 1190 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1191 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1192 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1193 1194 ac->ac_start_time = (time_t)mono_time.tv_sec; 1195 ac->ac_flags |= AC_ACTIVE; 1196 amr_outl(amr, AMR_QREG_IDB, 1197 (amr->amr_mbox_paddr + 16) | AMR_QIDB_SUBMIT); 1198 return (0); 1199 } 1200 1201 int 1202 amr_std_submit(struct amr_softc *amr, struct amr_ccb *ac) 1203 { 1204 1205 amr->amr_mbox->mb_poll = 0; 1206 amr->amr_mbox->mb_ack = 0; 1207 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1208 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1209 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1210 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1211 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1212 return (EAGAIN); 1213 1214 if ((amr_inb(amr, AMR_SREG_MBOX_BUSY) & AMR_SMBOX_BUSY_FLAG) != 0) { 1215 amr->amr_mbox->mb_cmd.mb_busy = 0; 1216 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1217 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1218 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1219 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1220 return (EAGAIN); 1221 } 1222 1223 amr->amr_mbox->mb_segment = 0; 1224 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1225 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1226 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1227 1228 ac->ac_start_time = (time_t)mono_time.tv_sec; 1229 ac->ac_flags |= AC_ACTIVE; 1230 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_POST); 1231 return (0); 1232 } 1233 1234 /* 1235 * Claim any work that the controller has completed; acknowledge completion, 1236 * save details of the completion in (mbsave). Must be called with 1237 * interrupts blocked. 1238 */ 1239 int 1240 amr_quartz_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1241 { 1242 1243 /* Work waiting for us? */ 1244 if (amr_inl(amr, AMR_QREG_ODB) != AMR_QODB_READY) 1245 return (-1); 1246 1247 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1248 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1249 1250 /* Save the mailbox, which contains a list of completed commands. */ 1251 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1252 1253 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1254 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1255 1256 /* Ack the interrupt and mailbox transfer. */ 1257 amr_outl(amr, AMR_QREG_ODB, AMR_QODB_READY); 1258 amr_outl(amr, AMR_QREG_IDB, (amr->amr_mbox_paddr+16) | AMR_QIDB_ACK); 1259 1260 /* 1261 * This waits for the controller to notice that we've taken the 1262 * command from it. It's very inefficient, and we shouldn't do it, 1263 * but if we remove this code, we stop completing commands under 1264 * load. 1265 * 1266 * Peter J says we shouldn't do this. The documentation says we 1267 * should. Who is right? 1268 */ 1269 while ((amr_inl(amr, AMR_QREG_IDB) & AMR_QIDB_ACK) != 0) 1270 DELAY(10); 1271 1272 return (0); 1273 } 1274 1275 int 1276 amr_std_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1277 { 1278 u_int8_t istat; 1279 1280 /* Check for valid interrupt status. */ 1281 if (((istat = amr_inb(amr, AMR_SREG_INTR)) & AMR_SINTR_VALID) == 0) 1282 return (-1); 1283 1284 /* Ack the interrupt. */ 1285 amr_outb(amr, AMR_SREG_INTR, istat); 1286 1287 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1288 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1289 1290 /* Save mailbox, which contains a list of completed commands. */ 1291 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1292 1293 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1294 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1295 1296 /* Ack mailbox transfer. */ 1297 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 1298 1299 return (0); 1300 } 1301 1302 void 1303 amr_ccb_dump(struct amr_softc *amr, struct amr_ccb *ac) 1304 { 1305 int i; 1306 1307 printf("%s: ", amr->amr_dv.dv_xname); 1308 for (i = 0; i < 4; i++) 1309 printf("%08x ", ((u_int32_t *)&ac->ac_cmd)[i]); 1310 printf("\n"); 1311 } 1312
Indexes created Mon Sep 22 05:09:51 GMT 2025