amr.c revision 1.16
1 /* $NetBSD: amr.c,v 1.16 2003/10/25 18:31:11 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999,2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: amr_pci.c,v 1.5 2000/08/30 07:52:40 msmith Exp 66 * from FreeBSD: amr.c,v 1.16 2000/08/30 07:52:40 msmith Exp 67 */ 68 69 /* 70 * Driver for AMI RAID controllers. 71 */ 72 73 #include <sys/cdefs.h> 74 __KERNEL_RCSID(0, "$NetBSD: amr.c,v 1.16 2003/10/25 18:31:11 christos Exp $"); 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/device.h> 80 #include <sys/queue.h> 81 #include <sys/proc.h> 82 #include <sys/buf.h> 83 #include <sys/malloc.h> 84 #include <sys/kthread.h> 85 86 #include <uvm/uvm_extern.h> 87 88 #include <machine/endian.h> 89 #include <machine/bus.h> 90 91 #include <dev/pci/pcidevs.h> 92 #include <dev/pci/pcivar.h> 93 #include <dev/pci/amrreg.h> 94 #include <dev/pci/amrvar.h> 95 96 void amr_attach(struct device *, struct device *, void *); 97 void amr_ccb_dump(struct amr_softc *, struct amr_ccb *); 98 void *amr_enquire(struct amr_softc *, u_int8_t, u_int8_t, u_int8_t, void *); 99 int amr_init(struct amr_softc *, const char *, 100 struct pci_attach_args *pa); 101 int amr_intr(void *); 102 int amr_match(struct device *, struct cfdata *, void *); 103 int amr_print(void *, const char *); 104 void amr_shutdown(void *); 105 int amr_submatch(struct device *, struct cfdata *, void *); 106 void amr_teardown(struct amr_softc *); 107 void amr_thread(void *); 108 void amr_thread_create(void *); 109 110 int amr_mbox_wait(struct amr_softc *); 111 int amr_quartz_get_work(struct amr_softc *, struct amr_mailbox_resp *); 112 int amr_quartz_submit(struct amr_softc *, struct amr_ccb *); 113 int amr_std_get_work(struct amr_softc *, struct amr_mailbox_resp *); 114 int amr_std_submit(struct amr_softc *, struct amr_ccb *); 115 116 static inline u_int8_t amr_inb(struct amr_softc *, int); 117 static inline u_int32_t amr_inl(struct amr_softc *, int); 118 static inline void amr_outb(struct amr_softc *, int, u_int8_t); 119 static inline void amr_outl(struct amr_softc *, int, u_int32_t); 120 121 CFATTACH_DECL(amr, sizeof(struct amr_softc), 122 amr_match, amr_attach, NULL, NULL); 123 124 #define AT_QUARTZ 0x01 /* `Quartz' chipset */ 125 #define AT_SIG 0x02 /* Check for signature */ 126 127 struct amr_pci_type { 128 u_short apt_vendor; 129 u_short apt_product; 130 u_short apt_flags; 131 } const amr_pci_type[] = { 132 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID, 0 }, 133 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID2, 0 }, 134 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ | AT_SIG }, 136 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI, AT_QUARTZ }, 137 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI_2, AT_QUARTZ }, 138 }; 139 140 struct amr_typestr { 141 const char *at_str; 142 int at_sig; 143 } const amr_typestr[] = { 144 { "Series 431", AMR_SIG_431 }, 145 { "Series 438", AMR_SIG_438 }, 146 { "Series 466", AMR_SIG_466 }, 147 { "Series 467", AMR_SIG_467 }, 148 { "Series 490", AMR_SIG_490 }, 149 { "Series 762", AMR_SIG_762 }, 150 { "HP NetRAID (T5)", AMR_SIG_T5 }, 151 { "HP NetRAID (T7)", AMR_SIG_T7 }, 152 }; 153 154 struct { 155 const char *ds_descr; 156 int ds_happy; 157 } const amr_dstate[] = { 158 { "offline", 0 }, 159 { "degraded", 1 }, 160 { "optimal", 1 }, 161 { "online", 1 }, 162 { "failed", 0 }, 163 { "rebuilding", 1 }, 164 { "hotspare", 0 }, 165 }; 166 167 void *amr_sdh; 168 int amr_max_segs; 169 int amr_max_xfer; 170 171 static inline u_int8_t 172 amr_inb(struct amr_softc *amr, int off) 173 { 174 175 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 176 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 177 return (bus_space_read_1(amr->amr_iot, amr->amr_ioh, off)); 178 } 179 180 static inline u_int32_t 181 amr_inl(struct amr_softc *amr, int off) 182 { 183 184 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 185 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 186 return (bus_space_read_4(amr->amr_iot, amr->amr_ioh, off)); 187 } 188 189 static inline void 190 amr_outb(struct amr_softc *amr, int off, u_int8_t val) 191 { 192 193 bus_space_write_1(amr->amr_iot, amr->amr_ioh, off, val); 194 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 195 BUS_SPACE_BARRIER_WRITE); 196 } 197 198 static inline void 199 amr_outl(struct amr_softc *amr, int off, u_int32_t val) 200 { 201 202 bus_space_write_4(amr->amr_iot, amr->amr_ioh, off, val); 203 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 204 BUS_SPACE_BARRIER_WRITE); 205 } 206 207 /* 208 * Match a supported device. 209 */ 210 int 211 amr_match(struct device *parent, struct cfdata *match, void *aux) 212 { 213 struct pci_attach_args *pa; 214 pcireg_t s; 215 int i; 216 217 pa = (struct pci_attach_args *)aux; 218 219 /* 220 * Don't match the device if it's operating in I2O mode. In this 221 * case it should be handled by the `iop' driver. 222 */ 223 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 224 return (0); 225 226 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 227 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 228 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 229 break; 230 231 if (i == sizeof(amr_pci_type) / sizeof(amr_pci_type[0])) 232 return (0); 233 234 if ((amr_pci_type[i].apt_flags & AT_SIG) == 0) 235 return (1); 236 237 s = pci_conf_read(pa->pa_pc, pa->pa_tag, AMR_QUARTZ_SIG_REG) & 0xffff; 238 return (s == AMR_QUARTZ_SIG0 || s == AMR_QUARTZ_SIG1); 239 } 240 241 /* 242 * Attach a supported device. 243 */ 244 void 245 amr_attach(struct device *parent, struct device *self, void *aux) 246 { 247 bus_space_tag_t memt, iot; 248 bus_space_handle_t memh, ioh; 249 struct pci_attach_args *pa; 250 struct amr_attach_args amra; 251 const struct amr_pci_type *apt; 252 struct amr_softc *amr; 253 pci_chipset_tag_t pc; 254 pci_intr_handle_t ih; 255 const char *intrstr; 256 pcireg_t reg; 257 int rseg, i, j, size, rv, memreg, ioreg; 258 bus_size_t memsize = 0, iosize = 0; 259 struct amr_ccb *ac; 260 261 aprint_naive(": RAID controller\n"); 262 263 amr = (struct amr_softc *)self; 264 pa = (struct pci_attach_args *)aux; 265 pc = pa->pa_pc; 266 267 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 268 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 269 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 270 break; 271 apt = amr_pci_type + i; 272 273 memreg = ioreg = 0; 274 for (i = 0x10; i <= 0x14; i += 4) { 275 reg = pci_conf_read(pc, pa->pa_tag, i); 276 switch (PCI_MAPREG_TYPE(reg)) { 277 case PCI_MAPREG_TYPE_MEM: 278 if ((memsize = PCI_MAPREG_MEM_SIZE(reg)) != 0) 279 memreg = i; 280 break; 281 case PCI_MAPREG_TYPE_IO: 282 if ((iosize = PCI_MAPREG_IO_SIZE(reg)) != 0) 283 ioreg = i; 284 break; 285 286 } 287 } 288 289 if (memreg != 0) 290 if (pci_mapreg_map(pa, memreg, PCI_MAPREG_TYPE_MEM, 0, 291 &memt, &memh, NULL, NULL)) 292 memreg = 0; 293 if (ioreg != 0) 294 if (pci_mapreg_map(pa, ioreg, PCI_MAPREG_TYPE_IO, 0, 295 &iot, &ioh, NULL, NULL)) 296 ioreg = 0; 297 298 if (memreg) { 299 amr->amr_iot = memt; 300 amr->amr_ioh = memh; 301 amr->amr_ios = memsize; 302 } else if (ioreg) { 303 amr->amr_iot = iot; 304 amr->amr_ioh = ioh; 305 amr->amr_ios = iosize; 306 } else { 307 aprint_error("can't map control registers\n"); 308 amr_teardown(amr); 309 return; 310 } 311 312 amr->amr_flags |= AMRF_PCI_REGS; 313 amr->amr_dmat = pa->pa_dmat; 314 amr->amr_pc = pa->pa_pc; 315 316 /* Enable the device. */ 317 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 318 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 319 reg | PCI_COMMAND_MASTER_ENABLE); 320 321 /* Map and establish the interrupt. */ 322 if (pci_intr_map(pa, &ih)) { 323 aprint_error("can't map interrupt\n"); 324 amr_teardown(amr); 325 return; 326 } 327 intrstr = pci_intr_string(pc, ih); 328 amr->amr_ih = pci_intr_establish(pc, ih, IPL_BIO, amr_intr, amr); 329 if (amr->amr_ih == NULL) { 330 aprint_error("can't establish interrupt"); 331 if (intrstr != NULL) 332 aprint_normal(" at %s", intrstr); 333 aprint_normal("\n"); 334 amr_teardown(amr); 335 return; 336 } 337 amr->amr_flags |= AMRF_PCI_INTR; 338 339 /* 340 * Allocate space for the mailbox and S/G lists. Some controllers 341 * don't like S/G lists to be located below 0x2000, so we allocate 342 * enough slop to enable us to compensate. 343 * 344 * The standard mailbox structure needs to be aligned on a 16-byte 345 * boundary. The 64-bit mailbox has one extra field, 4 bytes in 346 * size, which preceeds the standard mailbox. 347 */ 348 size = AMR_SGL_SIZE * AMR_MAX_CMDS + 0x2000; 349 amr->amr_dmasize = size; 350 351 if ((rv = bus_dmamem_alloc(amr->amr_dmat, size, PAGE_SIZE, 0, 352 &amr->amr_dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 353 aprint_error("%s: unable to allocate buffer, rv = %d\n", 354 amr->amr_dv.dv_xname, rv); 355 amr_teardown(amr); 356 return; 357 } 358 amr->amr_flags |= AMRF_DMA_ALLOC; 359 360 if ((rv = bus_dmamem_map(amr->amr_dmat, &amr->amr_dmaseg, rseg, size, 361 (caddr_t *)&amr->amr_mbox, 362 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 363 aprint_error("%s: unable to map buffer, rv = %d\n", 364 amr->amr_dv.dv_xname, rv); 365 amr_teardown(amr); 366 return; 367 } 368 amr->amr_flags |= AMRF_DMA_MAP; 369 370 if ((rv = bus_dmamap_create(amr->amr_dmat, size, 1, size, 0, 371 BUS_DMA_NOWAIT, &amr->amr_dmamap)) != 0) { 372 aprint_error("%s: unable to create buffer DMA map, rv = %d\n", 373 amr->amr_dv.dv_xname, rv); 374 amr_teardown(amr); 375 return; 376 } 377 amr->amr_flags |= AMRF_DMA_CREATE; 378 379 if ((rv = bus_dmamap_load(amr->amr_dmat, amr->amr_dmamap, 380 amr->amr_mbox, size, NULL, BUS_DMA_NOWAIT)) != 0) { 381 aprint_error("%s: unable to load buffer DMA map, rv = %d\n", 382 amr->amr_dv.dv_xname, rv); 383 amr_teardown(amr); 384 return; 385 } 386 amr->amr_flags |= AMRF_DMA_LOAD; 387 388 memset(amr->amr_mbox, 0, size); 389 390 amr->amr_mbox_paddr = amr->amr_dmamap->dm_segs[0].ds_addr; 391 amr->amr_sgls_paddr = (amr->amr_mbox_paddr + 0x1fff) & ~0x1fff; 392 amr->amr_sgls = (struct amr_sgentry *)((caddr_t)amr->amr_mbox + 393 amr->amr_sgls_paddr - amr->amr_dmamap->dm_segs[0].ds_addr); 394 395 /* 396 * Allocate and initalise the command control blocks. 397 */ 398 ac = malloc(sizeof(*ac) * AMR_MAX_CMDS, M_DEVBUF, M_NOWAIT | M_ZERO); 399 amr->amr_ccbs = ac; 400 SLIST_INIT(&amr->amr_ccb_freelist); 401 TAILQ_INIT(&amr->amr_ccb_active); 402 amr->amr_flags |= AMRF_CCBS; 403 404 if (amr_max_xfer == 0) { 405 amr_max_xfer = min(((AMR_MAX_SEGS - 1) * PAGE_SIZE), MAXPHYS); 406 amr_max_segs = (amr_max_xfer + (PAGE_SIZE * 2) - 1) / PAGE_SIZE; 407 } 408 409 for (i = 0; i < AMR_MAX_CMDS; i++, ac++) { 410 rv = bus_dmamap_create(amr->amr_dmat, amr_max_xfer, 411 amr_max_segs, amr_max_xfer, 0, 412 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ac->ac_xfer_map); 413 if (rv != 0) 414 break; 415 416 ac->ac_ident = i; 417 amr_ccb_free(amr, ac); 418 } 419 if (i != AMR_MAX_CMDS) { 420 aprint_error("%s: memory exhausted\n", amr->amr_dv.dv_xname); 421 amr_teardown(amr); 422 return; 423 } 424 425 /* 426 * Take care of model-specific tasks. 427 */ 428 if ((apt->apt_flags & AT_QUARTZ) != 0) { 429 amr->amr_submit = amr_quartz_submit; 430 amr->amr_get_work = amr_quartz_get_work; 431 } else { 432 amr->amr_submit = amr_std_submit; 433 amr->amr_get_work = amr_std_get_work; 434 435 /* Notify the controller of the mailbox location. */ 436 amr_outl(amr, AMR_SREG_MBOX, (u_int32_t)amr->amr_mbox_paddr + 16); 437 amr_outb(amr, AMR_SREG_MBOX_ENABLE, AMR_SMBOX_ENABLE_ADDR); 438 439 /* Clear outstanding interrupts and enable interrupts. */ 440 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 441 amr_outb(amr, AMR_SREG_TOGL, 442 amr_inb(amr, AMR_SREG_TOGL) | AMR_STOGL_ENABLE); 443 } 444 445 /* 446 * Retrieve parameters, and tell the world about us. 447 */ 448 amr->amr_enqbuf = malloc(AMR_ENQUIRY_BUFSIZE, M_DEVBUF, M_NOWAIT); 449 amr->amr_flags |= AMRF_ENQBUF; 450 amr->amr_maxqueuecnt = i; 451 aprint_normal(": AMI RAID "); 452 if (amr_init(amr, intrstr, pa) != 0) { 453 amr_teardown(amr); 454 return; 455 } 456 457 /* 458 * Cap the maximum number of outstanding commands. AMI's Linux 459 * driver doesn't trust the controller's reported value, and lockups 460 * have been seen when we do. 461 */ 462 amr->amr_maxqueuecnt = min(amr->amr_maxqueuecnt, AMR_MAX_CMDS); 463 if (amr->amr_maxqueuecnt > i) 464 amr->amr_maxqueuecnt = i; 465 466 /* Set our `shutdownhook' before we start any device activity. */ 467 if (amr_sdh == NULL) 468 amr_sdh = shutdownhook_establish(amr_shutdown, NULL); 469 470 /* Attach sub-devices. */ 471 for (j = 0; j < amr->amr_numdrives; j++) { 472 if (amr->amr_drive[j].al_size == 0) 473 continue; 474 amra.amra_unit = j; 475 amr->amr_drive[j].al_dv = config_found_sm(&amr->amr_dv, &amra, 476 amr_print, amr_submatch); 477 } 478 479 SIMPLEQ_INIT(&amr->amr_ccb_queue); 480 481 /* XXX This doesn't work for newer boards yet. */ 482 if ((apt->apt_flags & AT_QUARTZ) == 0) 483 kthread_create(amr_thread_create, amr); 484 } 485 486 /* 487 * Free up resources. 488 */ 489 void 490 amr_teardown(struct amr_softc *amr) 491 { 492 struct amr_ccb *ac; 493 int fl; 494 495 fl = amr->amr_flags; 496 497 if ((fl & AMRF_THREAD) != 0) { 498 amr->amr_flags |= AMRF_THREAD_EXIT; 499 wakeup(amr_thread); 500 while ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) 501 tsleep(&amr->amr_flags, PWAIT, "amrexit", 0); 502 } 503 if ((fl & AMRF_CCBS) != 0) { 504 SLIST_FOREACH(ac, &amr->amr_ccb_freelist, ac_chain.slist) { 505 bus_dmamap_destroy(amr->amr_dmat, ac->ac_xfer_map); 506 } 507 free(amr->amr_ccbs, M_DEVBUF); 508 } 509 if ((fl & AMRF_ENQBUF) != 0) 510 free(amr->amr_enqbuf, M_DEVBUF); 511 if ((fl & AMRF_DMA_LOAD) != 0) 512 bus_dmamap_unload(amr->amr_dmat, amr->amr_dmamap); 513 if ((fl & AMRF_DMA_MAP) != 0) 514 bus_dmamem_unmap(amr->amr_dmat, (caddr_t)amr->amr_mbox, 515 amr->amr_dmasize); 516 if ((fl & AMRF_DMA_ALLOC) != 0) 517 bus_dmamem_free(amr->amr_dmat, &amr->amr_dmaseg, 1); 518 if ((fl & AMRF_DMA_CREATE) != 0) 519 bus_dmamap_destroy(amr->amr_dmat, amr->amr_dmamap); 520 if ((fl & AMRF_PCI_INTR) != 0) 521 pci_intr_disestablish(amr->amr_pc, amr->amr_ih); 522 if ((fl & AMRF_PCI_REGS) != 0) 523 bus_space_unmap(amr->amr_iot, amr->amr_ioh, amr->amr_ios); 524 } 525 526 /* 527 * Print autoconfiguration message for a sub-device. 528 */ 529 int 530 amr_print(void *aux, const char *pnp) 531 { 532 struct amr_attach_args *amra; 533 534 amra = (struct amr_attach_args *)aux; 535 536 if (pnp != NULL) 537 aprint_normal("block device at %s", pnp); 538 aprint_normal(" unit %d", amra->amra_unit); 539 return (UNCONF); 540 } 541 542 /* 543 * Match a sub-device. 544 */ 545 int 546 amr_submatch(struct device *parent, struct cfdata *cf, void *aux) 547 { 548 struct amr_attach_args *amra; 549 550 amra = (struct amr_attach_args *)aux; 551 552 if (cf->amracf_unit != AMRCF_UNIT_DEFAULT && 553 cf->amracf_unit != amra->amra_unit) 554 return (0); 555 556 return (config_match(parent, cf, aux)); 557 } 558 559 /* 560 * Retrieve operational parameters and describe the controller. 561 */ 562 int 563 amr_init(struct amr_softc *amr, const char *intrstr, 564 struct pci_attach_args *pa) 565 { 566 struct amr_adapter_info *aa; 567 struct amr_prodinfo *ap; 568 struct amr_enquiry *ae; 569 struct amr_enquiry3 *aex; 570 const char *prodstr; 571 u_int i, sig, ishp; 572 char buf[64]; 573 574 /* 575 * Try to get 40LD product info, which tells us what the card is 576 * labelled as. 577 */ 578 ap = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_PRODUCT_INFO, 0, 579 amr->amr_enqbuf); 580 if (ap != NULL) { 581 aprint_normal("<%.80s>\n", ap->ap_product); 582 if (intrstr != NULL) 583 aprint_normal("%s: interrupting at %s\n", 584 amr->amr_dv.dv_xname, intrstr); 585 aprint_normal("%s: firmware %.16s, BIOS %.16s, %dMB RAM\n", 586 amr->amr_dv.dv_xname, ap->ap_firmware, ap->ap_bios, 587 le16toh(ap->ap_memsize)); 588 589 amr->amr_maxqueuecnt = ap->ap_maxio; 590 591 /* 592 * Fetch and record state of logical drives. 593 */ 594 aex = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_ENQ3, 595 AMR_CONFIG_ENQ3_SOLICITED_FULL, amr->amr_enqbuf); 596 if (aex == NULL) { 597 aprint_error("%s ENQUIRY3 failed\n", 598 amr->amr_dv.dv_xname); 599 return (-1); 600 } 601 602 if (aex->ae_numldrives > AMR_MAX_UNITS) { 603 aprint_error( 604 "%s: adjust AMR_MAX_UNITS to %d (currently %d)" 605 "\n", amr->amr_dv.dv_xname, 606 ae->ae_ldrv.al_numdrives, AMR_MAX_UNITS); 607 amr->amr_numdrives = AMR_MAX_UNITS; 608 } else 609 amr->amr_numdrives = aex->ae_numldrives; 610 611 for (i = 0; i < amr->amr_numdrives; i++) { 612 amr->amr_drive[i].al_size = 613 le32toh(aex->ae_drivesize[i]); 614 amr->amr_drive[i].al_state = aex->ae_drivestate[i]; 615 amr->amr_drive[i].al_properties = aex->ae_driveprop[i]; 616 } 617 618 return (0); 619 } 620 621 /* 622 * Try 8LD extended ENQUIRY to get the controller signature. Once 623 * found, search for a product description. 624 */ 625 ae = amr_enquire(amr, AMR_CMD_EXT_ENQUIRY2, 0, 0, amr->amr_enqbuf); 626 if (ae != NULL) { 627 i = 0; 628 sig = le32toh(ae->ae_signature); 629 630 while (i < sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 631 if (amr_typestr[i].at_sig == sig) 632 break; 633 i++; 634 } 635 if (i == sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 636 sprintf(buf, "unknown ENQUIRY2 sig (0x%08x)", sig); 637 prodstr = buf; 638 } else 639 prodstr = amr_typestr[i].at_str; 640 } else { 641 ae = amr_enquire(amr, AMR_CMD_ENQUIRY, 0, 0, amr->amr_enqbuf); 642 if (ae == NULL) { 643 aprint_error("%s: unsupported controller\n", 644 amr->amr_dv.dv_xname); 645 return (-1); 646 } 647 648 switch (PCI_PRODUCT(pa->pa_id)) { 649 case PCI_PRODUCT_AMI_MEGARAID: 650 prodstr = "Series 428"; 651 break; 652 case PCI_PRODUCT_AMI_MEGARAID2: 653 prodstr = "Series 434"; 654 break; 655 default: 656 sprintf(buf, "unknown PCI dev (0x%04x)", 657 PCI_PRODUCT(pa->pa_id)); 658 prodstr = buf; 659 break; 660 } 661 } 662 663 /* 664 * HP NetRaid controllers have a special encoding of the firmware 665 * and BIOS versions. The AMI version seems to have it as strings 666 * whereas the HP version does it with a leading uppercase character 667 * and two binary numbers. 668 */ 669 aa = &ae->ae_adapter; 670 671 if (aa->aa_firmware[2] >= 'A' && aa->aa_firmware[2] <= 'Z' && 672 aa->aa_firmware[1] < ' ' && aa->aa_firmware[0] < ' ' && 673 aa->aa_bios[2] >= 'A' && aa->aa_bios[2] <= 'Z' && 674 aa->aa_bios[1] < ' ' && aa->aa_bios[0] < ' ') { 675 if (le32toh(ae->ae_signature) == AMR_SIG_438) { 676 /* The AMI 438 is a NetRaid 3si in HP-land. */ 677 prodstr = "HP NetRaid 3si"; 678 } 679 ishp = 1; 680 } else 681 ishp = 0; 682 683 aprint_normal("<%s>\n", prodstr); 684 if (intrstr != NULL) 685 aprint_normal("%s: interrupting at %s\n", amr->amr_dv.dv_xname, 686 intrstr); 687 688 if (ishp) 689 aprint_normal("%s: firmware <%c.%02d.%02d>, BIOS <%c.%02d.%02d>" 690 ", %dMB RAM\n", amr->amr_dv.dv_xname, aa->aa_firmware[2], 691 aa->aa_firmware[1], aa->aa_firmware[0], aa->aa_bios[2], 692 aa->aa_bios[1], aa->aa_bios[0], aa->aa_memorysize); 693 else 694 aprint_normal("%s: firmware <%.4s>, BIOS <%.4s>, %dMB RAM\n", 695 amr->amr_dv.dv_xname, aa->aa_firmware, aa->aa_bios, 696 aa->aa_memorysize); 697 698 amr->amr_maxqueuecnt = aa->aa_maxio; 699 700 /* 701 * Record state of logical drives. 702 */ 703 if (ae->ae_ldrv.al_numdrives > AMR_MAX_UNITS) { 704 aprint_error("%s: adjust AMR_MAX_UNITS to %d (currently %d)\n", 705 amr->amr_dv.dv_xname, ae->ae_ldrv.al_numdrives, 706 AMR_MAX_UNITS); 707 amr->amr_numdrives = AMR_MAX_UNITS; 708 } else 709 amr->amr_numdrives = ae->ae_ldrv.al_numdrives; 710 711 for (i = 0; i < AMR_MAX_UNITS; i++) { 712 amr->amr_drive[i].al_size = le32toh(ae->ae_ldrv.al_size[i]); 713 amr->amr_drive[i].al_state = ae->ae_ldrv.al_state[i]; 714 amr->amr_drive[i].al_properties = ae->ae_ldrv.al_properties[i]; 715 } 716 717 return (0); 718 } 719 720 /* 721 * Flush the internal cache on each configured controller. Called at 722 * shutdown time. 723 */ 724 void 725 amr_shutdown(void *cookie) 726 { 727 extern struct cfdriver amr_cd; 728 struct amr_softc *amr; 729 struct amr_ccb *ac; 730 int i, rv, s; 731 732 for (i = 0; i < amr_cd.cd_ndevs; i++) { 733 if ((amr = device_lookup(&amr_cd, i)) == NULL) 734 continue; 735 736 if ((rv = amr_ccb_alloc(amr, &ac)) == 0) { 737 ac->ac_cmd.mb_command = AMR_CMD_FLUSH; 738 s = splbio(); 739 rv = amr_ccb_poll(amr, ac, 30000); 740 splx(s); 741 amr_ccb_free(amr, ac); 742 } 743 if (rv != 0) 744 printf("%s: unable to flush cache (%d)\n", 745 amr->amr_dv.dv_xname, rv); 746 } 747 } 748 749 /* 750 * Interrupt service routine. 751 */ 752 int 753 amr_intr(void *cookie) 754 { 755 struct amr_softc *amr; 756 struct amr_ccb *ac; 757 struct amr_mailbox_resp mbox; 758 u_int i, forus, idx; 759 760 amr = cookie; 761 forus = 0; 762 763 while ((*amr->amr_get_work)(amr, &mbox) == 0) { 764 /* Iterate over completed commands in this result. */ 765 for (i = 0; i < mbox.mb_nstatus; i++) { 766 idx = mbox.mb_completed[i] - 1; 767 ac = amr->amr_ccbs + idx; 768 769 if (idx >= amr->amr_maxqueuecnt) { 770 printf("%s: bad status (bogus ID: %u=%u)\n", 771 amr->amr_dv.dv_xname, i, idx); 772 continue; 773 } 774 775 if ((ac->ac_flags & AC_ACTIVE) == 0) { 776 printf("%s: bad status (not active; 0x04%x)\n", 777 amr->amr_dv.dv_xname, ac->ac_flags); 778 continue; 779 } 780 781 ac->ac_status = mbox.mb_status; 782 ac->ac_flags = (ac->ac_flags & ~AC_ACTIVE) | 783 AC_COMPLETE; 784 TAILQ_REMOVE(&amr->amr_ccb_active, ac, ac_chain.tailq); 785 786 if ((ac->ac_flags & AC_MOAN) != 0) 787 printf("%s: ccb %d completed\n", 788 amr->amr_dv.dv_xname, ac->ac_ident); 789 790 /* Pass notification to upper layers. */ 791 if (ac->ac_handler != NULL) 792 (*ac->ac_handler)(ac); 793 else 794 wakeup(ac); 795 } 796 forus = 1; 797 } 798 799 if (forus) 800 amr_ccb_enqueue(amr, NULL); 801 802 return (forus); 803 } 804 805 /* 806 * Create the watchdog thread. 807 */ 808 void 809 amr_thread_create(void *cookie) 810 { 811 struct amr_softc *amr; 812 int rv; 813 814 amr = cookie; 815 816 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 817 amr->amr_flags ^= AMRF_THREAD_EXIT; 818 wakeup(&amr->amr_flags); 819 return; 820 } 821 822 rv = kthread_create1(amr_thread, amr, &amr->amr_thread, "%s", 823 amr->amr_dv.dv_xname); 824 if (rv != 0) 825 aprint_error("%s: unable to create thread (%d)", 826 amr->amr_dv.dv_xname, rv); 827 else 828 amr->amr_flags |= AMRF_THREAD; 829 } 830 831 /* 832 * Watchdog thread. 833 */ 834 void 835 amr_thread(void *cookie) 836 { 837 struct amr_softc *amr; 838 struct amr_ccb *ac; 839 struct amr_logdrive *al; 840 struct amr_enquiry *ae; 841 time_t curtime; 842 int rv, i, s; 843 844 amr = cookie; 845 ae = amr->amr_enqbuf; 846 847 for (;;) { 848 tsleep(amr_thread, PWAIT, "amrwdog", AMR_WDOG_TICKS); 849 850 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 851 amr->amr_flags ^= AMRF_THREAD_EXIT; 852 wakeup(&amr->amr_flags); 853 kthread_exit(0); 854 } 855 856 s = splbio(); 857 amr_intr(cookie); 858 curtime = (time_t)mono_time.tv_sec; 859 ac = TAILQ_FIRST(&amr->amr_ccb_active); 860 while (ac != NULL) { 861 if (ac->ac_start_time + AMR_TIMEOUT > curtime) 862 break; 863 if ((ac->ac_flags & AC_MOAN) == 0) { 864 printf("%s: ccb %d timed out; mailbox:\n", 865 amr->amr_dv.dv_xname, ac->ac_ident); 866 amr_ccb_dump(amr, ac); 867 ac->ac_flags |= AC_MOAN; 868 } 869 ac = TAILQ_NEXT(ac, ac_chain.tailq); 870 } 871 splx(s); 872 873 if ((rv = amr_ccb_alloc(amr, &ac)) != 0) { 874 printf("%s: ccb_alloc failed (%d)\n", 875 amr->amr_dv.dv_xname, rv); 876 continue; 877 } 878 879 ac->ac_cmd.mb_command = AMR_CMD_ENQUIRY; 880 881 rv = amr_ccb_map(amr, ac, amr->amr_enqbuf, 882 AMR_ENQUIRY_BUFSIZE, 0); 883 if (rv != 0) { 884 printf("%s: ccb_map failed (%d)\n", 885 amr->amr_dv.dv_xname, rv); 886 amr_ccb_free(amr, ac); 887 continue; 888 } 889 890 rv = amr_ccb_wait(amr, ac); 891 amr_ccb_unmap(amr, ac); 892 if (rv != 0) { 893 printf("%s: enquiry failed (st=%d)\n", 894 amr->amr_dv.dv_xname, ac->ac_status); 895 continue; 896 } 897 amr_ccb_free(amr, ac); 898 899 al = amr->amr_drive; 900 for (i = 0; i < AMR_MAX_UNITS; i++, al++) { 901 if (al->al_dv == NULL) 902 continue; 903 if (al->al_state == ae->ae_ldrv.al_state[i]) 904 continue; 905 906 printf("%s: state changed: %s -> %s\n", 907 al->al_dv->dv_xname, 908 amr_drive_state(al->al_state, NULL), 909 amr_drive_state(ae->ae_ldrv.al_state[i], NULL)); 910 911 al->al_state = ae->ae_ldrv.al_state[i]; 912 } 913 } 914 } 915 916 /* 917 * Return a text description of a logical drive's current state. 918 */ 919 const char * 920 amr_drive_state(int state, int *happy) 921 { 922 const char *str; 923 924 state = AMR_DRV_CURSTATE(state); 925 if (state >= sizeof(amr_dstate) / sizeof(amr_dstate[0])) { 926 if (happy) 927 *happy = 1; 928 str = "status unknown"; 929 } else { 930 if (happy) 931 *happy = amr_dstate[state].ds_happy; 932 str = amr_dstate[state].ds_descr; 933 } 934 935 return (str); 936 } 937 938 /* 939 * Run a generic enquiry-style command. 940 */ 941 void * 942 amr_enquire(struct amr_softc *amr, u_int8_t cmd, u_int8_t cmdsub, 943 u_int8_t cmdqual, void *buf) 944 { 945 struct amr_ccb *ac; 946 u_int8_t *mb; 947 int rv; 948 949 if (amr_ccb_alloc(amr, &ac) != 0) 950 return (NULL); 951 952 /* Build the command proper. */ 953 mb = (u_int8_t *)&ac->ac_cmd; 954 mb[0] = cmd; 955 mb[2] = cmdsub; 956 mb[3] = cmdqual; 957 958 rv = amr_ccb_map(amr, ac, buf, AMR_ENQUIRY_BUFSIZE, 0); 959 if (rv == 0) { 960 rv = amr_ccb_poll(amr, ac, 2000); 961 amr_ccb_unmap(amr, ac); 962 } 963 amr_ccb_free(amr, ac); 964 965 return (rv ? NULL : buf); 966 } 967 968 /* 969 * Allocate and initialise a CCB. 970 */ 971 int 972 amr_ccb_alloc(struct amr_softc *amr, struct amr_ccb **acp) 973 { 974 int s; 975 976 s = splbio(); 977 if ((*acp = SLIST_FIRST(&amr->amr_ccb_freelist)) == NULL) { 978 splx(s); 979 return (EAGAIN); 980 } 981 SLIST_REMOVE_HEAD(&amr->amr_ccb_freelist, ac_chain.slist); 982 splx(s); 983 984 return (0); 985 } 986 987 /* 988 * Free a CCB. 989 */ 990 void 991 amr_ccb_free(struct amr_softc *amr, struct amr_ccb *ac) 992 { 993 int s; 994 995 memset(&ac->ac_cmd, 0, sizeof(ac->ac_cmd)); 996 ac->ac_cmd.mb_ident = ac->ac_ident + 1; 997 ac->ac_cmd.mb_busy = 1; 998 ac->ac_handler = NULL; 999 ac->ac_flags = 0; 1000 1001 s = splbio(); 1002 SLIST_INSERT_HEAD(&amr->amr_ccb_freelist, ac, ac_chain.slist); 1003 splx(s); 1004 } 1005 1006 /* 1007 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 1008 * the order that they were enqueued and try to submit their command blocks 1009 * to the controller for execution. 1010 */ 1011 void 1012 amr_ccb_enqueue(struct amr_softc *amr, struct amr_ccb *ac) 1013 { 1014 int s; 1015 1016 s = splbio(); 1017 1018 if (ac != NULL) 1019 SIMPLEQ_INSERT_TAIL(&amr->amr_ccb_queue, ac, ac_chain.simpleq); 1020 1021 while ((ac = SIMPLEQ_FIRST(&amr->amr_ccb_queue)) != NULL) { 1022 if ((*amr->amr_submit)(amr, ac) != 0) 1023 break; 1024 SIMPLEQ_REMOVE_HEAD(&amr->amr_ccb_queue, ac_chain.simpleq); 1025 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1026 } 1027 1028 splx(s); 1029 } 1030 1031 /* 1032 * Map the specified CCB's data buffer onto the bus, and fill the 1033 * scatter-gather list. 1034 */ 1035 int 1036 amr_ccb_map(struct amr_softc *amr, struct amr_ccb *ac, void *data, int size, 1037 int out) 1038 { 1039 struct amr_sgentry *sge; 1040 struct amr_mailbox_cmd *mb; 1041 int nsegs, i, rv, sgloff; 1042 bus_dmamap_t xfer; 1043 1044 xfer = ac->ac_xfer_map; 1045 1046 rv = bus_dmamap_load(amr->amr_dmat, xfer, data, size, NULL, 1047 BUS_DMA_NOWAIT); 1048 if (rv != 0) 1049 return (rv); 1050 1051 mb = &ac->ac_cmd; 1052 ac->ac_xfer_size = size; 1053 ac->ac_flags |= (out ? AC_XFER_OUT : AC_XFER_IN); 1054 sgloff = AMR_SGL_SIZE * ac->ac_ident; 1055 1056 /* We don't need to use a scatter/gather list for just 1 segment. */ 1057 nsegs = xfer->dm_nsegs; 1058 if (nsegs == 1) { 1059 mb->mb_nsgelem = 0; 1060 mb->mb_physaddr = htole32(xfer->dm_segs[0].ds_addr); 1061 ac->ac_flags |= AC_NOSGL; 1062 } else { 1063 mb->mb_nsgelem = nsegs; 1064 mb->mb_physaddr = htole32(amr->amr_sgls_paddr + sgloff); 1065 1066 sge = (struct amr_sgentry *)((caddr_t)amr->amr_sgls + sgloff); 1067 for (i = 0; i < nsegs; i++, sge++) { 1068 sge->sge_addr = htole32(xfer->dm_segs[i].ds_addr); 1069 sge->sge_count = htole32(xfer->dm_segs[i].ds_len); 1070 } 1071 } 1072 1073 bus_dmamap_sync(amr->amr_dmat, xfer, 0, ac->ac_xfer_size, 1074 out ? BUS_DMASYNC_PREWRITE : BUS_DMASYNC_PREREAD); 1075 1076 if ((ac->ac_flags & AC_NOSGL) == 0) 1077 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, sgloff, 1078 AMR_SGL_SIZE, BUS_DMASYNC_PREWRITE); 1079 1080 return (0); 1081 } 1082 1083 /* 1084 * Unmap the specified CCB's data buffer. 1085 */ 1086 void 1087 amr_ccb_unmap(struct amr_softc *amr, struct amr_ccb *ac) 1088 { 1089 1090 if ((ac->ac_flags & AC_NOSGL) == 0) 1091 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 1092 AMR_SGL_SIZE * ac->ac_ident, AMR_SGL_SIZE, 1093 BUS_DMASYNC_POSTWRITE); 1094 bus_dmamap_sync(amr->amr_dmat, ac->ac_xfer_map, 0, ac->ac_xfer_size, 1095 (ac->ac_flags & AC_XFER_IN) != 0 ? 1096 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1097 bus_dmamap_unload(amr->amr_dmat, ac->ac_xfer_map); 1098 } 1099 1100 /* 1101 * Submit a command to the controller and poll on completion. Return 1102 * non-zero on timeout or error. Must be called with interrupts blocked. 1103 */ 1104 int 1105 amr_ccb_poll(struct amr_softc *amr, struct amr_ccb *ac, int timo) 1106 { 1107 int rv; 1108 1109 if ((rv = (*amr->amr_submit)(amr, ac)) != 0) 1110 return (rv); 1111 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1112 1113 for (timo *= 10; timo != 0; timo--) { 1114 amr_intr(amr); 1115 if ((ac->ac_flags & AC_COMPLETE) != 0) 1116 break; 1117 DELAY(100); 1118 } 1119 1120 return (timo == 0 || ac->ac_status != 0 ? EIO : 0); 1121 } 1122 1123 /* 1124 * Submit a command to the controller and sleep on completion. Return 1125 * non-zero on error. 1126 */ 1127 int 1128 amr_ccb_wait(struct amr_softc *amr, struct amr_ccb *ac) 1129 { 1130 int s; 1131 1132 s = splbio(); 1133 amr_ccb_enqueue(amr, ac); 1134 tsleep(ac, PRIBIO, "amrcmd", 0); 1135 splx(s); 1136 1137 return (ac->ac_status != 0 ? EIO : 0); 1138 } 1139 1140 /* 1141 * Wait for the mailbox to become available. 1142 */ 1143 int 1144 amr_mbox_wait(struct amr_softc *amr) 1145 { 1146 int timo; 1147 1148 for (timo = 10000; timo != 0; timo--) { 1149 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1150 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1151 if (amr->amr_mbox->mb_cmd.mb_busy == 0) 1152 break; 1153 DELAY(100); 1154 } 1155 1156 if (timo == 0) 1157 printf("%s: controller wedged\n", amr->amr_dv.dv_xname); 1158 1159 return (timo != 0 ? 0 : EAGAIN); 1160 } 1161 1162 /* 1163 * Tell the controller that the mailbox contains a valid command. Must be 1164 * called with interrupts blocked. 1165 */ 1166 int 1167 amr_quartz_submit(struct amr_softc *amr, struct amr_ccb *ac) 1168 { 1169 u_int32_t v; 1170 1171 amr->amr_mbox->mb_poll = 0; 1172 amr->amr_mbox->mb_ack = 0; 1173 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1174 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1175 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1176 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1177 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1178 return (EAGAIN); 1179 1180 v = amr_inl(amr, AMR_QREG_IDB); 1181 if ((v & AMR_QIDB_SUBMIT) != 0) { 1182 amr->amr_mbox->mb_cmd.mb_busy = 0; 1183 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1184 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1185 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1186 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1187 return (EAGAIN); 1188 } 1189 1190 amr->amr_mbox->mb_segment = 0; 1191 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1192 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1193 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1194 1195 ac->ac_start_time = (time_t)mono_time.tv_sec; 1196 ac->ac_flags |= AC_ACTIVE; 1197 amr_outl(amr, AMR_QREG_IDB, 1198 (amr->amr_mbox_paddr + 16) | AMR_QIDB_SUBMIT); 1199 return (0); 1200 } 1201 1202 int 1203 amr_std_submit(struct amr_softc *amr, struct amr_ccb *ac) 1204 { 1205 1206 amr->amr_mbox->mb_poll = 0; 1207 amr->amr_mbox->mb_ack = 0; 1208 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1209 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1210 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1211 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1212 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1213 return (EAGAIN); 1214 1215 if ((amr_inb(amr, AMR_SREG_MBOX_BUSY) & AMR_SMBOX_BUSY_FLAG) != 0) { 1216 amr->amr_mbox->mb_cmd.mb_busy = 0; 1217 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1218 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1219 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1220 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1221 return (EAGAIN); 1222 } 1223 1224 amr->amr_mbox->mb_segment = 0; 1225 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1226 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1227 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1228 1229 ac->ac_start_time = (time_t)mono_time.tv_sec; 1230 ac->ac_flags |= AC_ACTIVE; 1231 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_POST); 1232 return (0); 1233 } 1234 1235 /* 1236 * Claim any work that the controller has completed; acknowledge completion, 1237 * save details of the completion in (mbsave). Must be called with 1238 * interrupts blocked. 1239 */ 1240 int 1241 amr_quartz_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1242 { 1243 1244 /* Work waiting for us? */ 1245 if (amr_inl(amr, AMR_QREG_ODB) != AMR_QODB_READY) 1246 return (-1); 1247 1248 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1249 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1250 1251 /* Save the mailbox, which contains a list of completed commands. */ 1252 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1253 1254 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1255 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1256 1257 /* Ack the interrupt and mailbox transfer. */ 1258 amr_outl(amr, AMR_QREG_ODB, AMR_QODB_READY); 1259 amr_outl(amr, AMR_QREG_IDB, (amr->amr_mbox_paddr+16) | AMR_QIDB_ACK); 1260 1261 /* 1262 * This waits for the controller to notice that we've taken the 1263 * command from it. It's very inefficient, and we shouldn't do it, 1264 * but if we remove this code, we stop completing commands under 1265 * load. 1266 * 1267 * Peter J says we shouldn't do this. The documentation says we 1268 * should. Who is right? 1269 */ 1270 while ((amr_inl(amr, AMR_QREG_IDB) & AMR_QIDB_ACK) != 0) 1271 DELAY(10); 1272 1273 return (0); 1274 } 1275 1276 int 1277 amr_std_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1278 { 1279 u_int8_t istat; 1280 1281 /* Check for valid interrupt status. */ 1282 if (((istat = amr_inb(amr, AMR_SREG_INTR)) & AMR_SINTR_VALID) == 0) 1283 return (-1); 1284 1285 /* Ack the interrupt. */ 1286 amr_outb(amr, AMR_SREG_INTR, istat); 1287 1288 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1289 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1290 1291 /* Save mailbox, which contains a list of completed commands. */ 1292 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1293 1294 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1295 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1296 1297 /* Ack mailbox transfer. */ 1298 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 1299 1300 return (0); 1301 } 1302 1303 void 1304 amr_ccb_dump(struct amr_softc *amr, struct amr_ccb *ac) 1305 { 1306 int i; 1307 1308 printf("%s: ", amr->amr_dv.dv_xname); 1309 for (i = 0; i < 4; i++) 1310 printf("%08x ", ((u_int32_t *)&ac->ac_cmd)[i]); 1311 printf("\n"); 1312 } 1313
Indexes created Sun Sep 21 20:09:37 GMT 2025