amr.c revision 1.19.2.1
1 /* $NetBSD: amr.c,v 1.19.2.1 2004/09/11 13:27:29 tron Exp $ */ 2 3 /*- 4 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999,2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: amr_pci.c,v 1.5 2000/08/30 07:52:40 msmith Exp 66 * from FreeBSD: amr.c,v 1.16 2000/08/30 07:52:40 msmith Exp 67 */ 68 69 /* 70 * Driver for AMI RAID controllers. 71 */ 72 73 #include <sys/cdefs.h> 74 __KERNEL_RCSID(0, "$NetBSD: amr.c,v 1.19.2.1 2004/09/11 13:27:29 tron Exp $"); 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/device.h> 80 #include <sys/queue.h> 81 #include <sys/proc.h> 82 #include <sys/buf.h> 83 #include <sys/malloc.h> 84 #include <sys/kthread.h> 85 86 #include <uvm/uvm_extern.h> 87 88 #include <machine/endian.h> 89 #include <machine/bus.h> 90 91 #include <dev/pci/pcidevs.h> 92 #include <dev/pci/pcivar.h> 93 #include <dev/pci/amrreg.h> 94 #include <dev/pci/amrvar.h> 95 96 void amr_attach(struct device *, struct device *, void *); 97 void amr_ccb_dump(struct amr_softc *, struct amr_ccb *); 98 void *amr_enquire(struct amr_softc *, u_int8_t, u_int8_t, u_int8_t, void *); 99 int amr_init(struct amr_softc *, const char *, 100 struct pci_attach_args *pa); 101 int amr_intr(void *); 102 int amr_match(struct device *, struct cfdata *, void *); 103 int amr_print(void *, const char *); 104 void amr_shutdown(void *); 105 int amr_submatch(struct device *, struct cfdata *, void *); 106 void amr_teardown(struct amr_softc *); 107 void amr_thread(void *); 108 void amr_thread_create(void *); 109 110 int amr_mbox_wait(struct amr_softc *); 111 int amr_quartz_get_work(struct amr_softc *, struct amr_mailbox_resp *); 112 int amr_quartz_submit(struct amr_softc *, struct amr_ccb *); 113 int amr_std_get_work(struct amr_softc *, struct amr_mailbox_resp *); 114 int amr_std_submit(struct amr_softc *, struct amr_ccb *); 115 116 static inline u_int8_t amr_inb(struct amr_softc *, int); 117 static inline u_int32_t amr_inl(struct amr_softc *, int); 118 static inline void amr_outb(struct amr_softc *, int, u_int8_t); 119 static inline void amr_outl(struct amr_softc *, int, u_int32_t); 120 121 CFATTACH_DECL(amr, sizeof(struct amr_softc), 122 amr_match, amr_attach, NULL, NULL); 123 124 #define AT_QUARTZ 0x01 /* `Quartz' chipset */ 125 #define AT_SIG 0x02 /* Check for signature */ 126 127 struct amr_pci_type { 128 u_short apt_vendor; 129 u_short apt_product; 130 u_short apt_flags; 131 } const amr_pci_type[] = { 132 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID, 0 }, 133 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID2, 0 }, 134 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 135 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ | AT_SIG }, 137 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI, AT_QUARTZ }, 138 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI_2, AT_QUARTZ }, 139 }; 140 141 struct amr_typestr { 142 const char *at_str; 143 int at_sig; 144 } const amr_typestr[] = { 145 { "Series 431", AMR_SIG_431 }, 146 { "Series 438", AMR_SIG_438 }, 147 { "Series 466", AMR_SIG_466 }, 148 { "Series 467", AMR_SIG_467 }, 149 { "Series 490", AMR_SIG_490 }, 150 { "Series 762", AMR_SIG_762 }, 151 { "HP NetRAID (T5)", AMR_SIG_T5 }, 152 { "HP NetRAID (T7)", AMR_SIG_T7 }, 153 }; 154 155 struct { 156 const char *ds_descr; 157 int ds_happy; 158 } const amr_dstate[] = { 159 { "offline", 0 }, 160 { "degraded", 1 }, 161 { "optimal", 1 }, 162 { "online", 1 }, 163 { "failed", 0 }, 164 { "rebuilding", 1 }, 165 { "hotspare", 0 }, 166 }; 167 168 void *amr_sdh; 169 int amr_max_segs; 170 int amr_max_xfer; 171 172 static inline u_int8_t 173 amr_inb(struct amr_softc *amr, int off) 174 { 175 176 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 177 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 178 return (bus_space_read_1(amr->amr_iot, amr->amr_ioh, off)); 179 } 180 181 static inline u_int32_t 182 amr_inl(struct amr_softc *amr, int off) 183 { 184 185 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 186 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 187 return (bus_space_read_4(amr->amr_iot, amr->amr_ioh, off)); 188 } 189 190 static inline void 191 amr_outb(struct amr_softc *amr, int off, u_int8_t val) 192 { 193 194 bus_space_write_1(amr->amr_iot, amr->amr_ioh, off, val); 195 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 196 BUS_SPACE_BARRIER_WRITE); 197 } 198 199 static inline void 200 amr_outl(struct amr_softc *amr, int off, u_int32_t val) 201 { 202 203 bus_space_write_4(amr->amr_iot, amr->amr_ioh, off, val); 204 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 205 BUS_SPACE_BARRIER_WRITE); 206 } 207 208 /* 209 * Match a supported device. 210 */ 211 int 212 amr_match(struct device *parent, struct cfdata *match, void *aux) 213 { 214 struct pci_attach_args *pa; 215 pcireg_t s; 216 int i; 217 218 pa = (struct pci_attach_args *)aux; 219 220 /* 221 * Don't match the device if it's operating in I2O mode. In this 222 * case it should be handled by the `iop' driver. 223 */ 224 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 225 return (0); 226 227 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 228 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 229 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 230 break; 231 232 if (i == sizeof(amr_pci_type) / sizeof(amr_pci_type[0])) 233 return (0); 234 235 if ((amr_pci_type[i].apt_flags & AT_SIG) == 0) 236 return (1); 237 238 s = pci_conf_read(pa->pa_pc, pa->pa_tag, AMR_QUARTZ_SIG_REG) & 0xffff; 239 return (s == AMR_QUARTZ_SIG0 || s == AMR_QUARTZ_SIG1); 240 } 241 242 /* 243 * Attach a supported device. 244 */ 245 void 246 amr_attach(struct device *parent, struct device *self, void *aux) 247 { 248 struct pci_attach_args *pa; 249 struct amr_attach_args amra; 250 const struct amr_pci_type *apt; 251 struct amr_softc *amr; 252 pci_chipset_tag_t pc; 253 pci_intr_handle_t ih; 254 const char *intrstr; 255 pcireg_t reg; 256 int rseg, i, j, size, rv, memreg, ioreg; 257 struct amr_ccb *ac; 258 259 aprint_naive(": RAID controller\n"); 260 261 amr = (struct amr_softc *)self; 262 pa = (struct pci_attach_args *)aux; 263 pc = pa->pa_pc; 264 265 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 266 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 267 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 268 break; 269 apt = amr_pci_type + i; 270 271 memreg = ioreg = 0; 272 for (i = 0x10; i <= 0x14; i += 4) { 273 reg = pci_conf_read(pc, pa->pa_tag, i); 274 switch (PCI_MAPREG_TYPE(reg)) { 275 case PCI_MAPREG_TYPE_MEM: 276 if (PCI_MAPREG_MEM_SIZE(reg) != 0) 277 memreg = i; 278 break; 279 case PCI_MAPREG_TYPE_IO: 280 if (PCI_MAPREG_IO_SIZE(reg) != 0) 281 ioreg = i; 282 break; 283 284 } 285 } 286 287 if (memreg && pci_mapreg_map(pa, memreg, PCI_MAPREG_TYPE_MEM, 0, 288 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 289 ; 290 else if (ioreg && pci_mapreg_map(pa, ioreg, PCI_MAPREG_TYPE_IO, 0, 291 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 292 ; 293 else { 294 aprint_error("can't map control registers\n"); 295 amr_teardown(amr); 296 return; 297 } 298 299 amr->amr_flags |= AMRF_PCI_REGS; 300 amr->amr_dmat = pa->pa_dmat; 301 amr->amr_pc = pa->pa_pc; 302 303 /* Enable the device. */ 304 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 305 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 306 reg | PCI_COMMAND_MASTER_ENABLE); 307 308 /* Map and establish the interrupt. */ 309 if (pci_intr_map(pa, &ih)) { 310 aprint_error("can't map interrupt\n"); 311 amr_teardown(amr); 312 return; 313 } 314 intrstr = pci_intr_string(pc, ih); 315 amr->amr_ih = pci_intr_establish(pc, ih, IPL_BIO, amr_intr, amr); 316 if (amr->amr_ih == NULL) { 317 aprint_error("can't establish interrupt"); 318 if (intrstr != NULL) 319 aprint_normal(" at %s", intrstr); 320 aprint_normal("\n"); 321 amr_teardown(amr); 322 return; 323 } 324 amr->amr_flags |= AMRF_PCI_INTR; 325 326 /* 327 * Allocate space for the mailbox and S/G lists. Some controllers 328 * don't like S/G lists to be located below 0x2000, so we allocate 329 * enough slop to enable us to compensate. 330 * 331 * The standard mailbox structure needs to be aligned on a 16-byte 332 * boundary. The 64-bit mailbox has one extra field, 4 bytes in 333 * size, which preceeds the standard mailbox. 334 */ 335 size = AMR_SGL_SIZE * AMR_MAX_CMDS + 0x2000; 336 amr->amr_dmasize = size; 337 338 if ((rv = bus_dmamem_alloc(amr->amr_dmat, size, PAGE_SIZE, 0, 339 &amr->amr_dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 340 aprint_error("%s: unable to allocate buffer, rv = %d\n", 341 amr->amr_dv.dv_xname, rv); 342 amr_teardown(amr); 343 return; 344 } 345 amr->amr_flags |= AMRF_DMA_ALLOC; 346 347 if ((rv = bus_dmamem_map(amr->amr_dmat, &amr->amr_dmaseg, rseg, size, 348 (caddr_t *)&amr->amr_mbox, 349 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 350 aprint_error("%s: unable to map buffer, rv = %d\n", 351 amr->amr_dv.dv_xname, rv); 352 amr_teardown(amr); 353 return; 354 } 355 amr->amr_flags |= AMRF_DMA_MAP; 356 357 if ((rv = bus_dmamap_create(amr->amr_dmat, size, 1, size, 0, 358 BUS_DMA_NOWAIT, &amr->amr_dmamap)) != 0) { 359 aprint_error("%s: unable to create buffer DMA map, rv = %d\n", 360 amr->amr_dv.dv_xname, rv); 361 amr_teardown(amr); 362 return; 363 } 364 amr->amr_flags |= AMRF_DMA_CREATE; 365 366 if ((rv = bus_dmamap_load(amr->amr_dmat, amr->amr_dmamap, 367 amr->amr_mbox, size, NULL, BUS_DMA_NOWAIT)) != 0) { 368 aprint_error("%s: unable to load buffer DMA map, rv = %d\n", 369 amr->amr_dv.dv_xname, rv); 370 amr_teardown(amr); 371 return; 372 } 373 amr->amr_flags |= AMRF_DMA_LOAD; 374 375 memset(amr->amr_mbox, 0, size); 376 377 amr->amr_mbox_paddr = amr->amr_dmamap->dm_segs[0].ds_addr; 378 amr->amr_sgls_paddr = (amr->amr_mbox_paddr + 0x1fff) & ~0x1fff; 379 amr->amr_sgls = (struct amr_sgentry *)((caddr_t)amr->amr_mbox + 380 amr->amr_sgls_paddr - amr->amr_dmamap->dm_segs[0].ds_addr); 381 382 /* 383 * Allocate and initalise the command control blocks. 384 */ 385 ac = malloc(sizeof(*ac) * AMR_MAX_CMDS, M_DEVBUF, M_NOWAIT | M_ZERO); 386 amr->amr_ccbs = ac; 387 SLIST_INIT(&amr->amr_ccb_freelist); 388 TAILQ_INIT(&amr->amr_ccb_active); 389 amr->amr_flags |= AMRF_CCBS; 390 391 if (amr_max_xfer == 0) { 392 amr_max_xfer = min(((AMR_MAX_SEGS - 1) * PAGE_SIZE), MAXPHYS); 393 amr_max_segs = (amr_max_xfer + (PAGE_SIZE * 2) - 1) / PAGE_SIZE; 394 } 395 396 for (i = 0; i < AMR_MAX_CMDS; i++, ac++) { 397 rv = bus_dmamap_create(amr->amr_dmat, amr_max_xfer, 398 amr_max_segs, amr_max_xfer, 0, 399 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ac->ac_xfer_map); 400 if (rv != 0) 401 break; 402 403 ac->ac_ident = i; 404 amr_ccb_free(amr, ac); 405 } 406 if (i != AMR_MAX_CMDS) { 407 aprint_error("%s: memory exhausted\n", amr->amr_dv.dv_xname); 408 amr_teardown(amr); 409 return; 410 } 411 412 /* 413 * Take care of model-specific tasks. 414 */ 415 if ((apt->apt_flags & AT_QUARTZ) != 0) { 416 amr->amr_submit = amr_quartz_submit; 417 amr->amr_get_work = amr_quartz_get_work; 418 } else { 419 amr->amr_submit = amr_std_submit; 420 amr->amr_get_work = amr_std_get_work; 421 422 /* Notify the controller of the mailbox location. */ 423 amr_outl(amr, AMR_SREG_MBOX, (u_int32_t)amr->amr_mbox_paddr + 16); 424 amr_outb(amr, AMR_SREG_MBOX_ENABLE, AMR_SMBOX_ENABLE_ADDR); 425 426 /* Clear outstanding interrupts and enable interrupts. */ 427 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 428 amr_outb(amr, AMR_SREG_TOGL, 429 amr_inb(amr, AMR_SREG_TOGL) | AMR_STOGL_ENABLE); 430 } 431 432 /* 433 * Retrieve parameters, and tell the world about us. 434 */ 435 amr->amr_enqbuf = malloc(AMR_ENQUIRY_BUFSIZE, M_DEVBUF, M_NOWAIT); 436 amr->amr_flags |= AMRF_ENQBUF; 437 amr->amr_maxqueuecnt = i; 438 aprint_normal(": AMI RAID "); 439 if (amr_init(amr, intrstr, pa) != 0) { 440 amr_teardown(amr); 441 return; 442 } 443 444 /* 445 * Cap the maximum number of outstanding commands. AMI's Linux 446 * driver doesn't trust the controller's reported value, and lockups 447 * have been seen when we do. 448 */ 449 amr->amr_maxqueuecnt = min(amr->amr_maxqueuecnt, AMR_MAX_CMDS); 450 if (amr->amr_maxqueuecnt > i) 451 amr->amr_maxqueuecnt = i; 452 453 /* Set our `shutdownhook' before we start any device activity. */ 454 if (amr_sdh == NULL) 455 amr_sdh = shutdownhook_establish(amr_shutdown, NULL); 456 457 /* Attach sub-devices. */ 458 for (j = 0; j < amr->amr_numdrives; j++) { 459 if (amr->amr_drive[j].al_size == 0) 460 continue; 461 amra.amra_unit = j; 462 amr->amr_drive[j].al_dv = config_found_sm(&amr->amr_dv, &amra, 463 amr_print, amr_submatch); 464 } 465 466 SIMPLEQ_INIT(&amr->amr_ccb_queue); 467 468 /* XXX This doesn't work for newer boards yet. */ 469 if ((apt->apt_flags & AT_QUARTZ) == 0) 470 kthread_create(amr_thread_create, amr); 471 } 472 473 /* 474 * Free up resources. 475 */ 476 void 477 amr_teardown(struct amr_softc *amr) 478 { 479 struct amr_ccb *ac; 480 int fl; 481 482 fl = amr->amr_flags; 483 484 if ((fl & AMRF_THREAD) != 0) { 485 amr->amr_flags |= AMRF_THREAD_EXIT; 486 wakeup(amr_thread); 487 while ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) 488 tsleep(&amr->amr_flags, PWAIT, "amrexit", 0); 489 } 490 if ((fl & AMRF_CCBS) != 0) { 491 SLIST_FOREACH(ac, &amr->amr_ccb_freelist, ac_chain.slist) { 492 bus_dmamap_destroy(amr->amr_dmat, ac->ac_xfer_map); 493 } 494 free(amr->amr_ccbs, M_DEVBUF); 495 } 496 if ((fl & AMRF_ENQBUF) != 0) 497 free(amr->amr_enqbuf, M_DEVBUF); 498 if ((fl & AMRF_DMA_LOAD) != 0) 499 bus_dmamap_unload(amr->amr_dmat, amr->amr_dmamap); 500 if ((fl & AMRF_DMA_MAP) != 0) 501 bus_dmamem_unmap(amr->amr_dmat, (caddr_t)amr->amr_mbox, 502 amr->amr_dmasize); 503 if ((fl & AMRF_DMA_ALLOC) != 0) 504 bus_dmamem_free(amr->amr_dmat, &amr->amr_dmaseg, 1); 505 if ((fl & AMRF_DMA_CREATE) != 0) 506 bus_dmamap_destroy(amr->amr_dmat, amr->amr_dmamap); 507 if ((fl & AMRF_PCI_INTR) != 0) 508 pci_intr_disestablish(amr->amr_pc, amr->amr_ih); 509 if ((fl & AMRF_PCI_REGS) != 0) 510 bus_space_unmap(amr->amr_iot, amr->amr_ioh, amr->amr_ios); 511 } 512 513 /* 514 * Print autoconfiguration message for a sub-device. 515 */ 516 int 517 amr_print(void *aux, const char *pnp) 518 { 519 struct amr_attach_args *amra; 520 521 amra = (struct amr_attach_args *)aux; 522 523 if (pnp != NULL) 524 aprint_normal("block device at %s", pnp); 525 aprint_normal(" unit %d", amra->amra_unit); 526 return (UNCONF); 527 } 528 529 /* 530 * Match a sub-device. 531 */ 532 int 533 amr_submatch(struct device *parent, struct cfdata *cf, void *aux) 534 { 535 struct amr_attach_args *amra; 536 537 amra = (struct amr_attach_args *)aux; 538 539 if (cf->amracf_unit != AMRCF_UNIT_DEFAULT && 540 cf->amracf_unit != amra->amra_unit) 541 return (0); 542 543 return (config_match(parent, cf, aux)); 544 } 545 546 /* 547 * Retrieve operational parameters and describe the controller. 548 */ 549 int 550 amr_init(struct amr_softc *amr, const char *intrstr, 551 struct pci_attach_args *pa) 552 { 553 struct amr_adapter_info *aa; 554 struct amr_prodinfo *ap; 555 struct amr_enquiry *ae; 556 struct amr_enquiry3 *aex; 557 const char *prodstr; 558 u_int i, sig, ishp; 559 char buf[64]; 560 561 /* 562 * Try to get 40LD product info, which tells us what the card is 563 * labelled as. 564 */ 565 ap = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_PRODUCT_INFO, 0, 566 amr->amr_enqbuf); 567 if (ap != NULL) { 568 aprint_normal("<%.80s>\n", ap->ap_product); 569 if (intrstr != NULL) 570 aprint_normal("%s: interrupting at %s\n", 571 amr->amr_dv.dv_xname, intrstr); 572 aprint_normal("%s: firmware %.16s, BIOS %.16s, %dMB RAM\n", 573 amr->amr_dv.dv_xname, ap->ap_firmware, ap->ap_bios, 574 le16toh(ap->ap_memsize)); 575 576 amr->amr_maxqueuecnt = ap->ap_maxio; 577 578 /* 579 * Fetch and record state of logical drives. 580 */ 581 aex = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_ENQ3, 582 AMR_CONFIG_ENQ3_SOLICITED_FULL, amr->amr_enqbuf); 583 if (aex == NULL) { 584 aprint_error("%s ENQUIRY3 failed\n", 585 amr->amr_dv.dv_xname); 586 return (-1); 587 } 588 589 if (aex->ae_numldrives > AMR_MAX_UNITS) { 590 aprint_error( 591 "%s: adjust AMR_MAX_UNITS to %d (currently %d)" 592 "\n", amr->amr_dv.dv_xname, AMR_MAX_UNITS, 593 amr->amr_numdrives); 594 amr->amr_numdrives = AMR_MAX_UNITS; 595 } else 596 amr->amr_numdrives = aex->ae_numldrives; 597 598 for (i = 0; i < amr->amr_numdrives; i++) { 599 amr->amr_drive[i].al_size = 600 le32toh(aex->ae_drivesize[i]); 601 amr->amr_drive[i].al_state = aex->ae_drivestate[i]; 602 amr->amr_drive[i].al_properties = aex->ae_driveprop[i]; 603 } 604 605 return (0); 606 } 607 608 /* 609 * Try 8LD extended ENQUIRY to get the controller signature. Once 610 * found, search for a product description. 611 */ 612 ae = amr_enquire(amr, AMR_CMD_EXT_ENQUIRY2, 0, 0, amr->amr_enqbuf); 613 if (ae != NULL) { 614 i = 0; 615 sig = le32toh(ae->ae_signature); 616 617 while (i < sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 618 if (amr_typestr[i].at_sig == sig) 619 break; 620 i++; 621 } 622 if (i == sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 623 sprintf(buf, "unknown ENQUIRY2 sig (0x%08x)", sig); 624 prodstr = buf; 625 } else 626 prodstr = amr_typestr[i].at_str; 627 } else { 628 ae = amr_enquire(amr, AMR_CMD_ENQUIRY, 0, 0, amr->amr_enqbuf); 629 if (ae == NULL) { 630 aprint_error("%s: unsupported controller\n", 631 amr->amr_dv.dv_xname); 632 return (-1); 633 } 634 635 switch (PCI_PRODUCT(pa->pa_id)) { 636 case PCI_PRODUCT_AMI_MEGARAID: 637 prodstr = "Series 428"; 638 break; 639 case PCI_PRODUCT_AMI_MEGARAID2: 640 prodstr = "Series 434"; 641 break; 642 default: 643 sprintf(buf, "unknown PCI dev (0x%04x)", 644 PCI_PRODUCT(pa->pa_id)); 645 prodstr = buf; 646 break; 647 } 648 } 649 650 /* 651 * HP NetRaid controllers have a special encoding of the firmware 652 * and BIOS versions. The AMI version seems to have it as strings 653 * whereas the HP version does it with a leading uppercase character 654 * and two binary numbers. 655 */ 656 aa = &ae->ae_adapter; 657 658 if (aa->aa_firmware[2] >= 'A' && aa->aa_firmware[2] <= 'Z' && 659 aa->aa_firmware[1] < ' ' && aa->aa_firmware[0] < ' ' && 660 aa->aa_bios[2] >= 'A' && aa->aa_bios[2] <= 'Z' && 661 aa->aa_bios[1] < ' ' && aa->aa_bios[0] < ' ') { 662 if (le32toh(ae->ae_signature) == AMR_SIG_438) { 663 /* The AMI 438 is a NetRaid 3si in HP-land. */ 664 prodstr = "HP NetRaid 3si"; 665 } 666 ishp = 1; 667 } else 668 ishp = 0; 669 670 aprint_normal("<%s>\n", prodstr); 671 if (intrstr != NULL) 672 aprint_normal("%s: interrupting at %s\n", amr->amr_dv.dv_xname, 673 intrstr); 674 675 if (ishp) 676 aprint_normal("%s: firmware <%c.%02d.%02d>, BIOS <%c.%02d.%02d>" 677 ", %dMB RAM\n", amr->amr_dv.dv_xname, aa->aa_firmware[2], 678 aa->aa_firmware[1], aa->aa_firmware[0], aa->aa_bios[2], 679 aa->aa_bios[1], aa->aa_bios[0], aa->aa_memorysize); 680 else 681 aprint_normal("%s: firmware <%.4s>, BIOS <%.4s>, %dMB RAM\n", 682 amr->amr_dv.dv_xname, aa->aa_firmware, aa->aa_bios, 683 aa->aa_memorysize); 684 685 amr->amr_maxqueuecnt = aa->aa_maxio; 686 687 /* 688 * Record state of logical drives. 689 */ 690 if (ae->ae_ldrv.al_numdrives > AMR_MAX_UNITS) { 691 aprint_error("%s: adjust AMR_MAX_UNITS to %d (currently %d)\n", 692 amr->amr_dv.dv_xname, ae->ae_ldrv.al_numdrives, 693 AMR_MAX_UNITS); 694 amr->amr_numdrives = AMR_MAX_UNITS; 695 } else 696 amr->amr_numdrives = ae->ae_ldrv.al_numdrives; 697 698 for (i = 0; i < AMR_MAX_UNITS; i++) { 699 amr->amr_drive[i].al_size = le32toh(ae->ae_ldrv.al_size[i]); 700 amr->amr_drive[i].al_state = ae->ae_ldrv.al_state[i]; 701 amr->amr_drive[i].al_properties = ae->ae_ldrv.al_properties[i]; 702 } 703 704 return (0); 705 } 706 707 /* 708 * Flush the internal cache on each configured controller. Called at 709 * shutdown time. 710 */ 711 void 712 amr_shutdown(void *cookie) 713 { 714 extern struct cfdriver amr_cd; 715 struct amr_softc *amr; 716 struct amr_ccb *ac; 717 int i, rv, s; 718 719 for (i = 0; i < amr_cd.cd_ndevs; i++) { 720 if ((amr = device_lookup(&amr_cd, i)) == NULL) 721 continue; 722 723 if ((rv = amr_ccb_alloc(amr, &ac)) == 0) { 724 ac->ac_cmd.mb_command = AMR_CMD_FLUSH; 725 s = splbio(); 726 rv = amr_ccb_poll(amr, ac, 30000); 727 splx(s); 728 amr_ccb_free(amr, ac); 729 } 730 if (rv != 0) 731 printf("%s: unable to flush cache (%d)\n", 732 amr->amr_dv.dv_xname, rv); 733 } 734 } 735 736 /* 737 * Interrupt service routine. 738 */ 739 int 740 amr_intr(void *cookie) 741 { 742 struct amr_softc *amr; 743 struct amr_ccb *ac; 744 struct amr_mailbox_resp mbox; 745 u_int i, forus, idx; 746 747 amr = cookie; 748 forus = 0; 749 750 while ((*amr->amr_get_work)(amr, &mbox) == 0) { 751 /* Iterate over completed commands in this result. */ 752 for (i = 0; i < mbox.mb_nstatus; i++) { 753 idx = mbox.mb_completed[i] - 1; 754 ac = amr->amr_ccbs + idx; 755 756 if (idx >= amr->amr_maxqueuecnt) { 757 printf("%s: bad status (bogus ID: %u=%u)\n", 758 amr->amr_dv.dv_xname, i, idx); 759 continue; 760 } 761 762 if ((ac->ac_flags & AC_ACTIVE) == 0) { 763 printf("%s: bad status (not active; 0x04%x)\n", 764 amr->amr_dv.dv_xname, ac->ac_flags); 765 continue; 766 } 767 768 ac->ac_status = mbox.mb_status; 769 ac->ac_flags = (ac->ac_flags & ~AC_ACTIVE) | 770 AC_COMPLETE; 771 TAILQ_REMOVE(&amr->amr_ccb_active, ac, ac_chain.tailq); 772 773 if ((ac->ac_flags & AC_MOAN) != 0) 774 printf("%s: ccb %d completed\n", 775 amr->amr_dv.dv_xname, ac->ac_ident); 776 777 /* Pass notification to upper layers. */ 778 if (ac->ac_handler != NULL) 779 (*ac->ac_handler)(ac); 780 else 781 wakeup(ac); 782 } 783 forus = 1; 784 } 785 786 if (forus) 787 amr_ccb_enqueue(amr, NULL); 788 789 return (forus); 790 } 791 792 /* 793 * Create the watchdog thread. 794 */ 795 void 796 amr_thread_create(void *cookie) 797 { 798 struct amr_softc *amr; 799 int rv; 800 801 amr = cookie; 802 803 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 804 amr->amr_flags ^= AMRF_THREAD_EXIT; 805 wakeup(&amr->amr_flags); 806 return; 807 } 808 809 rv = kthread_create1(amr_thread, amr, &amr->amr_thread, "%s", 810 amr->amr_dv.dv_xname); 811 if (rv != 0) 812 aprint_error("%s: unable to create thread (%d)", 813 amr->amr_dv.dv_xname, rv); 814 else 815 amr->amr_flags |= AMRF_THREAD; 816 } 817 818 /* 819 * Watchdog thread. 820 */ 821 void 822 amr_thread(void *cookie) 823 { 824 struct amr_softc *amr; 825 struct amr_ccb *ac; 826 struct amr_logdrive *al; 827 struct amr_enquiry *ae; 828 time_t curtime; 829 int rv, i, s; 830 831 amr = cookie; 832 ae = amr->amr_enqbuf; 833 834 for (;;) { 835 tsleep(amr_thread, PWAIT, "amrwdog", AMR_WDOG_TICKS); 836 837 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 838 amr->amr_flags ^= AMRF_THREAD_EXIT; 839 wakeup(&amr->amr_flags); 840 kthread_exit(0); 841 } 842 843 s = splbio(); 844 amr_intr(cookie); 845 curtime = (time_t)mono_time.tv_sec; 846 ac = TAILQ_FIRST(&amr->amr_ccb_active); 847 while (ac != NULL) { 848 if (ac->ac_start_time + AMR_TIMEOUT > curtime) 849 break; 850 if ((ac->ac_flags & AC_MOAN) == 0) { 851 printf("%s: ccb %d timed out; mailbox:\n", 852 amr->amr_dv.dv_xname, ac->ac_ident); 853 amr_ccb_dump(amr, ac); 854 ac->ac_flags |= AC_MOAN; 855 } 856 ac = TAILQ_NEXT(ac, ac_chain.tailq); 857 } 858 splx(s); 859 860 if ((rv = amr_ccb_alloc(amr, &ac)) != 0) { 861 printf("%s: ccb_alloc failed (%d)\n", 862 amr->amr_dv.dv_xname, rv); 863 continue; 864 } 865 866 ac->ac_cmd.mb_command = AMR_CMD_ENQUIRY; 867 868 rv = amr_ccb_map(amr, ac, amr->amr_enqbuf, 869 AMR_ENQUIRY_BUFSIZE, 0); 870 if (rv != 0) { 871 printf("%s: ccb_map failed (%d)\n", 872 amr->amr_dv.dv_xname, rv); 873 amr_ccb_free(amr, ac); 874 continue; 875 } 876 877 rv = amr_ccb_wait(amr, ac); 878 amr_ccb_unmap(amr, ac); 879 if (rv != 0) { 880 printf("%s: enquiry failed (st=%d)\n", 881 amr->amr_dv.dv_xname, ac->ac_status); 882 continue; 883 } 884 amr_ccb_free(amr, ac); 885 886 al = amr->amr_drive; 887 for (i = 0; i < AMR_MAX_UNITS; i++, al++) { 888 if (al->al_dv == NULL) 889 continue; 890 if (al->al_state == ae->ae_ldrv.al_state[i]) 891 continue; 892 893 printf("%s: state changed: %s -> %s\n", 894 al->al_dv->dv_xname, 895 amr_drive_state(al->al_state, NULL), 896 amr_drive_state(ae->ae_ldrv.al_state[i], NULL)); 897 898 al->al_state = ae->ae_ldrv.al_state[i]; 899 } 900 } 901 } 902 903 /* 904 * Return a text description of a logical drive's current state. 905 */ 906 const char * 907 amr_drive_state(int state, int *happy) 908 { 909 const char *str; 910 911 state = AMR_DRV_CURSTATE(state); 912 if (state >= sizeof(amr_dstate) / sizeof(amr_dstate[0])) { 913 if (happy) 914 *happy = 1; 915 str = "status unknown"; 916 } else { 917 if (happy) 918 *happy = amr_dstate[state].ds_happy; 919 str = amr_dstate[state].ds_descr; 920 } 921 922 return (str); 923 } 924 925 /* 926 * Run a generic enquiry-style command. 927 */ 928 void * 929 amr_enquire(struct amr_softc *amr, u_int8_t cmd, u_int8_t cmdsub, 930 u_int8_t cmdqual, void *buf) 931 { 932 struct amr_ccb *ac; 933 u_int8_t *mb; 934 int rv; 935 936 if (amr_ccb_alloc(amr, &ac) != 0) 937 return (NULL); 938 939 /* Build the command proper. */ 940 mb = (u_int8_t *)&ac->ac_cmd; 941 mb[0] = cmd; 942 mb[2] = cmdsub; 943 mb[3] = cmdqual; 944 945 rv = amr_ccb_map(amr, ac, buf, AMR_ENQUIRY_BUFSIZE, 0); 946 if (rv == 0) { 947 rv = amr_ccb_poll(amr, ac, 2000); 948 amr_ccb_unmap(amr, ac); 949 } 950 amr_ccb_free(amr, ac); 951 952 return (rv ? NULL : buf); 953 } 954 955 /* 956 * Allocate and initialise a CCB. 957 */ 958 int 959 amr_ccb_alloc(struct amr_softc *amr, struct amr_ccb **acp) 960 { 961 int s; 962 963 s = splbio(); 964 if ((*acp = SLIST_FIRST(&amr->amr_ccb_freelist)) == NULL) { 965 splx(s); 966 return (EAGAIN); 967 } 968 SLIST_REMOVE_HEAD(&amr->amr_ccb_freelist, ac_chain.slist); 969 splx(s); 970 971 return (0); 972 } 973 974 /* 975 * Free a CCB. 976 */ 977 void 978 amr_ccb_free(struct amr_softc *amr, struct amr_ccb *ac) 979 { 980 int s; 981 982 memset(&ac->ac_cmd, 0, sizeof(ac->ac_cmd)); 983 ac->ac_cmd.mb_ident = ac->ac_ident + 1; 984 ac->ac_cmd.mb_busy = 1; 985 ac->ac_handler = NULL; 986 ac->ac_flags = 0; 987 988 s = splbio(); 989 SLIST_INSERT_HEAD(&amr->amr_ccb_freelist, ac, ac_chain.slist); 990 splx(s); 991 } 992 993 /* 994 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 995 * the order that they were enqueued and try to submit their command blocks 996 * to the controller for execution. 997 */ 998 void 999 amr_ccb_enqueue(struct amr_softc *amr, struct amr_ccb *ac) 1000 { 1001 int s; 1002 1003 s = splbio(); 1004 1005 if (ac != NULL) 1006 SIMPLEQ_INSERT_TAIL(&amr->amr_ccb_queue, ac, ac_chain.simpleq); 1007 1008 while ((ac = SIMPLEQ_FIRST(&amr->amr_ccb_queue)) != NULL) { 1009 if ((*amr->amr_submit)(amr, ac) != 0) 1010 break; 1011 SIMPLEQ_REMOVE_HEAD(&amr->amr_ccb_queue, ac_chain.simpleq); 1012 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1013 } 1014 1015 splx(s); 1016 } 1017 1018 /* 1019 * Map the specified CCB's data buffer onto the bus, and fill the 1020 * scatter-gather list. 1021 */ 1022 int 1023 amr_ccb_map(struct amr_softc *amr, struct amr_ccb *ac, void *data, int size, 1024 int out) 1025 { 1026 struct amr_sgentry *sge; 1027 struct amr_mailbox_cmd *mb; 1028 int nsegs, i, rv, sgloff; 1029 bus_dmamap_t xfer; 1030 1031 xfer = ac->ac_xfer_map; 1032 1033 rv = bus_dmamap_load(amr->amr_dmat, xfer, data, size, NULL, 1034 BUS_DMA_NOWAIT); 1035 if (rv != 0) 1036 return (rv); 1037 1038 mb = &ac->ac_cmd; 1039 ac->ac_xfer_size = size; 1040 ac->ac_flags |= (out ? AC_XFER_OUT : AC_XFER_IN); 1041 sgloff = AMR_SGL_SIZE * ac->ac_ident; 1042 1043 /* We don't need to use a scatter/gather list for just 1 segment. */ 1044 nsegs = xfer->dm_nsegs; 1045 if (nsegs == 1) { 1046 mb->mb_nsgelem = 0; 1047 mb->mb_physaddr = htole32(xfer->dm_segs[0].ds_addr); 1048 ac->ac_flags |= AC_NOSGL; 1049 } else { 1050 mb->mb_nsgelem = nsegs; 1051 mb->mb_physaddr = htole32(amr->amr_sgls_paddr + sgloff); 1052 1053 sge = (struct amr_sgentry *)((caddr_t)amr->amr_sgls + sgloff); 1054 for (i = 0; i < nsegs; i++, sge++) { 1055 sge->sge_addr = htole32(xfer->dm_segs[i].ds_addr); 1056 sge->sge_count = htole32(xfer->dm_segs[i].ds_len); 1057 } 1058 } 1059 1060 bus_dmamap_sync(amr->amr_dmat, xfer, 0, ac->ac_xfer_size, 1061 out ? BUS_DMASYNC_PREWRITE : BUS_DMASYNC_PREREAD); 1062 1063 if ((ac->ac_flags & AC_NOSGL) == 0) 1064 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, sgloff, 1065 AMR_SGL_SIZE, BUS_DMASYNC_PREWRITE); 1066 1067 return (0); 1068 } 1069 1070 /* 1071 * Unmap the specified CCB's data buffer. 1072 */ 1073 void 1074 amr_ccb_unmap(struct amr_softc *amr, struct amr_ccb *ac) 1075 { 1076 1077 if ((ac->ac_flags & AC_NOSGL) == 0) 1078 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 1079 AMR_SGL_SIZE * ac->ac_ident, AMR_SGL_SIZE, 1080 BUS_DMASYNC_POSTWRITE); 1081 bus_dmamap_sync(amr->amr_dmat, ac->ac_xfer_map, 0, ac->ac_xfer_size, 1082 (ac->ac_flags & AC_XFER_IN) != 0 ? 1083 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1084 bus_dmamap_unload(amr->amr_dmat, ac->ac_xfer_map); 1085 } 1086 1087 /* 1088 * Submit a command to the controller and poll on completion. Return 1089 * non-zero on timeout or error. Must be called with interrupts blocked. 1090 */ 1091 int 1092 amr_ccb_poll(struct amr_softc *amr, struct amr_ccb *ac, int timo) 1093 { 1094 int rv; 1095 1096 if ((rv = (*amr->amr_submit)(amr, ac)) != 0) 1097 return (rv); 1098 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1099 1100 for (timo *= 10; timo != 0; timo--) { 1101 amr_intr(amr); 1102 if ((ac->ac_flags & AC_COMPLETE) != 0) 1103 break; 1104 DELAY(100); 1105 } 1106 1107 return (timo == 0 || ac->ac_status != 0 ? EIO : 0); 1108 } 1109 1110 /* 1111 * Submit a command to the controller and sleep on completion. Return 1112 * non-zero on error. 1113 */ 1114 int 1115 amr_ccb_wait(struct amr_softc *amr, struct amr_ccb *ac) 1116 { 1117 int s; 1118 1119 s = splbio(); 1120 amr_ccb_enqueue(amr, ac); 1121 tsleep(ac, PRIBIO, "amrcmd", 0); 1122 splx(s); 1123 1124 return (ac->ac_status != 0 ? EIO : 0); 1125 } 1126 1127 /* 1128 * Wait for the mailbox to become available. 1129 */ 1130 int 1131 amr_mbox_wait(struct amr_softc *amr) 1132 { 1133 int timo; 1134 1135 for (timo = 10000; timo != 0; timo--) { 1136 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1137 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1138 if (amr->amr_mbox->mb_cmd.mb_busy == 0) 1139 break; 1140 DELAY(100); 1141 } 1142 1143 if (timo == 0) 1144 printf("%s: controller wedged\n", amr->amr_dv.dv_xname); 1145 1146 return (timo != 0 ? 0 : EAGAIN); 1147 } 1148 1149 /* 1150 * Tell the controller that the mailbox contains a valid command. Must be 1151 * called with interrupts blocked. 1152 */ 1153 int 1154 amr_quartz_submit(struct amr_softc *amr, struct amr_ccb *ac) 1155 { 1156 u_int32_t v; 1157 1158 amr->amr_mbox->mb_poll = 0; 1159 amr->amr_mbox->mb_ack = 0; 1160 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1161 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1162 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1163 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1164 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1165 return (EAGAIN); 1166 1167 v = amr_inl(amr, AMR_QREG_IDB); 1168 if ((v & AMR_QIDB_SUBMIT) != 0) { 1169 amr->amr_mbox->mb_cmd.mb_busy = 0; 1170 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1171 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1172 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1173 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1174 return (EAGAIN); 1175 } 1176 1177 amr->amr_mbox->mb_segment = 0; 1178 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1179 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1180 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1181 1182 ac->ac_start_time = (time_t)mono_time.tv_sec; 1183 ac->ac_flags |= AC_ACTIVE; 1184 amr_outl(amr, AMR_QREG_IDB, 1185 (amr->amr_mbox_paddr + 16) | AMR_QIDB_SUBMIT); 1186 return (0); 1187 } 1188 1189 int 1190 amr_std_submit(struct amr_softc *amr, struct amr_ccb *ac) 1191 { 1192 1193 amr->amr_mbox->mb_poll = 0; 1194 amr->amr_mbox->mb_ack = 0; 1195 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1196 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1197 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1198 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1199 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1200 return (EAGAIN); 1201 1202 if ((amr_inb(amr, AMR_SREG_MBOX_BUSY) & AMR_SMBOX_BUSY_FLAG) != 0) { 1203 amr->amr_mbox->mb_cmd.mb_busy = 0; 1204 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1205 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1206 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1207 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1208 return (EAGAIN); 1209 } 1210 1211 amr->amr_mbox->mb_segment = 0; 1212 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1213 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1214 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1215 1216 ac->ac_start_time = (time_t)mono_time.tv_sec; 1217 ac->ac_flags |= AC_ACTIVE; 1218 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_POST); 1219 return (0); 1220 } 1221 1222 /* 1223 * Claim any work that the controller has completed; acknowledge completion, 1224 * save details of the completion in (mbsave). Must be called with 1225 * interrupts blocked. 1226 */ 1227 int 1228 amr_quartz_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1229 { 1230 1231 /* Work waiting for us? */ 1232 if (amr_inl(amr, AMR_QREG_ODB) != AMR_QODB_READY) 1233 return (-1); 1234 1235 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1236 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1237 1238 /* Save the mailbox, which contains a list of completed commands. */ 1239 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1240 1241 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1242 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1243 1244 /* Ack the interrupt and mailbox transfer. */ 1245 amr_outl(amr, AMR_QREG_ODB, AMR_QODB_READY); 1246 amr_outl(amr, AMR_QREG_IDB, (amr->amr_mbox_paddr+16) | AMR_QIDB_ACK); 1247 1248 /* 1249 * This waits for the controller to notice that we've taken the 1250 * command from it. It's very inefficient, and we shouldn't do it, 1251 * but if we remove this code, we stop completing commands under 1252 * load. 1253 * 1254 * Peter J says we shouldn't do this. The documentation says we 1255 * should. Who is right? 1256 */ 1257 while ((amr_inl(amr, AMR_QREG_IDB) & AMR_QIDB_ACK) != 0) 1258 DELAY(10); 1259 1260 return (0); 1261 } 1262 1263 int 1264 amr_std_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1265 { 1266 u_int8_t istat; 1267 1268 /* Check for valid interrupt status. */ 1269 if (((istat = amr_inb(amr, AMR_SREG_INTR)) & AMR_SINTR_VALID) == 0) 1270 return (-1); 1271 1272 /* Ack the interrupt. */ 1273 amr_outb(amr, AMR_SREG_INTR, istat); 1274 1275 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1276 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1277 1278 /* Save mailbox, which contains a list of completed commands. */ 1279 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1280 1281 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1282 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1283 1284 /* Ack mailbox transfer. */ 1285 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 1286 1287 return (0); 1288 } 1289 1290 void 1291 amr_ccb_dump(struct amr_softc *amr, struct amr_ccb *ac) 1292 { 1293 int i; 1294 1295 printf("%s: ", amr->amr_dv.dv_xname); 1296 for (i = 0; i < 4; i++) 1297 printf("%08x ", ((u_int32_t *)&ac->ac_cmd)[i]); 1298 printf("\n"); 1299 } 1300
Indexes created Thu Oct 02 14:10:14 GMT 2025