amr.c revision 1.19.2.2
1 /* $NetBSD: amr.c,v 1.19.2.2 2004/11/12 06:14:28 jmc Exp $ */ 2 3 /*- 4 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999,2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: amr_pci.c,v 1.5 2000/08/30 07:52:40 msmith Exp 66 * from FreeBSD: amr.c,v 1.16 2000/08/30 07:52:40 msmith Exp 67 */ 68 69 /* 70 * Driver for AMI RAID controllers. 71 */ 72 73 #include <sys/cdefs.h> 74 __KERNEL_RCSID(0, "$NetBSD: amr.c,v 1.19.2.2 2004/11/12 06:14:28 jmc Exp $"); 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/device.h> 80 #include <sys/queue.h> 81 #include <sys/proc.h> 82 #include <sys/buf.h> 83 #include <sys/malloc.h> 84 #include <sys/kthread.h> 85 86 #include <uvm/uvm_extern.h> 87 88 #include <machine/endian.h> 89 #include <machine/bus.h> 90 91 #include <dev/pci/pcidevs.h> 92 #include <dev/pci/pcivar.h> 93 #include <dev/pci/amrreg.h> 94 #include <dev/pci/amrvar.h> 95 96 void amr_attach(struct device *, struct device *, void *); 97 void amr_ccb_dump(struct amr_softc *, struct amr_ccb *); 98 void *amr_enquire(struct amr_softc *, u_int8_t, u_int8_t, u_int8_t, void *); 99 int amr_init(struct amr_softc *, const char *, 100 struct pci_attach_args *pa); 101 int amr_intr(void *); 102 int amr_match(struct device *, struct cfdata *, void *); 103 int amr_print(void *, const char *); 104 void amr_shutdown(void *); 105 int amr_submatch(struct device *, struct cfdata *, void *); 106 void amr_teardown(struct amr_softc *); 107 void amr_thread(void *); 108 void amr_thread_create(void *); 109 110 int amr_mbox_wait(struct amr_softc *); 111 int amr_quartz_get_work(struct amr_softc *, struct amr_mailbox_resp *); 112 int amr_quartz_submit(struct amr_softc *, struct amr_ccb *); 113 int amr_std_get_work(struct amr_softc *, struct amr_mailbox_resp *); 114 int amr_std_submit(struct amr_softc *, struct amr_ccb *); 115 116 static inline u_int8_t amr_inb(struct amr_softc *, int); 117 static inline u_int32_t amr_inl(struct amr_softc *, int); 118 static inline void amr_outb(struct amr_softc *, int, u_int8_t); 119 static inline void amr_outl(struct amr_softc *, int, u_int32_t); 120 121 CFATTACH_DECL(amr, sizeof(struct amr_softc), 122 amr_match, amr_attach, NULL, NULL); 123 124 #define AT_QUARTZ 0x01 /* `Quartz' chipset */ 125 #define AT_SIG 0x02 /* Check for signature */ 126 127 struct amr_pci_type { 128 u_short apt_vendor; 129 u_short apt_product; 130 u_short apt_flags; 131 } const amr_pci_type[] = { 132 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID, 0 }, 133 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID2, 0 }, 134 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 135 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ | AT_SIG }, 137 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI, AT_QUARTZ }, 138 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI_2, AT_QUARTZ }, 139 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4ESI, AT_QUARTZ }, 140 }; 141 142 struct amr_typestr { 143 const char *at_str; 144 int at_sig; 145 } const amr_typestr[] = { 146 { "Series 431", AMR_SIG_431 }, 147 { "Series 438", AMR_SIG_438 }, 148 { "Series 466", AMR_SIG_466 }, 149 { "Series 467", AMR_SIG_467 }, 150 { "Series 490", AMR_SIG_490 }, 151 { "Series 762", AMR_SIG_762 }, 152 { "HP NetRAID (T5)", AMR_SIG_T5 }, 153 { "HP NetRAID (T7)", AMR_SIG_T7 }, 154 }; 155 156 struct { 157 const char *ds_descr; 158 int ds_happy; 159 } const amr_dstate[] = { 160 { "offline", 0 }, 161 { "degraded", 1 }, 162 { "optimal", 1 }, 163 { "online", 1 }, 164 { "failed", 0 }, 165 { "rebuilding", 1 }, 166 { "hotspare", 0 }, 167 }; 168 169 void *amr_sdh; 170 int amr_max_segs; 171 int amr_max_xfer; 172 173 static inline u_int8_t 174 amr_inb(struct amr_softc *amr, int off) 175 { 176 177 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 178 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 179 return (bus_space_read_1(amr->amr_iot, amr->amr_ioh, off)); 180 } 181 182 static inline u_int32_t 183 amr_inl(struct amr_softc *amr, int off) 184 { 185 186 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 187 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 188 return (bus_space_read_4(amr->amr_iot, amr->amr_ioh, off)); 189 } 190 191 static inline void 192 amr_outb(struct amr_softc *amr, int off, u_int8_t val) 193 { 194 195 bus_space_write_1(amr->amr_iot, amr->amr_ioh, off, val); 196 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 197 BUS_SPACE_BARRIER_WRITE); 198 } 199 200 static inline void 201 amr_outl(struct amr_softc *amr, int off, u_int32_t val) 202 { 203 204 bus_space_write_4(amr->amr_iot, amr->amr_ioh, off, val); 205 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 206 BUS_SPACE_BARRIER_WRITE); 207 } 208 209 /* 210 * Match a supported device. 211 */ 212 int 213 amr_match(struct device *parent, struct cfdata *match, void *aux) 214 { 215 struct pci_attach_args *pa; 216 pcireg_t s; 217 int i; 218 219 pa = (struct pci_attach_args *)aux; 220 221 /* 222 * Don't match the device if it's operating in I2O mode. In this 223 * case it should be handled by the `iop' driver. 224 */ 225 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 226 return (0); 227 228 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 229 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 230 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 231 break; 232 233 if (i == sizeof(amr_pci_type) / sizeof(amr_pci_type[0])) 234 return (0); 235 236 if ((amr_pci_type[i].apt_flags & AT_SIG) == 0) 237 return (1); 238 239 s = pci_conf_read(pa->pa_pc, pa->pa_tag, AMR_QUARTZ_SIG_REG) & 0xffff; 240 return (s == AMR_QUARTZ_SIG0 || s == AMR_QUARTZ_SIG1); 241 } 242 243 /* 244 * Attach a supported device. 245 */ 246 void 247 amr_attach(struct device *parent, struct device *self, void *aux) 248 { 249 struct pci_attach_args *pa; 250 struct amr_attach_args amra; 251 const struct amr_pci_type *apt; 252 struct amr_softc *amr; 253 pci_chipset_tag_t pc; 254 pci_intr_handle_t ih; 255 const char *intrstr; 256 pcireg_t reg; 257 int rseg, i, j, size, rv, memreg, ioreg; 258 struct amr_ccb *ac; 259 260 aprint_naive(": RAID controller\n"); 261 262 amr = (struct amr_softc *)self; 263 pa = (struct pci_attach_args *)aux; 264 pc = pa->pa_pc; 265 266 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 267 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 268 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 269 break; 270 apt = amr_pci_type + i; 271 272 memreg = ioreg = 0; 273 for (i = 0x10; i <= 0x14; i += 4) { 274 reg = pci_conf_read(pc, pa->pa_tag, i); 275 switch (PCI_MAPREG_TYPE(reg)) { 276 case PCI_MAPREG_TYPE_MEM: 277 if (PCI_MAPREG_MEM_SIZE(reg) != 0) 278 memreg = i; 279 break; 280 case PCI_MAPREG_TYPE_IO: 281 if (PCI_MAPREG_IO_SIZE(reg) != 0) 282 ioreg = i; 283 break; 284 285 } 286 } 287 288 if (memreg && pci_mapreg_map(pa, memreg, PCI_MAPREG_TYPE_MEM, 0, 289 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 290 ; 291 else if (ioreg && pci_mapreg_map(pa, ioreg, PCI_MAPREG_TYPE_IO, 0, 292 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 293 ; 294 else { 295 aprint_error("can't map control registers\n"); 296 amr_teardown(amr); 297 return; 298 } 299 300 amr->amr_flags |= AMRF_PCI_REGS; 301 amr->amr_dmat = pa->pa_dmat; 302 amr->amr_pc = pa->pa_pc; 303 304 /* Enable the device. */ 305 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 306 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 307 reg | PCI_COMMAND_MASTER_ENABLE); 308 309 /* Map and establish the interrupt. */ 310 if (pci_intr_map(pa, &ih)) { 311 aprint_error("can't map interrupt\n"); 312 amr_teardown(amr); 313 return; 314 } 315 intrstr = pci_intr_string(pc, ih); 316 amr->amr_ih = pci_intr_establish(pc, ih, IPL_BIO, amr_intr, amr); 317 if (amr->amr_ih == NULL) { 318 aprint_error("can't establish interrupt"); 319 if (intrstr != NULL) 320 aprint_normal(" at %s", intrstr); 321 aprint_normal("\n"); 322 amr_teardown(amr); 323 return; 324 } 325 amr->amr_flags |= AMRF_PCI_INTR; 326 327 /* 328 * Allocate space for the mailbox and S/G lists. Some controllers 329 * don't like S/G lists to be located below 0x2000, so we allocate 330 * enough slop to enable us to compensate. 331 * 332 * The standard mailbox structure needs to be aligned on a 16-byte 333 * boundary. The 64-bit mailbox has one extra field, 4 bytes in 334 * size, which preceeds the standard mailbox. 335 */ 336 size = AMR_SGL_SIZE * AMR_MAX_CMDS + 0x2000; 337 amr->amr_dmasize = size; 338 339 if ((rv = bus_dmamem_alloc(amr->amr_dmat, size, PAGE_SIZE, 0, 340 &amr->amr_dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 341 aprint_error("%s: unable to allocate buffer, rv = %d\n", 342 amr->amr_dv.dv_xname, rv); 343 amr_teardown(amr); 344 return; 345 } 346 amr->amr_flags |= AMRF_DMA_ALLOC; 347 348 if ((rv = bus_dmamem_map(amr->amr_dmat, &amr->amr_dmaseg, rseg, size, 349 (caddr_t *)&amr->amr_mbox, 350 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 351 aprint_error("%s: unable to map buffer, rv = %d\n", 352 amr->amr_dv.dv_xname, rv); 353 amr_teardown(amr); 354 return; 355 } 356 amr->amr_flags |= AMRF_DMA_MAP; 357 358 if ((rv = bus_dmamap_create(amr->amr_dmat, size, 1, size, 0, 359 BUS_DMA_NOWAIT, &amr->amr_dmamap)) != 0) { 360 aprint_error("%s: unable to create buffer DMA map, rv = %d\n", 361 amr->amr_dv.dv_xname, rv); 362 amr_teardown(amr); 363 return; 364 } 365 amr->amr_flags |= AMRF_DMA_CREATE; 366 367 if ((rv = bus_dmamap_load(amr->amr_dmat, amr->amr_dmamap, 368 amr->amr_mbox, size, NULL, BUS_DMA_NOWAIT)) != 0) { 369 aprint_error("%s: unable to load buffer DMA map, rv = %d\n", 370 amr->amr_dv.dv_xname, rv); 371 amr_teardown(amr); 372 return; 373 } 374 amr->amr_flags |= AMRF_DMA_LOAD; 375 376 memset(amr->amr_mbox, 0, size); 377 378 amr->amr_mbox_paddr = amr->amr_dmamap->dm_segs[0].ds_addr; 379 amr->amr_sgls_paddr = (amr->amr_mbox_paddr + 0x1fff) & ~0x1fff; 380 amr->amr_sgls = (struct amr_sgentry *)((caddr_t)amr->amr_mbox + 381 amr->amr_sgls_paddr - amr->amr_dmamap->dm_segs[0].ds_addr); 382 383 /* 384 * Allocate and initalise the command control blocks. 385 */ 386 ac = malloc(sizeof(*ac) * AMR_MAX_CMDS, M_DEVBUF, M_NOWAIT | M_ZERO); 387 amr->amr_ccbs = ac; 388 SLIST_INIT(&amr->amr_ccb_freelist); 389 TAILQ_INIT(&amr->amr_ccb_active); 390 amr->amr_flags |= AMRF_CCBS; 391 392 if (amr_max_xfer == 0) { 393 amr_max_xfer = min(((AMR_MAX_SEGS - 1) * PAGE_SIZE), MAXPHYS); 394 amr_max_segs = (amr_max_xfer + (PAGE_SIZE * 2) - 1) / PAGE_SIZE; 395 } 396 397 for (i = 0; i < AMR_MAX_CMDS; i++, ac++) { 398 rv = bus_dmamap_create(amr->amr_dmat, amr_max_xfer, 399 amr_max_segs, amr_max_xfer, 0, 400 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ac->ac_xfer_map); 401 if (rv != 0) 402 break; 403 404 ac->ac_ident = i; 405 amr_ccb_free(amr, ac); 406 } 407 if (i != AMR_MAX_CMDS) { 408 aprint_error("%s: memory exhausted\n", amr->amr_dv.dv_xname); 409 amr_teardown(amr); 410 return; 411 } 412 413 /* 414 * Take care of model-specific tasks. 415 */ 416 if ((apt->apt_flags & AT_QUARTZ) != 0) { 417 amr->amr_submit = amr_quartz_submit; 418 amr->amr_get_work = amr_quartz_get_work; 419 } else { 420 amr->amr_submit = amr_std_submit; 421 amr->amr_get_work = amr_std_get_work; 422 423 /* Notify the controller of the mailbox location. */ 424 amr_outl(amr, AMR_SREG_MBOX, (u_int32_t)amr->amr_mbox_paddr + 16); 425 amr_outb(amr, AMR_SREG_MBOX_ENABLE, AMR_SMBOX_ENABLE_ADDR); 426 427 /* Clear outstanding interrupts and enable interrupts. */ 428 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 429 amr_outb(amr, AMR_SREG_TOGL, 430 amr_inb(amr, AMR_SREG_TOGL) | AMR_STOGL_ENABLE); 431 } 432 433 /* 434 * Retrieve parameters, and tell the world about us. 435 */ 436 amr->amr_enqbuf = malloc(AMR_ENQUIRY_BUFSIZE, M_DEVBUF, M_NOWAIT); 437 amr->amr_flags |= AMRF_ENQBUF; 438 amr->amr_maxqueuecnt = i; 439 aprint_normal(": AMI RAID "); 440 if (amr_init(amr, intrstr, pa) != 0) { 441 amr_teardown(amr); 442 return; 443 } 444 445 /* 446 * Cap the maximum number of outstanding commands. AMI's Linux 447 * driver doesn't trust the controller's reported value, and lockups 448 * have been seen when we do. 449 */ 450 amr->amr_maxqueuecnt = min(amr->amr_maxqueuecnt, AMR_MAX_CMDS); 451 if (amr->amr_maxqueuecnt > i) 452 amr->amr_maxqueuecnt = i; 453 454 /* Set our `shutdownhook' before we start any device activity. */ 455 if (amr_sdh == NULL) 456 amr_sdh = shutdownhook_establish(amr_shutdown, NULL); 457 458 /* Attach sub-devices. */ 459 for (j = 0; j < amr->amr_numdrives; j++) { 460 if (amr->amr_drive[j].al_size == 0) 461 continue; 462 amra.amra_unit = j; 463 amr->amr_drive[j].al_dv = config_found_sm(&amr->amr_dv, &amra, 464 amr_print, amr_submatch); 465 } 466 467 SIMPLEQ_INIT(&amr->amr_ccb_queue); 468 469 /* XXX This doesn't work for newer boards yet. */ 470 if ((apt->apt_flags & AT_QUARTZ) == 0) 471 kthread_create(amr_thread_create, amr); 472 } 473 474 /* 475 * Free up resources. 476 */ 477 void 478 amr_teardown(struct amr_softc *amr) 479 { 480 struct amr_ccb *ac; 481 int fl; 482 483 fl = amr->amr_flags; 484 485 if ((fl & AMRF_THREAD) != 0) { 486 amr->amr_flags |= AMRF_THREAD_EXIT; 487 wakeup(amr_thread); 488 while ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) 489 tsleep(&amr->amr_flags, PWAIT, "amrexit", 0); 490 } 491 if ((fl & AMRF_CCBS) != 0) { 492 SLIST_FOREACH(ac, &amr->amr_ccb_freelist, ac_chain.slist) { 493 bus_dmamap_destroy(amr->amr_dmat, ac->ac_xfer_map); 494 } 495 free(amr->amr_ccbs, M_DEVBUF); 496 } 497 if ((fl & AMRF_ENQBUF) != 0) 498 free(amr->amr_enqbuf, M_DEVBUF); 499 if ((fl & AMRF_DMA_LOAD) != 0) 500 bus_dmamap_unload(amr->amr_dmat, amr->amr_dmamap); 501 if ((fl & AMRF_DMA_MAP) != 0) 502 bus_dmamem_unmap(amr->amr_dmat, (caddr_t)amr->amr_mbox, 503 amr->amr_dmasize); 504 if ((fl & AMRF_DMA_ALLOC) != 0) 505 bus_dmamem_free(amr->amr_dmat, &amr->amr_dmaseg, 1); 506 if ((fl & AMRF_DMA_CREATE) != 0) 507 bus_dmamap_destroy(amr->amr_dmat, amr->amr_dmamap); 508 if ((fl & AMRF_PCI_INTR) != 0) 509 pci_intr_disestablish(amr->amr_pc, amr->amr_ih); 510 if ((fl & AMRF_PCI_REGS) != 0) 511 bus_space_unmap(amr->amr_iot, amr->amr_ioh, amr->amr_ios); 512 } 513 514 /* 515 * Print autoconfiguration message for a sub-device. 516 */ 517 int 518 amr_print(void *aux, const char *pnp) 519 { 520 struct amr_attach_args *amra; 521 522 amra = (struct amr_attach_args *)aux; 523 524 if (pnp != NULL) 525 aprint_normal("block device at %s", pnp); 526 aprint_normal(" unit %d", amra->amra_unit); 527 return (UNCONF); 528 } 529 530 /* 531 * Match a sub-device. 532 */ 533 int 534 amr_submatch(struct device *parent, struct cfdata *cf, void *aux) 535 { 536 struct amr_attach_args *amra; 537 538 amra = (struct amr_attach_args *)aux; 539 540 if (cf->amracf_unit != AMRCF_UNIT_DEFAULT && 541 cf->amracf_unit != amra->amra_unit) 542 return (0); 543 544 return (config_match(parent, cf, aux)); 545 } 546 547 /* 548 * Retrieve operational parameters and describe the controller. 549 */ 550 int 551 amr_init(struct amr_softc *amr, const char *intrstr, 552 struct pci_attach_args *pa) 553 { 554 struct amr_adapter_info *aa; 555 struct amr_prodinfo *ap; 556 struct amr_enquiry *ae; 557 struct amr_enquiry3 *aex; 558 const char *prodstr; 559 u_int i, sig, ishp; 560 char buf[64]; 561 562 /* 563 * Try to get 40LD product info, which tells us what the card is 564 * labelled as. 565 */ 566 ap = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_PRODUCT_INFO, 0, 567 amr->amr_enqbuf); 568 if (ap != NULL) { 569 aprint_normal("<%.80s>\n", ap->ap_product); 570 if (intrstr != NULL) 571 aprint_normal("%s: interrupting at %s\n", 572 amr->amr_dv.dv_xname, intrstr); 573 aprint_normal("%s: firmware %.16s, BIOS %.16s, %dMB RAM\n", 574 amr->amr_dv.dv_xname, ap->ap_firmware, ap->ap_bios, 575 le16toh(ap->ap_memsize)); 576 577 amr->amr_maxqueuecnt = ap->ap_maxio; 578 579 /* 580 * Fetch and record state of logical drives. 581 */ 582 aex = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_ENQ3, 583 AMR_CONFIG_ENQ3_SOLICITED_FULL, amr->amr_enqbuf); 584 if (aex == NULL) { 585 aprint_error("%s ENQUIRY3 failed\n", 586 amr->amr_dv.dv_xname); 587 return (-1); 588 } 589 590 if (aex->ae_numldrives > AMR_MAX_UNITS) { 591 aprint_error( 592 "%s: adjust AMR_MAX_UNITS to %d (currently %d)" 593 "\n", amr->amr_dv.dv_xname, AMR_MAX_UNITS, 594 amr->amr_numdrives); 595 amr->amr_numdrives = AMR_MAX_UNITS; 596 } else 597 amr->amr_numdrives = aex->ae_numldrives; 598 599 for (i = 0; i < amr->amr_numdrives; i++) { 600 amr->amr_drive[i].al_size = 601 le32toh(aex->ae_drivesize[i]); 602 amr->amr_drive[i].al_state = aex->ae_drivestate[i]; 603 amr->amr_drive[i].al_properties = aex->ae_driveprop[i]; 604 } 605 606 return (0); 607 } 608 609 /* 610 * Try 8LD extended ENQUIRY to get the controller signature. Once 611 * found, search for a product description. 612 */ 613 ae = amr_enquire(amr, AMR_CMD_EXT_ENQUIRY2, 0, 0, amr->amr_enqbuf); 614 if (ae != NULL) { 615 i = 0; 616 sig = le32toh(ae->ae_signature); 617 618 while (i < sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 619 if (amr_typestr[i].at_sig == sig) 620 break; 621 i++; 622 } 623 if (i == sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 624 sprintf(buf, "unknown ENQUIRY2 sig (0x%08x)", sig); 625 prodstr = buf; 626 } else 627 prodstr = amr_typestr[i].at_str; 628 } else { 629 ae = amr_enquire(amr, AMR_CMD_ENQUIRY, 0, 0, amr->amr_enqbuf); 630 if (ae == NULL) { 631 aprint_error("%s: unsupported controller\n", 632 amr->amr_dv.dv_xname); 633 return (-1); 634 } 635 636 switch (PCI_PRODUCT(pa->pa_id)) { 637 case PCI_PRODUCT_AMI_MEGARAID: 638 prodstr = "Series 428"; 639 break; 640 case PCI_PRODUCT_AMI_MEGARAID2: 641 prodstr = "Series 434"; 642 break; 643 default: 644 sprintf(buf, "unknown PCI dev (0x%04x)", 645 PCI_PRODUCT(pa->pa_id)); 646 prodstr = buf; 647 break; 648 } 649 } 650 651 /* 652 * HP NetRaid controllers have a special encoding of the firmware 653 * and BIOS versions. The AMI version seems to have it as strings 654 * whereas the HP version does it with a leading uppercase character 655 * and two binary numbers. 656 */ 657 aa = &ae->ae_adapter; 658 659 if (aa->aa_firmware[2] >= 'A' && aa->aa_firmware[2] <= 'Z' && 660 aa->aa_firmware[1] < ' ' && aa->aa_firmware[0] < ' ' && 661 aa->aa_bios[2] >= 'A' && aa->aa_bios[2] <= 'Z' && 662 aa->aa_bios[1] < ' ' && aa->aa_bios[0] < ' ') { 663 if (le32toh(ae->ae_signature) == AMR_SIG_438) { 664 /* The AMI 438 is a NetRaid 3si in HP-land. */ 665 prodstr = "HP NetRaid 3si"; 666 } 667 ishp = 1; 668 } else 669 ishp = 0; 670 671 aprint_normal("<%s>\n", prodstr); 672 if (intrstr != NULL) 673 aprint_normal("%s: interrupting at %s\n", amr->amr_dv.dv_xname, 674 intrstr); 675 676 if (ishp) 677 aprint_normal("%s: firmware <%c.%02d.%02d>, BIOS <%c.%02d.%02d>" 678 ", %dMB RAM\n", amr->amr_dv.dv_xname, aa->aa_firmware[2], 679 aa->aa_firmware[1], aa->aa_firmware[0], aa->aa_bios[2], 680 aa->aa_bios[1], aa->aa_bios[0], aa->aa_memorysize); 681 else 682 aprint_normal("%s: firmware <%.4s>, BIOS <%.4s>, %dMB RAM\n", 683 amr->amr_dv.dv_xname, aa->aa_firmware, aa->aa_bios, 684 aa->aa_memorysize); 685 686 amr->amr_maxqueuecnt = aa->aa_maxio; 687 688 /* 689 * Record state of logical drives. 690 */ 691 if (ae->ae_ldrv.al_numdrives > AMR_MAX_UNITS) { 692 aprint_error("%s: adjust AMR_MAX_UNITS to %d (currently %d)\n", 693 amr->amr_dv.dv_xname, ae->ae_ldrv.al_numdrives, 694 AMR_MAX_UNITS); 695 amr->amr_numdrives = AMR_MAX_UNITS; 696 } else 697 amr->amr_numdrives = ae->ae_ldrv.al_numdrives; 698 699 for (i = 0; i < AMR_MAX_UNITS; i++) { 700 amr->amr_drive[i].al_size = le32toh(ae->ae_ldrv.al_size[i]); 701 amr->amr_drive[i].al_state = ae->ae_ldrv.al_state[i]; 702 amr->amr_drive[i].al_properties = ae->ae_ldrv.al_properties[i]; 703 } 704 705 return (0); 706 } 707 708 /* 709 * Flush the internal cache on each configured controller. Called at 710 * shutdown time. 711 */ 712 void 713 amr_shutdown(void *cookie) 714 { 715 extern struct cfdriver amr_cd; 716 struct amr_softc *amr; 717 struct amr_ccb *ac; 718 int i, rv, s; 719 720 for (i = 0; i < amr_cd.cd_ndevs; i++) { 721 if ((amr = device_lookup(&amr_cd, i)) == NULL) 722 continue; 723 724 if ((rv = amr_ccb_alloc(amr, &ac)) == 0) { 725 ac->ac_cmd.mb_command = AMR_CMD_FLUSH; 726 s = splbio(); 727 rv = amr_ccb_poll(amr, ac, 30000); 728 splx(s); 729 amr_ccb_free(amr, ac); 730 } 731 if (rv != 0) 732 printf("%s: unable to flush cache (%d)\n", 733 amr->amr_dv.dv_xname, rv); 734 } 735 } 736 737 /* 738 * Interrupt service routine. 739 */ 740 int 741 amr_intr(void *cookie) 742 { 743 struct amr_softc *amr; 744 struct amr_ccb *ac; 745 struct amr_mailbox_resp mbox; 746 u_int i, forus, idx; 747 748 amr = cookie; 749 forus = 0; 750 751 while ((*amr->amr_get_work)(amr, &mbox) == 0) { 752 /* Iterate over completed commands in this result. */ 753 for (i = 0; i < mbox.mb_nstatus; i++) { 754 idx = mbox.mb_completed[i] - 1; 755 ac = amr->amr_ccbs + idx; 756 757 if (idx >= amr->amr_maxqueuecnt) { 758 printf("%s: bad status (bogus ID: %u=%u)\n", 759 amr->amr_dv.dv_xname, i, idx); 760 continue; 761 } 762 763 if ((ac->ac_flags & AC_ACTIVE) == 0) { 764 printf("%s: bad status (not active; 0x04%x)\n", 765 amr->amr_dv.dv_xname, ac->ac_flags); 766 continue; 767 } 768 769 ac->ac_status = mbox.mb_status; 770 ac->ac_flags = (ac->ac_flags & ~AC_ACTIVE) | 771 AC_COMPLETE; 772 TAILQ_REMOVE(&amr->amr_ccb_active, ac, ac_chain.tailq); 773 774 if ((ac->ac_flags & AC_MOAN) != 0) 775 printf("%s: ccb %d completed\n", 776 amr->amr_dv.dv_xname, ac->ac_ident); 777 778 /* Pass notification to upper layers. */ 779 if (ac->ac_handler != NULL) 780 (*ac->ac_handler)(ac); 781 else 782 wakeup(ac); 783 } 784 forus = 1; 785 } 786 787 if (forus) 788 amr_ccb_enqueue(amr, NULL); 789 790 return (forus); 791 } 792 793 /* 794 * Create the watchdog thread. 795 */ 796 void 797 amr_thread_create(void *cookie) 798 { 799 struct amr_softc *amr; 800 int rv; 801 802 amr = cookie; 803 804 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 805 amr->amr_flags ^= AMRF_THREAD_EXIT; 806 wakeup(&amr->amr_flags); 807 return; 808 } 809 810 rv = kthread_create1(amr_thread, amr, &amr->amr_thread, "%s", 811 amr->amr_dv.dv_xname); 812 if (rv != 0) 813 aprint_error("%s: unable to create thread (%d)", 814 amr->amr_dv.dv_xname, rv); 815 else 816 amr->amr_flags |= AMRF_THREAD; 817 } 818 819 /* 820 * Watchdog thread. 821 */ 822 void 823 amr_thread(void *cookie) 824 { 825 struct amr_softc *amr; 826 struct amr_ccb *ac; 827 struct amr_logdrive *al; 828 struct amr_enquiry *ae; 829 time_t curtime; 830 int rv, i, s; 831 832 amr = cookie; 833 ae = amr->amr_enqbuf; 834 835 for (;;) { 836 tsleep(amr_thread, PWAIT, "amrwdog", AMR_WDOG_TICKS); 837 838 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 839 amr->amr_flags ^= AMRF_THREAD_EXIT; 840 wakeup(&amr->amr_flags); 841 kthread_exit(0); 842 } 843 844 s = splbio(); 845 amr_intr(cookie); 846 curtime = (time_t)mono_time.tv_sec; 847 ac = TAILQ_FIRST(&amr->amr_ccb_active); 848 while (ac != NULL) { 849 if (ac->ac_start_time + AMR_TIMEOUT > curtime) 850 break; 851 if ((ac->ac_flags & AC_MOAN) == 0) { 852 printf("%s: ccb %d timed out; mailbox:\n", 853 amr->amr_dv.dv_xname, ac->ac_ident); 854 amr_ccb_dump(amr, ac); 855 ac->ac_flags |= AC_MOAN; 856 } 857 ac = TAILQ_NEXT(ac, ac_chain.tailq); 858 } 859 splx(s); 860 861 if ((rv = amr_ccb_alloc(amr, &ac)) != 0) { 862 printf("%s: ccb_alloc failed (%d)\n", 863 amr->amr_dv.dv_xname, rv); 864 continue; 865 } 866 867 ac->ac_cmd.mb_command = AMR_CMD_ENQUIRY; 868 869 rv = amr_ccb_map(amr, ac, amr->amr_enqbuf, 870 AMR_ENQUIRY_BUFSIZE, 0); 871 if (rv != 0) { 872 printf("%s: ccb_map failed (%d)\n", 873 amr->amr_dv.dv_xname, rv); 874 amr_ccb_free(amr, ac); 875 continue; 876 } 877 878 rv = amr_ccb_wait(amr, ac); 879 amr_ccb_unmap(amr, ac); 880 if (rv != 0) { 881 printf("%s: enquiry failed (st=%d)\n", 882 amr->amr_dv.dv_xname, ac->ac_status); 883 continue; 884 } 885 amr_ccb_free(amr, ac); 886 887 al = amr->amr_drive; 888 for (i = 0; i < AMR_MAX_UNITS; i++, al++) { 889 if (al->al_dv == NULL) 890 continue; 891 if (al->al_state == ae->ae_ldrv.al_state[i]) 892 continue; 893 894 printf("%s: state changed: %s -> %s\n", 895 al->al_dv->dv_xname, 896 amr_drive_state(al->al_state, NULL), 897 amr_drive_state(ae->ae_ldrv.al_state[i], NULL)); 898 899 al->al_state = ae->ae_ldrv.al_state[i]; 900 } 901 } 902 } 903 904 /* 905 * Return a text description of a logical drive's current state. 906 */ 907 const char * 908 amr_drive_state(int state, int *happy) 909 { 910 const char *str; 911 912 state = AMR_DRV_CURSTATE(state); 913 if (state >= sizeof(amr_dstate) / sizeof(amr_dstate[0])) { 914 if (happy) 915 *happy = 1; 916 str = "status unknown"; 917 } else { 918 if (happy) 919 *happy = amr_dstate[state].ds_happy; 920 str = amr_dstate[state].ds_descr; 921 } 922 923 return (str); 924 } 925 926 /* 927 * Run a generic enquiry-style command. 928 */ 929 void * 930 amr_enquire(struct amr_softc *amr, u_int8_t cmd, u_int8_t cmdsub, 931 u_int8_t cmdqual, void *buf) 932 { 933 struct amr_ccb *ac; 934 u_int8_t *mb; 935 int rv; 936 937 if (amr_ccb_alloc(amr, &ac) != 0) 938 return (NULL); 939 940 /* Build the command proper. */ 941 mb = (u_int8_t *)&ac->ac_cmd; 942 mb[0] = cmd; 943 mb[2] = cmdsub; 944 mb[3] = cmdqual; 945 946 rv = amr_ccb_map(amr, ac, buf, AMR_ENQUIRY_BUFSIZE, 0); 947 if (rv == 0) { 948 rv = amr_ccb_poll(amr, ac, 2000); 949 amr_ccb_unmap(amr, ac); 950 } 951 amr_ccb_free(amr, ac); 952 953 return (rv ? NULL : buf); 954 } 955 956 /* 957 * Allocate and initialise a CCB. 958 */ 959 int 960 amr_ccb_alloc(struct amr_softc *amr, struct amr_ccb **acp) 961 { 962 int s; 963 964 s = splbio(); 965 if ((*acp = SLIST_FIRST(&amr->amr_ccb_freelist)) == NULL) { 966 splx(s); 967 return (EAGAIN); 968 } 969 SLIST_REMOVE_HEAD(&amr->amr_ccb_freelist, ac_chain.slist); 970 splx(s); 971 972 return (0); 973 } 974 975 /* 976 * Free a CCB. 977 */ 978 void 979 amr_ccb_free(struct amr_softc *amr, struct amr_ccb *ac) 980 { 981 int s; 982 983 memset(&ac->ac_cmd, 0, sizeof(ac->ac_cmd)); 984 ac->ac_cmd.mb_ident = ac->ac_ident + 1; 985 ac->ac_cmd.mb_busy = 1; 986 ac->ac_handler = NULL; 987 ac->ac_flags = 0; 988 989 s = splbio(); 990 SLIST_INSERT_HEAD(&amr->amr_ccb_freelist, ac, ac_chain.slist); 991 splx(s); 992 } 993 994 /* 995 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 996 * the order that they were enqueued and try to submit their command blocks 997 * to the controller for execution. 998 */ 999 void 1000 amr_ccb_enqueue(struct amr_softc *amr, struct amr_ccb *ac) 1001 { 1002 int s; 1003 1004 s = splbio(); 1005 1006 if (ac != NULL) 1007 SIMPLEQ_INSERT_TAIL(&amr->amr_ccb_queue, ac, ac_chain.simpleq); 1008 1009 while ((ac = SIMPLEQ_FIRST(&amr->amr_ccb_queue)) != NULL) { 1010 if ((*amr->amr_submit)(amr, ac) != 0) 1011 break; 1012 SIMPLEQ_REMOVE_HEAD(&amr->amr_ccb_queue, ac_chain.simpleq); 1013 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1014 } 1015 1016 splx(s); 1017 } 1018 1019 /* 1020 * Map the specified CCB's data buffer onto the bus, and fill the 1021 * scatter-gather list. 1022 */ 1023 int 1024 amr_ccb_map(struct amr_softc *amr, struct amr_ccb *ac, void *data, int size, 1025 int out) 1026 { 1027 struct amr_sgentry *sge; 1028 struct amr_mailbox_cmd *mb; 1029 int nsegs, i, rv, sgloff; 1030 bus_dmamap_t xfer; 1031 1032 xfer = ac->ac_xfer_map; 1033 1034 rv = bus_dmamap_load(amr->amr_dmat, xfer, data, size, NULL, 1035 BUS_DMA_NOWAIT); 1036 if (rv != 0) 1037 return (rv); 1038 1039 mb = &ac->ac_cmd; 1040 ac->ac_xfer_size = size; 1041 ac->ac_flags |= (out ? AC_XFER_OUT : AC_XFER_IN); 1042 sgloff = AMR_SGL_SIZE * ac->ac_ident; 1043 1044 /* We don't need to use a scatter/gather list for just 1 segment. */ 1045 nsegs = xfer->dm_nsegs; 1046 if (nsegs == 1) { 1047 mb->mb_nsgelem = 0; 1048 mb->mb_physaddr = htole32(xfer->dm_segs[0].ds_addr); 1049 ac->ac_flags |= AC_NOSGL; 1050 } else { 1051 mb->mb_nsgelem = nsegs; 1052 mb->mb_physaddr = htole32(amr->amr_sgls_paddr + sgloff); 1053 1054 sge = (struct amr_sgentry *)((caddr_t)amr->amr_sgls + sgloff); 1055 for (i = 0; i < nsegs; i++, sge++) { 1056 sge->sge_addr = htole32(xfer->dm_segs[i].ds_addr); 1057 sge->sge_count = htole32(xfer->dm_segs[i].ds_len); 1058 } 1059 } 1060 1061 bus_dmamap_sync(amr->amr_dmat, xfer, 0, ac->ac_xfer_size, 1062 out ? BUS_DMASYNC_PREWRITE : BUS_DMASYNC_PREREAD); 1063 1064 if ((ac->ac_flags & AC_NOSGL) == 0) 1065 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, sgloff, 1066 AMR_SGL_SIZE, BUS_DMASYNC_PREWRITE); 1067 1068 return (0); 1069 } 1070 1071 /* 1072 * Unmap the specified CCB's data buffer. 1073 */ 1074 void 1075 amr_ccb_unmap(struct amr_softc *amr, struct amr_ccb *ac) 1076 { 1077 1078 if ((ac->ac_flags & AC_NOSGL) == 0) 1079 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 1080 AMR_SGL_SIZE * ac->ac_ident, AMR_SGL_SIZE, 1081 BUS_DMASYNC_POSTWRITE); 1082 bus_dmamap_sync(amr->amr_dmat, ac->ac_xfer_map, 0, ac->ac_xfer_size, 1083 (ac->ac_flags & AC_XFER_IN) != 0 ? 1084 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1085 bus_dmamap_unload(amr->amr_dmat, ac->ac_xfer_map); 1086 } 1087 1088 /* 1089 * Submit a command to the controller and poll on completion. Return 1090 * non-zero on timeout or error. Must be called with interrupts blocked. 1091 */ 1092 int 1093 amr_ccb_poll(struct amr_softc *amr, struct amr_ccb *ac, int timo) 1094 { 1095 int rv; 1096 1097 if ((rv = (*amr->amr_submit)(amr, ac)) != 0) 1098 return (rv); 1099 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1100 1101 for (timo *= 10; timo != 0; timo--) { 1102 amr_intr(amr); 1103 if ((ac->ac_flags & AC_COMPLETE) != 0) 1104 break; 1105 DELAY(100); 1106 } 1107 1108 return (timo == 0 || ac->ac_status != 0 ? EIO : 0); 1109 } 1110 1111 /* 1112 * Submit a command to the controller and sleep on completion. Return 1113 * non-zero on error. 1114 */ 1115 int 1116 amr_ccb_wait(struct amr_softc *amr, struct amr_ccb *ac) 1117 { 1118 int s; 1119 1120 s = splbio(); 1121 amr_ccb_enqueue(amr, ac); 1122 tsleep(ac, PRIBIO, "amrcmd", 0); 1123 splx(s); 1124 1125 return (ac->ac_status != 0 ? EIO : 0); 1126 } 1127 1128 /* 1129 * Wait for the mailbox to become available. 1130 */ 1131 int 1132 amr_mbox_wait(struct amr_softc *amr) 1133 { 1134 int timo; 1135 1136 for (timo = 10000; timo != 0; timo--) { 1137 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1138 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1139 if (amr->amr_mbox->mb_cmd.mb_busy == 0) 1140 break; 1141 DELAY(100); 1142 } 1143 1144 if (timo == 0) 1145 printf("%s: controller wedged\n", amr->amr_dv.dv_xname); 1146 1147 return (timo != 0 ? 0 : EAGAIN); 1148 } 1149 1150 /* 1151 * Tell the controller that the mailbox contains a valid command. Must be 1152 * called with interrupts blocked. 1153 */ 1154 int 1155 amr_quartz_submit(struct amr_softc *amr, struct amr_ccb *ac) 1156 { 1157 u_int32_t v; 1158 1159 amr->amr_mbox->mb_poll = 0; 1160 amr->amr_mbox->mb_ack = 0; 1161 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1162 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1163 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1164 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1165 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1166 return (EAGAIN); 1167 1168 v = amr_inl(amr, AMR_QREG_IDB); 1169 if ((v & AMR_QIDB_SUBMIT) != 0) { 1170 amr->amr_mbox->mb_cmd.mb_busy = 0; 1171 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1172 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1173 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1174 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1175 return (EAGAIN); 1176 } 1177 1178 amr->amr_mbox->mb_segment = 0; 1179 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1180 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1181 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1182 1183 ac->ac_start_time = (time_t)mono_time.tv_sec; 1184 ac->ac_flags |= AC_ACTIVE; 1185 amr_outl(amr, AMR_QREG_IDB, 1186 (amr->amr_mbox_paddr + 16) | AMR_QIDB_SUBMIT); 1187 return (0); 1188 } 1189 1190 int 1191 amr_std_submit(struct amr_softc *amr, struct amr_ccb *ac) 1192 { 1193 1194 amr->amr_mbox->mb_poll = 0; 1195 amr->amr_mbox->mb_ack = 0; 1196 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1197 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1198 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1199 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1200 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1201 return (EAGAIN); 1202 1203 if ((amr_inb(amr, AMR_SREG_MBOX_BUSY) & AMR_SMBOX_BUSY_FLAG) != 0) { 1204 amr->amr_mbox->mb_cmd.mb_busy = 0; 1205 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1206 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1207 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1208 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1209 return (EAGAIN); 1210 } 1211 1212 amr->amr_mbox->mb_segment = 0; 1213 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1214 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1215 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1216 1217 ac->ac_start_time = (time_t)mono_time.tv_sec; 1218 ac->ac_flags |= AC_ACTIVE; 1219 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_POST); 1220 return (0); 1221 } 1222 1223 /* 1224 * Claim any work that the controller has completed; acknowledge completion, 1225 * save details of the completion in (mbsave). Must be called with 1226 * interrupts blocked. 1227 */ 1228 int 1229 amr_quartz_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1230 { 1231 1232 /* Work waiting for us? */ 1233 if (amr_inl(amr, AMR_QREG_ODB) != AMR_QODB_READY) 1234 return (-1); 1235 1236 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1237 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1238 1239 /* Save the mailbox, which contains a list of completed commands. */ 1240 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1241 1242 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1243 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1244 1245 /* Ack the interrupt and mailbox transfer. */ 1246 amr_outl(amr, AMR_QREG_ODB, AMR_QODB_READY); 1247 amr_outl(amr, AMR_QREG_IDB, (amr->amr_mbox_paddr+16) | AMR_QIDB_ACK); 1248 1249 /* 1250 * This waits for the controller to notice that we've taken the 1251 * command from it. It's very inefficient, and we shouldn't do it, 1252 * but if we remove this code, we stop completing commands under 1253 * load. 1254 * 1255 * Peter J says we shouldn't do this. The documentation says we 1256 * should. Who is right? 1257 */ 1258 while ((amr_inl(amr, AMR_QREG_IDB) & AMR_QIDB_ACK) != 0) 1259 DELAY(10); 1260 1261 return (0); 1262 } 1263 1264 int 1265 amr_std_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1266 { 1267 u_int8_t istat; 1268 1269 /* Check for valid interrupt status. */ 1270 if (((istat = amr_inb(amr, AMR_SREG_INTR)) & AMR_SINTR_VALID) == 0) 1271 return (-1); 1272 1273 /* Ack the interrupt. */ 1274 amr_outb(amr, AMR_SREG_INTR, istat); 1275 1276 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1277 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1278 1279 /* Save mailbox, which contains a list of completed commands. */ 1280 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1281 1282 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1283 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1284 1285 /* Ack mailbox transfer. */ 1286 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 1287 1288 return (0); 1289 } 1290 1291 void 1292 amr_ccb_dump(struct amr_softc *amr, struct amr_ccb *ac) 1293 { 1294 int i; 1295 1296 printf("%s: ", amr->amr_dv.dv_xname); 1297 for (i = 0; i < 4; i++) 1298 printf("%08x ", ((u_int32_t *)&ac->ac_cmd)[i]); 1299 printf("\n"); 1300 } 1301
Indexes created Thu Oct 02 14:10:14 GMT 2025