amr.c revision 1.22
1 /* $NetBSD: amr.c,v 1.22 2004/09/13 12:55:48 drochner Exp $ */ 2 3 /*- 4 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999,2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: amr_pci.c,v 1.5 2000/08/30 07:52:40 msmith Exp 66 * from FreeBSD: amr.c,v 1.16 2000/08/30 07:52:40 msmith Exp 67 */ 68 69 /* 70 * Driver for AMI RAID controllers. 71 */ 72 73 #include <sys/cdefs.h> 74 __KERNEL_RCSID(0, "$NetBSD: amr.c,v 1.22 2004/09/13 12:55:48 drochner Exp $"); 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/device.h> 80 #include <sys/queue.h> 81 #include <sys/proc.h> 82 #include <sys/buf.h> 83 #include <sys/malloc.h> 84 #include <sys/kthread.h> 85 86 #include <uvm/uvm_extern.h> 87 88 #include <machine/endian.h> 89 #include <machine/bus.h> 90 91 #include <dev/pci/pcidevs.h> 92 #include <dev/pci/pcivar.h> 93 #include <dev/pci/amrreg.h> 94 #include <dev/pci/amrvar.h> 95 96 #include "locators.h" 97 98 void amr_attach(struct device *, struct device *, void *); 99 void amr_ccb_dump(struct amr_softc *, struct amr_ccb *); 100 void *amr_enquire(struct amr_softc *, u_int8_t, u_int8_t, u_int8_t, void *); 101 int amr_init(struct amr_softc *, const char *, 102 struct pci_attach_args *pa); 103 int amr_intr(void *); 104 int amr_match(struct device *, struct cfdata *, void *); 105 int amr_print(void *, const char *); 106 void amr_shutdown(void *); 107 int amr_submatch(struct device *, struct cfdata *, 108 const locdesc_t *, void *); 109 void amr_teardown(struct amr_softc *); 110 void amr_thread(void *); 111 void amr_thread_create(void *); 112 113 int amr_mbox_wait(struct amr_softc *); 114 int amr_quartz_get_work(struct amr_softc *, struct amr_mailbox_resp *); 115 int amr_quartz_submit(struct amr_softc *, struct amr_ccb *); 116 int amr_std_get_work(struct amr_softc *, struct amr_mailbox_resp *); 117 int amr_std_submit(struct amr_softc *, struct amr_ccb *); 118 119 static inline u_int8_t amr_inb(struct amr_softc *, int); 120 static inline u_int32_t amr_inl(struct amr_softc *, int); 121 static inline void amr_outb(struct amr_softc *, int, u_int8_t); 122 static inline void amr_outl(struct amr_softc *, int, u_int32_t); 123 124 CFATTACH_DECL(amr, sizeof(struct amr_softc), 125 amr_match, amr_attach, NULL, NULL); 126 127 #define AT_QUARTZ 0x01 /* `Quartz' chipset */ 128 #define AT_SIG 0x02 /* Check for signature */ 129 130 struct amr_pci_type { 131 u_short apt_vendor; 132 u_short apt_product; 133 u_short apt_flags; 134 } const amr_pci_type[] = { 135 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID, 0 }, 136 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID2, 0 }, 137 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 138 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ | AT_SIG }, 140 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI, AT_QUARTZ }, 141 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI_2, AT_QUARTZ }, 142 }; 143 144 struct amr_typestr { 145 const char *at_str; 146 int at_sig; 147 } const amr_typestr[] = { 148 { "Series 431", AMR_SIG_431 }, 149 { "Series 438", AMR_SIG_438 }, 150 { "Series 466", AMR_SIG_466 }, 151 { "Series 467", AMR_SIG_467 }, 152 { "Series 490", AMR_SIG_490 }, 153 { "Series 762", AMR_SIG_762 }, 154 { "HP NetRAID (T5)", AMR_SIG_T5 }, 155 { "HP NetRAID (T7)", AMR_SIG_T7 }, 156 }; 157 158 struct { 159 const char *ds_descr; 160 int ds_happy; 161 } const amr_dstate[] = { 162 { "offline", 0 }, 163 { "degraded", 1 }, 164 { "optimal", 1 }, 165 { "online", 1 }, 166 { "failed", 0 }, 167 { "rebuilding", 1 }, 168 { "hotspare", 0 }, 169 }; 170 171 void *amr_sdh; 172 int amr_max_segs; 173 int amr_max_xfer; 174 175 static inline u_int8_t 176 amr_inb(struct amr_softc *amr, int off) 177 { 178 179 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 180 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 181 return (bus_space_read_1(amr->amr_iot, amr->amr_ioh, off)); 182 } 183 184 static inline u_int32_t 185 amr_inl(struct amr_softc *amr, int off) 186 { 187 188 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 189 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 190 return (bus_space_read_4(amr->amr_iot, amr->amr_ioh, off)); 191 } 192 193 static inline void 194 amr_outb(struct amr_softc *amr, int off, u_int8_t val) 195 { 196 197 bus_space_write_1(amr->amr_iot, amr->amr_ioh, off, val); 198 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 199 BUS_SPACE_BARRIER_WRITE); 200 } 201 202 static inline void 203 amr_outl(struct amr_softc *amr, int off, u_int32_t val) 204 { 205 206 bus_space_write_4(amr->amr_iot, amr->amr_ioh, off, val); 207 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 208 BUS_SPACE_BARRIER_WRITE); 209 } 210 211 /* 212 * Match a supported device. 213 */ 214 int 215 amr_match(struct device *parent, struct cfdata *match, void *aux) 216 { 217 struct pci_attach_args *pa; 218 pcireg_t s; 219 int i; 220 221 pa = (struct pci_attach_args *)aux; 222 223 /* 224 * Don't match the device if it's operating in I2O mode. In this 225 * case it should be handled by the `iop' driver. 226 */ 227 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 228 return (0); 229 230 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 231 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 232 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 233 break; 234 235 if (i == sizeof(amr_pci_type) / sizeof(amr_pci_type[0])) 236 return (0); 237 238 if ((amr_pci_type[i].apt_flags & AT_SIG) == 0) 239 return (1); 240 241 s = pci_conf_read(pa->pa_pc, pa->pa_tag, AMR_QUARTZ_SIG_REG) & 0xffff; 242 return (s == AMR_QUARTZ_SIG0 || s == AMR_QUARTZ_SIG1); 243 } 244 245 /* 246 * Attach a supported device. 247 */ 248 void 249 amr_attach(struct device *parent, struct device *self, void *aux) 250 { 251 struct pci_attach_args *pa; 252 struct amr_attach_args amra; 253 const struct amr_pci_type *apt; 254 struct amr_softc *amr; 255 pci_chipset_tag_t pc; 256 pci_intr_handle_t ih; 257 const char *intrstr; 258 pcireg_t reg; 259 int rseg, i, j, size, rv, memreg, ioreg; 260 struct amr_ccb *ac; 261 int help[2]; 262 locdesc_t *ldesc = (void *)help; /* XXX */ 263 264 aprint_naive(": RAID controller\n"); 265 266 amr = (struct amr_softc *)self; 267 pa = (struct pci_attach_args *)aux; 268 pc = pa->pa_pc; 269 270 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 271 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 272 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 273 break; 274 apt = amr_pci_type + i; 275 276 memreg = ioreg = 0; 277 for (i = 0x10; i <= 0x14; i += 4) { 278 reg = pci_conf_read(pc, pa->pa_tag, i); 279 switch (PCI_MAPREG_TYPE(reg)) { 280 case PCI_MAPREG_TYPE_MEM: 281 if (PCI_MAPREG_MEM_SIZE(reg) != 0) 282 memreg = i; 283 break; 284 case PCI_MAPREG_TYPE_IO: 285 if (PCI_MAPREG_IO_SIZE(reg) != 0) 286 ioreg = i; 287 break; 288 289 } 290 } 291 292 if (memreg && pci_mapreg_map(pa, memreg, PCI_MAPREG_TYPE_MEM, 0, 293 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 294 ; 295 else if (ioreg && pci_mapreg_map(pa, ioreg, PCI_MAPREG_TYPE_IO, 0, 296 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 297 ; 298 else { 299 aprint_error("can't map control registers\n"); 300 amr_teardown(amr); 301 return; 302 } 303 304 amr->amr_flags |= AMRF_PCI_REGS; 305 amr->amr_dmat = pa->pa_dmat; 306 amr->amr_pc = pa->pa_pc; 307 308 /* Enable the device. */ 309 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 310 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 311 reg | PCI_COMMAND_MASTER_ENABLE); 312 313 /* Map and establish the interrupt. */ 314 if (pci_intr_map(pa, &ih)) { 315 aprint_error("can't map interrupt\n"); 316 amr_teardown(amr); 317 return; 318 } 319 intrstr = pci_intr_string(pc, ih); 320 amr->amr_ih = pci_intr_establish(pc, ih, IPL_BIO, amr_intr, amr); 321 if (amr->amr_ih == NULL) { 322 aprint_error("can't establish interrupt"); 323 if (intrstr != NULL) 324 aprint_normal(" at %s", intrstr); 325 aprint_normal("\n"); 326 amr_teardown(amr); 327 return; 328 } 329 amr->amr_flags |= AMRF_PCI_INTR; 330 331 /* 332 * Allocate space for the mailbox and S/G lists. Some controllers 333 * don't like S/G lists to be located below 0x2000, so we allocate 334 * enough slop to enable us to compensate. 335 * 336 * The standard mailbox structure needs to be aligned on a 16-byte 337 * boundary. The 64-bit mailbox has one extra field, 4 bytes in 338 * size, which preceeds the standard mailbox. 339 */ 340 size = AMR_SGL_SIZE * AMR_MAX_CMDS + 0x2000; 341 amr->amr_dmasize = size; 342 343 if ((rv = bus_dmamem_alloc(amr->amr_dmat, size, PAGE_SIZE, 0, 344 &amr->amr_dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 345 aprint_error("%s: unable to allocate buffer, rv = %d\n", 346 amr->amr_dv.dv_xname, rv); 347 amr_teardown(amr); 348 return; 349 } 350 amr->amr_flags |= AMRF_DMA_ALLOC; 351 352 if ((rv = bus_dmamem_map(amr->amr_dmat, &amr->amr_dmaseg, rseg, size, 353 (caddr_t *)&amr->amr_mbox, 354 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 355 aprint_error("%s: unable to map buffer, rv = %d\n", 356 amr->amr_dv.dv_xname, rv); 357 amr_teardown(amr); 358 return; 359 } 360 amr->amr_flags |= AMRF_DMA_MAP; 361 362 if ((rv = bus_dmamap_create(amr->amr_dmat, size, 1, size, 0, 363 BUS_DMA_NOWAIT, &amr->amr_dmamap)) != 0) { 364 aprint_error("%s: unable to create buffer DMA map, rv = %d\n", 365 amr->amr_dv.dv_xname, rv); 366 amr_teardown(amr); 367 return; 368 } 369 amr->amr_flags |= AMRF_DMA_CREATE; 370 371 if ((rv = bus_dmamap_load(amr->amr_dmat, amr->amr_dmamap, 372 amr->amr_mbox, size, NULL, BUS_DMA_NOWAIT)) != 0) { 373 aprint_error("%s: unable to load buffer DMA map, rv = %d\n", 374 amr->amr_dv.dv_xname, rv); 375 amr_teardown(amr); 376 return; 377 } 378 amr->amr_flags |= AMRF_DMA_LOAD; 379 380 memset(amr->amr_mbox, 0, size); 381 382 amr->amr_mbox_paddr = amr->amr_dmamap->dm_segs[0].ds_addr; 383 amr->amr_sgls_paddr = (amr->amr_mbox_paddr + 0x1fff) & ~0x1fff; 384 amr->amr_sgls = (struct amr_sgentry *)((caddr_t)amr->amr_mbox + 385 amr->amr_sgls_paddr - amr->amr_dmamap->dm_segs[0].ds_addr); 386 387 /* 388 * Allocate and initalise the command control blocks. 389 */ 390 ac = malloc(sizeof(*ac) * AMR_MAX_CMDS, M_DEVBUF, M_NOWAIT | M_ZERO); 391 amr->amr_ccbs = ac; 392 SLIST_INIT(&amr->amr_ccb_freelist); 393 TAILQ_INIT(&amr->amr_ccb_active); 394 amr->amr_flags |= AMRF_CCBS; 395 396 if (amr_max_xfer == 0) { 397 amr_max_xfer = min(((AMR_MAX_SEGS - 1) * PAGE_SIZE), MAXPHYS); 398 amr_max_segs = (amr_max_xfer + (PAGE_SIZE * 2) - 1) / PAGE_SIZE; 399 } 400 401 for (i = 0; i < AMR_MAX_CMDS; i++, ac++) { 402 rv = bus_dmamap_create(amr->amr_dmat, amr_max_xfer, 403 amr_max_segs, amr_max_xfer, 0, 404 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ac->ac_xfer_map); 405 if (rv != 0) 406 break; 407 408 ac->ac_ident = i; 409 amr_ccb_free(amr, ac); 410 } 411 if (i != AMR_MAX_CMDS) { 412 aprint_error("%s: memory exhausted\n", amr->amr_dv.dv_xname); 413 amr_teardown(amr); 414 return; 415 } 416 417 /* 418 * Take care of model-specific tasks. 419 */ 420 if ((apt->apt_flags & AT_QUARTZ) != 0) { 421 amr->amr_submit = amr_quartz_submit; 422 amr->amr_get_work = amr_quartz_get_work; 423 } else { 424 amr->amr_submit = amr_std_submit; 425 amr->amr_get_work = amr_std_get_work; 426 427 /* Notify the controller of the mailbox location. */ 428 amr_outl(amr, AMR_SREG_MBOX, (u_int32_t)amr->amr_mbox_paddr + 16); 429 amr_outb(amr, AMR_SREG_MBOX_ENABLE, AMR_SMBOX_ENABLE_ADDR); 430 431 /* Clear outstanding interrupts and enable interrupts. */ 432 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 433 amr_outb(amr, AMR_SREG_TOGL, 434 amr_inb(amr, AMR_SREG_TOGL) | AMR_STOGL_ENABLE); 435 } 436 437 /* 438 * Retrieve parameters, and tell the world about us. 439 */ 440 amr->amr_enqbuf = malloc(AMR_ENQUIRY_BUFSIZE, M_DEVBUF, M_NOWAIT); 441 amr->amr_flags |= AMRF_ENQBUF; 442 amr->amr_maxqueuecnt = i; 443 aprint_normal(": AMI RAID "); 444 if (amr_init(amr, intrstr, pa) != 0) { 445 amr_teardown(amr); 446 return; 447 } 448 449 /* 450 * Cap the maximum number of outstanding commands. AMI's Linux 451 * driver doesn't trust the controller's reported value, and lockups 452 * have been seen when we do. 453 */ 454 amr->amr_maxqueuecnt = min(amr->amr_maxqueuecnt, AMR_MAX_CMDS); 455 if (amr->amr_maxqueuecnt > i) 456 amr->amr_maxqueuecnt = i; 457 458 /* Set our `shutdownhook' before we start any device activity. */ 459 if (amr_sdh == NULL) 460 amr_sdh = shutdownhook_establish(amr_shutdown, NULL); 461 462 /* Attach sub-devices. */ 463 for (j = 0; j < amr->amr_numdrives; j++) { 464 if (amr->amr_drive[j].al_size == 0) 465 continue; 466 amra.amra_unit = j; 467 468 ldesc->len = 1; 469 ldesc->locs[AMRCF_UNIT] = j; 470 471 amr->amr_drive[j].al_dv = config_found_sm_loc(&amr->amr_dv, 472 "amr", ldesc, &amra, amr_print, amr_submatch); 473 } 474 475 SIMPLEQ_INIT(&amr->amr_ccb_queue); 476 477 /* XXX This doesn't work for newer boards yet. */ 478 if ((apt->apt_flags & AT_QUARTZ) == 0) 479 kthread_create(amr_thread_create, amr); 480 } 481 482 /* 483 * Free up resources. 484 */ 485 void 486 amr_teardown(struct amr_softc *amr) 487 { 488 struct amr_ccb *ac; 489 int fl; 490 491 fl = amr->amr_flags; 492 493 if ((fl & AMRF_THREAD) != 0) { 494 amr->amr_flags |= AMRF_THREAD_EXIT; 495 wakeup(amr_thread); 496 while ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) 497 tsleep(&amr->amr_flags, PWAIT, "amrexit", 0); 498 } 499 if ((fl & AMRF_CCBS) != 0) { 500 SLIST_FOREACH(ac, &amr->amr_ccb_freelist, ac_chain.slist) { 501 bus_dmamap_destroy(amr->amr_dmat, ac->ac_xfer_map); 502 } 503 free(amr->amr_ccbs, M_DEVBUF); 504 } 505 if ((fl & AMRF_ENQBUF) != 0) 506 free(amr->amr_enqbuf, M_DEVBUF); 507 if ((fl & AMRF_DMA_LOAD) != 0) 508 bus_dmamap_unload(amr->amr_dmat, amr->amr_dmamap); 509 if ((fl & AMRF_DMA_MAP) != 0) 510 bus_dmamem_unmap(amr->amr_dmat, (caddr_t)amr->amr_mbox, 511 amr->amr_dmasize); 512 if ((fl & AMRF_DMA_ALLOC) != 0) 513 bus_dmamem_free(amr->amr_dmat, &amr->amr_dmaseg, 1); 514 if ((fl & AMRF_DMA_CREATE) != 0) 515 bus_dmamap_destroy(amr->amr_dmat, amr->amr_dmamap); 516 if ((fl & AMRF_PCI_INTR) != 0) 517 pci_intr_disestablish(amr->amr_pc, amr->amr_ih); 518 if ((fl & AMRF_PCI_REGS) != 0) 519 bus_space_unmap(amr->amr_iot, amr->amr_ioh, amr->amr_ios); 520 } 521 522 /* 523 * Print autoconfiguration message for a sub-device. 524 */ 525 int 526 amr_print(void *aux, const char *pnp) 527 { 528 struct amr_attach_args *amra; 529 530 amra = (struct amr_attach_args *)aux; 531 532 if (pnp != NULL) 533 aprint_normal("block device at %s", pnp); 534 aprint_normal(" unit %d", amra->amra_unit); 535 return (UNCONF); 536 } 537 538 /* 539 * Match a sub-device. 540 */ 541 int 542 amr_submatch(struct device *parent, struct cfdata *cf, 543 const locdesc_t *ldesc, void *aux) 544 { 545 struct amr_attach_args *amra; 546 547 amra = (struct amr_attach_args *)aux; 548 549 if (cf->cf_loc[AMRCF_UNIT] != AMRCF_UNIT_DEFAULT && 550 cf->cf_loc[AMRCF_UNIT] != ldesc->locs[AMRCF_UNIT]) 551 return (0); 552 553 return (config_match(parent, cf, aux)); 554 } 555 556 /* 557 * Retrieve operational parameters and describe the controller. 558 */ 559 int 560 amr_init(struct amr_softc *amr, const char *intrstr, 561 struct pci_attach_args *pa) 562 { 563 struct amr_adapter_info *aa; 564 struct amr_prodinfo *ap; 565 struct amr_enquiry *ae; 566 struct amr_enquiry3 *aex; 567 const char *prodstr; 568 u_int i, sig, ishp; 569 char buf[64]; 570 571 /* 572 * Try to get 40LD product info, which tells us what the card is 573 * labelled as. 574 */ 575 ap = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_PRODUCT_INFO, 0, 576 amr->amr_enqbuf); 577 if (ap != NULL) { 578 aprint_normal("<%.80s>\n", ap->ap_product); 579 if (intrstr != NULL) 580 aprint_normal("%s: interrupting at %s\n", 581 amr->amr_dv.dv_xname, intrstr); 582 aprint_normal("%s: firmware %.16s, BIOS %.16s, %dMB RAM\n", 583 amr->amr_dv.dv_xname, ap->ap_firmware, ap->ap_bios, 584 le16toh(ap->ap_memsize)); 585 586 amr->amr_maxqueuecnt = ap->ap_maxio; 587 588 /* 589 * Fetch and record state of logical drives. 590 */ 591 aex = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_ENQ3, 592 AMR_CONFIG_ENQ3_SOLICITED_FULL, amr->amr_enqbuf); 593 if (aex == NULL) { 594 aprint_error("%s ENQUIRY3 failed\n", 595 amr->amr_dv.dv_xname); 596 return (-1); 597 } 598 599 if (aex->ae_numldrives > AMR_MAX_UNITS) { 600 aprint_error( 601 "%s: adjust AMR_MAX_UNITS to %d (currently %d)" 602 "\n", amr->amr_dv.dv_xname, AMR_MAX_UNITS, 603 amr->amr_numdrives); 604 amr->amr_numdrives = AMR_MAX_UNITS; 605 } else 606 amr->amr_numdrives = aex->ae_numldrives; 607 608 for (i = 0; i < amr->amr_numdrives; i++) { 609 amr->amr_drive[i].al_size = 610 le32toh(aex->ae_drivesize[i]); 611 amr->amr_drive[i].al_state = aex->ae_drivestate[i]; 612 amr->amr_drive[i].al_properties = aex->ae_driveprop[i]; 613 } 614 615 return (0); 616 } 617 618 /* 619 * Try 8LD extended ENQUIRY to get the controller signature. Once 620 * found, search for a product description. 621 */ 622 ae = amr_enquire(amr, AMR_CMD_EXT_ENQUIRY2, 0, 0, amr->amr_enqbuf); 623 if (ae != NULL) { 624 i = 0; 625 sig = le32toh(ae->ae_signature); 626 627 while (i < sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 628 if (amr_typestr[i].at_sig == sig) 629 break; 630 i++; 631 } 632 if (i == sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 633 snprintf(buf, sizeof(buf), 634 "unknown ENQUIRY2 sig (0x%08x)", sig); 635 prodstr = buf; 636 } else 637 prodstr = amr_typestr[i].at_str; 638 } else { 639 ae = amr_enquire(amr, AMR_CMD_ENQUIRY, 0, 0, amr->amr_enqbuf); 640 if (ae == NULL) { 641 aprint_error("%s: unsupported controller\n", 642 amr->amr_dv.dv_xname); 643 return (-1); 644 } 645 646 switch (PCI_PRODUCT(pa->pa_id)) { 647 case PCI_PRODUCT_AMI_MEGARAID: 648 prodstr = "Series 428"; 649 break; 650 case PCI_PRODUCT_AMI_MEGARAID2: 651 prodstr = "Series 434"; 652 break; 653 default: 654 snprintf(buf, sizeof(buf), "unknown PCI dev (0x%04x)", 655 PCI_PRODUCT(pa->pa_id)); 656 prodstr = buf; 657 break; 658 } 659 } 660 661 /* 662 * HP NetRaid controllers have a special encoding of the firmware 663 * and BIOS versions. The AMI version seems to have it as strings 664 * whereas the HP version does it with a leading uppercase character 665 * and two binary numbers. 666 */ 667 aa = &ae->ae_adapter; 668 669 if (aa->aa_firmware[2] >= 'A' && aa->aa_firmware[2] <= 'Z' && 670 aa->aa_firmware[1] < ' ' && aa->aa_firmware[0] < ' ' && 671 aa->aa_bios[2] >= 'A' && aa->aa_bios[2] <= 'Z' && 672 aa->aa_bios[1] < ' ' && aa->aa_bios[0] < ' ') { 673 if (le32toh(ae->ae_signature) == AMR_SIG_438) { 674 /* The AMI 438 is a NetRaid 3si in HP-land. */ 675 prodstr = "HP NetRaid 3si"; 676 } 677 ishp = 1; 678 } else 679 ishp = 0; 680 681 aprint_normal("<%s>\n", prodstr); 682 if (intrstr != NULL) 683 aprint_normal("%s: interrupting at %s\n", amr->amr_dv.dv_xname, 684 intrstr); 685 686 if (ishp) 687 aprint_normal("%s: firmware <%c.%02d.%02d>, BIOS <%c.%02d.%02d>" 688 ", %dMB RAM\n", amr->amr_dv.dv_xname, aa->aa_firmware[2], 689 aa->aa_firmware[1], aa->aa_firmware[0], aa->aa_bios[2], 690 aa->aa_bios[1], aa->aa_bios[0], aa->aa_memorysize); 691 else 692 aprint_normal("%s: firmware <%.4s>, BIOS <%.4s>, %dMB RAM\n", 693 amr->amr_dv.dv_xname, aa->aa_firmware, aa->aa_bios, 694 aa->aa_memorysize); 695 696 amr->amr_maxqueuecnt = aa->aa_maxio; 697 698 /* 699 * Record state of logical drives. 700 */ 701 if (ae->ae_ldrv.al_numdrives > AMR_MAX_UNITS) { 702 aprint_error("%s: adjust AMR_MAX_UNITS to %d (currently %d)\n", 703 amr->amr_dv.dv_xname, ae->ae_ldrv.al_numdrives, 704 AMR_MAX_UNITS); 705 amr->amr_numdrives = AMR_MAX_UNITS; 706 } else 707 amr->amr_numdrives = ae->ae_ldrv.al_numdrives; 708 709 for (i = 0; i < AMR_MAX_UNITS; i++) { 710 amr->amr_drive[i].al_size = le32toh(ae->ae_ldrv.al_size[i]); 711 amr->amr_drive[i].al_state = ae->ae_ldrv.al_state[i]; 712 amr->amr_drive[i].al_properties = ae->ae_ldrv.al_properties[i]; 713 } 714 715 return (0); 716 } 717 718 /* 719 * Flush the internal cache on each configured controller. Called at 720 * shutdown time. 721 */ 722 void 723 amr_shutdown(void *cookie) 724 { 725 extern struct cfdriver amr_cd; 726 struct amr_softc *amr; 727 struct amr_ccb *ac; 728 int i, rv, s; 729 730 for (i = 0; i < amr_cd.cd_ndevs; i++) { 731 if ((amr = device_lookup(&amr_cd, i)) == NULL) 732 continue; 733 734 if ((rv = amr_ccb_alloc(amr, &ac)) == 0) { 735 ac->ac_cmd.mb_command = AMR_CMD_FLUSH; 736 s = splbio(); 737 rv = amr_ccb_poll(amr, ac, 30000); 738 splx(s); 739 amr_ccb_free(amr, ac); 740 } 741 if (rv != 0) 742 printf("%s: unable to flush cache (%d)\n", 743 amr->amr_dv.dv_xname, rv); 744 } 745 } 746 747 /* 748 * Interrupt service routine. 749 */ 750 int 751 amr_intr(void *cookie) 752 { 753 struct amr_softc *amr; 754 struct amr_ccb *ac; 755 struct amr_mailbox_resp mbox; 756 u_int i, forus, idx; 757 758 amr = cookie; 759 forus = 0; 760 761 while ((*amr->amr_get_work)(amr, &mbox) == 0) { 762 /* Iterate over completed commands in this result. */ 763 for (i = 0; i < mbox.mb_nstatus; i++) { 764 idx = mbox.mb_completed[i] - 1; 765 ac = amr->amr_ccbs + idx; 766 767 if (idx >= amr->amr_maxqueuecnt) { 768 printf("%s: bad status (bogus ID: %u=%u)\n", 769 amr->amr_dv.dv_xname, i, idx); 770 continue; 771 } 772 773 if ((ac->ac_flags & AC_ACTIVE) == 0) { 774 printf("%s: bad status (not active; 0x04%x)\n", 775 amr->amr_dv.dv_xname, ac->ac_flags); 776 continue; 777 } 778 779 ac->ac_status = mbox.mb_status; 780 ac->ac_flags = (ac->ac_flags & ~AC_ACTIVE) | 781 AC_COMPLETE; 782 TAILQ_REMOVE(&amr->amr_ccb_active, ac, ac_chain.tailq); 783 784 if ((ac->ac_flags & AC_MOAN) != 0) 785 printf("%s: ccb %d completed\n", 786 amr->amr_dv.dv_xname, ac->ac_ident); 787 788 /* Pass notification to upper layers. */ 789 if (ac->ac_handler != NULL) 790 (*ac->ac_handler)(ac); 791 else 792 wakeup(ac); 793 } 794 forus = 1; 795 } 796 797 if (forus) 798 amr_ccb_enqueue(amr, NULL); 799 800 return (forus); 801 } 802 803 /* 804 * Create the watchdog thread. 805 */ 806 void 807 amr_thread_create(void *cookie) 808 { 809 struct amr_softc *amr; 810 int rv; 811 812 amr = cookie; 813 814 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 815 amr->amr_flags ^= AMRF_THREAD_EXIT; 816 wakeup(&amr->amr_flags); 817 return; 818 } 819 820 rv = kthread_create1(amr_thread, amr, &amr->amr_thread, "%s", 821 amr->amr_dv.dv_xname); 822 if (rv != 0) 823 aprint_error("%s: unable to create thread (%d)", 824 amr->amr_dv.dv_xname, rv); 825 else 826 amr->amr_flags |= AMRF_THREAD; 827 } 828 829 /* 830 * Watchdog thread. 831 */ 832 void 833 amr_thread(void *cookie) 834 { 835 struct amr_softc *amr; 836 struct amr_ccb *ac; 837 struct amr_logdrive *al; 838 struct amr_enquiry *ae; 839 time_t curtime; 840 int rv, i, s; 841 842 amr = cookie; 843 ae = amr->amr_enqbuf; 844 845 for (;;) { 846 tsleep(amr_thread, PWAIT, "amrwdog", AMR_WDOG_TICKS); 847 848 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 849 amr->amr_flags ^= AMRF_THREAD_EXIT; 850 wakeup(&amr->amr_flags); 851 kthread_exit(0); 852 } 853 854 s = splbio(); 855 amr_intr(cookie); 856 curtime = (time_t)mono_time.tv_sec; 857 ac = TAILQ_FIRST(&amr->amr_ccb_active); 858 while (ac != NULL) { 859 if (ac->ac_start_time + AMR_TIMEOUT > curtime) 860 break; 861 if ((ac->ac_flags & AC_MOAN) == 0) { 862 printf("%s: ccb %d timed out; mailbox:\n", 863 amr->amr_dv.dv_xname, ac->ac_ident); 864 amr_ccb_dump(amr, ac); 865 ac->ac_flags |= AC_MOAN; 866 } 867 ac = TAILQ_NEXT(ac, ac_chain.tailq); 868 } 869 splx(s); 870 871 if ((rv = amr_ccb_alloc(amr, &ac)) != 0) { 872 printf("%s: ccb_alloc failed (%d)\n", 873 amr->amr_dv.dv_xname, rv); 874 continue; 875 } 876 877 ac->ac_cmd.mb_command = AMR_CMD_ENQUIRY; 878 879 rv = amr_ccb_map(amr, ac, amr->amr_enqbuf, 880 AMR_ENQUIRY_BUFSIZE, 0); 881 if (rv != 0) { 882 printf("%s: ccb_map failed (%d)\n", 883 amr->amr_dv.dv_xname, rv); 884 amr_ccb_free(amr, ac); 885 continue; 886 } 887 888 rv = amr_ccb_wait(amr, ac); 889 amr_ccb_unmap(amr, ac); 890 if (rv != 0) { 891 printf("%s: enquiry failed (st=%d)\n", 892 amr->amr_dv.dv_xname, ac->ac_status); 893 continue; 894 } 895 amr_ccb_free(amr, ac); 896 897 al = amr->amr_drive; 898 for (i = 0; i < AMR_MAX_UNITS; i++, al++) { 899 if (al->al_dv == NULL) 900 continue; 901 if (al->al_state == ae->ae_ldrv.al_state[i]) 902 continue; 903 904 printf("%s: state changed: %s -> %s\n", 905 al->al_dv->dv_xname, 906 amr_drive_state(al->al_state, NULL), 907 amr_drive_state(ae->ae_ldrv.al_state[i], NULL)); 908 909 al->al_state = ae->ae_ldrv.al_state[i]; 910 } 911 } 912 } 913 914 /* 915 * Return a text description of a logical drive's current state. 916 */ 917 const char * 918 amr_drive_state(int state, int *happy) 919 { 920 const char *str; 921 922 state = AMR_DRV_CURSTATE(state); 923 if (state >= sizeof(amr_dstate) / sizeof(amr_dstate[0])) { 924 if (happy) 925 *happy = 1; 926 str = "status unknown"; 927 } else { 928 if (happy) 929 *happy = amr_dstate[state].ds_happy; 930 str = amr_dstate[state].ds_descr; 931 } 932 933 return (str); 934 } 935 936 /* 937 * Run a generic enquiry-style command. 938 */ 939 void * 940 amr_enquire(struct amr_softc *amr, u_int8_t cmd, u_int8_t cmdsub, 941 u_int8_t cmdqual, void *buf) 942 { 943 struct amr_ccb *ac; 944 u_int8_t *mb; 945 int rv; 946 947 if (amr_ccb_alloc(amr, &ac) != 0) 948 return (NULL); 949 950 /* Build the command proper. */ 951 mb = (u_int8_t *)&ac->ac_cmd; 952 mb[0] = cmd; 953 mb[2] = cmdsub; 954 mb[3] = cmdqual; 955 956 rv = amr_ccb_map(amr, ac, buf, AMR_ENQUIRY_BUFSIZE, 0); 957 if (rv == 0) { 958 rv = amr_ccb_poll(amr, ac, 2000); 959 amr_ccb_unmap(amr, ac); 960 } 961 amr_ccb_free(amr, ac); 962 963 return (rv ? NULL : buf); 964 } 965 966 /* 967 * Allocate and initialise a CCB. 968 */ 969 int 970 amr_ccb_alloc(struct amr_softc *amr, struct amr_ccb **acp) 971 { 972 int s; 973 974 s = splbio(); 975 if ((*acp = SLIST_FIRST(&amr->amr_ccb_freelist)) == NULL) { 976 splx(s); 977 return (EAGAIN); 978 } 979 SLIST_REMOVE_HEAD(&amr->amr_ccb_freelist, ac_chain.slist); 980 splx(s); 981 982 return (0); 983 } 984 985 /* 986 * Free a CCB. 987 */ 988 void 989 amr_ccb_free(struct amr_softc *amr, struct amr_ccb *ac) 990 { 991 int s; 992 993 memset(&ac->ac_cmd, 0, sizeof(ac->ac_cmd)); 994 ac->ac_cmd.mb_ident = ac->ac_ident + 1; 995 ac->ac_cmd.mb_busy = 1; 996 ac->ac_handler = NULL; 997 ac->ac_flags = 0; 998 999 s = splbio(); 1000 SLIST_INSERT_HEAD(&amr->amr_ccb_freelist, ac, ac_chain.slist); 1001 splx(s); 1002 } 1003 1004 /* 1005 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 1006 * the order that they were enqueued and try to submit their command blocks 1007 * to the controller for execution. 1008 */ 1009 void 1010 amr_ccb_enqueue(struct amr_softc *amr, struct amr_ccb *ac) 1011 { 1012 int s; 1013 1014 s = splbio(); 1015 1016 if (ac != NULL) 1017 SIMPLEQ_INSERT_TAIL(&amr->amr_ccb_queue, ac, ac_chain.simpleq); 1018 1019 while ((ac = SIMPLEQ_FIRST(&amr->amr_ccb_queue)) != NULL) { 1020 if ((*amr->amr_submit)(amr, ac) != 0) 1021 break; 1022 SIMPLEQ_REMOVE_HEAD(&amr->amr_ccb_queue, ac_chain.simpleq); 1023 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1024 } 1025 1026 splx(s); 1027 } 1028 1029 /* 1030 * Map the specified CCB's data buffer onto the bus, and fill the 1031 * scatter-gather list. 1032 */ 1033 int 1034 amr_ccb_map(struct amr_softc *amr, struct amr_ccb *ac, void *data, int size, 1035 int out) 1036 { 1037 struct amr_sgentry *sge; 1038 struct amr_mailbox_cmd *mb; 1039 int nsegs, i, rv, sgloff; 1040 bus_dmamap_t xfer; 1041 1042 xfer = ac->ac_xfer_map; 1043 1044 rv = bus_dmamap_load(amr->amr_dmat, xfer, data, size, NULL, 1045 BUS_DMA_NOWAIT); 1046 if (rv != 0) 1047 return (rv); 1048 1049 mb = &ac->ac_cmd; 1050 ac->ac_xfer_size = size; 1051 ac->ac_flags |= (out ? AC_XFER_OUT : AC_XFER_IN); 1052 sgloff = AMR_SGL_SIZE * ac->ac_ident; 1053 1054 /* We don't need to use a scatter/gather list for just 1 segment. */ 1055 nsegs = xfer->dm_nsegs; 1056 if (nsegs == 1) { 1057 mb->mb_nsgelem = 0; 1058 mb->mb_physaddr = htole32(xfer->dm_segs[0].ds_addr); 1059 ac->ac_flags |= AC_NOSGL; 1060 } else { 1061 mb->mb_nsgelem = nsegs; 1062 mb->mb_physaddr = htole32(amr->amr_sgls_paddr + sgloff); 1063 1064 sge = (struct amr_sgentry *)((caddr_t)amr->amr_sgls + sgloff); 1065 for (i = 0; i < nsegs; i++, sge++) { 1066 sge->sge_addr = htole32(xfer->dm_segs[i].ds_addr); 1067 sge->sge_count = htole32(xfer->dm_segs[i].ds_len); 1068 } 1069 } 1070 1071 bus_dmamap_sync(amr->amr_dmat, xfer, 0, ac->ac_xfer_size, 1072 out ? BUS_DMASYNC_PREWRITE : BUS_DMASYNC_PREREAD); 1073 1074 if ((ac->ac_flags & AC_NOSGL) == 0) 1075 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, sgloff, 1076 AMR_SGL_SIZE, BUS_DMASYNC_PREWRITE); 1077 1078 return (0); 1079 } 1080 1081 /* 1082 * Unmap the specified CCB's data buffer. 1083 */ 1084 void 1085 amr_ccb_unmap(struct amr_softc *amr, struct amr_ccb *ac) 1086 { 1087 1088 if ((ac->ac_flags & AC_NOSGL) == 0) 1089 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 1090 AMR_SGL_SIZE * ac->ac_ident, AMR_SGL_SIZE, 1091 BUS_DMASYNC_POSTWRITE); 1092 bus_dmamap_sync(amr->amr_dmat, ac->ac_xfer_map, 0, ac->ac_xfer_size, 1093 (ac->ac_flags & AC_XFER_IN) != 0 ? 1094 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1095 bus_dmamap_unload(amr->amr_dmat, ac->ac_xfer_map); 1096 } 1097 1098 /* 1099 * Submit a command to the controller and poll on completion. Return 1100 * non-zero on timeout or error. Must be called with interrupts blocked. 1101 */ 1102 int 1103 amr_ccb_poll(struct amr_softc *amr, struct amr_ccb *ac, int timo) 1104 { 1105 int rv; 1106 1107 if ((rv = (*amr->amr_submit)(amr, ac)) != 0) 1108 return (rv); 1109 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1110 1111 for (timo *= 10; timo != 0; timo--) { 1112 amr_intr(amr); 1113 if ((ac->ac_flags & AC_COMPLETE) != 0) 1114 break; 1115 DELAY(100); 1116 } 1117 1118 return (timo == 0 || ac->ac_status != 0 ? EIO : 0); 1119 } 1120 1121 /* 1122 * Submit a command to the controller and sleep on completion. Return 1123 * non-zero on error. 1124 */ 1125 int 1126 amr_ccb_wait(struct amr_softc *amr, struct amr_ccb *ac) 1127 { 1128 int s; 1129 1130 s = splbio(); 1131 amr_ccb_enqueue(amr, ac); 1132 tsleep(ac, PRIBIO, "amrcmd", 0); 1133 splx(s); 1134 1135 return (ac->ac_status != 0 ? EIO : 0); 1136 } 1137 1138 /* 1139 * Wait for the mailbox to become available. 1140 */ 1141 int 1142 amr_mbox_wait(struct amr_softc *amr) 1143 { 1144 int timo; 1145 1146 for (timo = 10000; timo != 0; timo--) { 1147 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1148 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1149 if (amr->amr_mbox->mb_cmd.mb_busy == 0) 1150 break; 1151 DELAY(100); 1152 } 1153 1154 if (timo == 0) 1155 printf("%s: controller wedged\n", amr->amr_dv.dv_xname); 1156 1157 return (timo != 0 ? 0 : EAGAIN); 1158 } 1159 1160 /* 1161 * Tell the controller that the mailbox contains a valid command. Must be 1162 * called with interrupts blocked. 1163 */ 1164 int 1165 amr_quartz_submit(struct amr_softc *amr, struct amr_ccb *ac) 1166 { 1167 u_int32_t v; 1168 1169 amr->amr_mbox->mb_poll = 0; 1170 amr->amr_mbox->mb_ack = 0; 1171 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1172 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1173 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1174 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1175 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1176 return (EAGAIN); 1177 1178 v = amr_inl(amr, AMR_QREG_IDB); 1179 if ((v & AMR_QIDB_SUBMIT) != 0) { 1180 amr->amr_mbox->mb_cmd.mb_busy = 0; 1181 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1182 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1183 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1184 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1185 return (EAGAIN); 1186 } 1187 1188 amr->amr_mbox->mb_segment = 0; 1189 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1190 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1191 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1192 1193 ac->ac_start_time = (time_t)mono_time.tv_sec; 1194 ac->ac_flags |= AC_ACTIVE; 1195 amr_outl(amr, AMR_QREG_IDB, 1196 (amr->amr_mbox_paddr + 16) | AMR_QIDB_SUBMIT); 1197 return (0); 1198 } 1199 1200 int 1201 amr_std_submit(struct amr_softc *amr, struct amr_ccb *ac) 1202 { 1203 1204 amr->amr_mbox->mb_poll = 0; 1205 amr->amr_mbox->mb_ack = 0; 1206 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1207 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1208 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1209 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1210 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1211 return (EAGAIN); 1212 1213 if ((amr_inb(amr, AMR_SREG_MBOX_BUSY) & AMR_SMBOX_BUSY_FLAG) != 0) { 1214 amr->amr_mbox->mb_cmd.mb_busy = 0; 1215 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1216 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1217 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1218 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1219 return (EAGAIN); 1220 } 1221 1222 amr->amr_mbox->mb_segment = 0; 1223 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1224 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1225 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1226 1227 ac->ac_start_time = (time_t)mono_time.tv_sec; 1228 ac->ac_flags |= AC_ACTIVE; 1229 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_POST); 1230 return (0); 1231 } 1232 1233 /* 1234 * Claim any work that the controller has completed; acknowledge completion, 1235 * save details of the completion in (mbsave). Must be called with 1236 * interrupts blocked. 1237 */ 1238 int 1239 amr_quartz_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1240 { 1241 1242 /* Work waiting for us? */ 1243 if (amr_inl(amr, AMR_QREG_ODB) != AMR_QODB_READY) 1244 return (-1); 1245 1246 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1247 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1248 1249 /* Save the mailbox, which contains a list of completed commands. */ 1250 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1251 1252 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1253 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1254 1255 /* Ack the interrupt and mailbox transfer. */ 1256 amr_outl(amr, AMR_QREG_ODB, AMR_QODB_READY); 1257 amr_outl(amr, AMR_QREG_IDB, (amr->amr_mbox_paddr+16) | AMR_QIDB_ACK); 1258 1259 /* 1260 * This waits for the controller to notice that we've taken the 1261 * command from it. It's very inefficient, and we shouldn't do it, 1262 * but if we remove this code, we stop completing commands under 1263 * load. 1264 * 1265 * Peter J says we shouldn't do this. The documentation says we 1266 * should. Who is right? 1267 */ 1268 while ((amr_inl(amr, AMR_QREG_IDB) & AMR_QIDB_ACK) != 0) 1269 DELAY(10); 1270 1271 return (0); 1272 } 1273 1274 int 1275 amr_std_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1276 { 1277 u_int8_t istat; 1278 1279 /* Check for valid interrupt status. */ 1280 if (((istat = amr_inb(amr, AMR_SREG_INTR)) & AMR_SINTR_VALID) == 0) 1281 return (-1); 1282 1283 /* Ack the interrupt. */ 1284 amr_outb(amr, AMR_SREG_INTR, istat); 1285 1286 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1287 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1288 1289 /* Save mailbox, which contains a list of completed commands. */ 1290 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1291 1292 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1293 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1294 1295 /* Ack mailbox transfer. */ 1296 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 1297 1298 return (0); 1299 } 1300 1301 void 1302 amr_ccb_dump(struct amr_softc *amr, struct amr_ccb *ac) 1303 { 1304 int i; 1305 1306 printf("%s: ", amr->amr_dv.dv_xname); 1307 for (i = 0; i < 4; i++) 1308 printf("%08x ", ((u_int32_t *)&ac->ac_cmd)[i]); 1309 printf("\n"); 1310 } 1311
Indexes created Thu Oct 02 14:10:14 GMT 2025