amr.c revision 1.25.2.1
1 /* $NetBSD: amr.c,v 1.25.2.1 2005/12/15 20:08:01 tron Exp $ */ 2 3 /*- 4 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999,2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: amr_pci.c,v 1.5 2000/08/30 07:52:40 msmith Exp 66 * from FreeBSD: amr.c,v 1.16 2000/08/30 07:52:40 msmith Exp 67 */ 68 69 /* 70 * Driver for AMI RAID controllers. 71 */ 72 73 #include <sys/cdefs.h> 74 __KERNEL_RCSID(0, "$NetBSD: amr.c,v 1.25.2.1 2005/12/15 20:08:01 tron Exp $"); 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/device.h> 80 #include <sys/queue.h> 81 #include <sys/proc.h> 82 #include <sys/buf.h> 83 #include <sys/malloc.h> 84 #include <sys/kthread.h> 85 86 #include <uvm/uvm_extern.h> 87 88 #include <machine/endian.h> 89 #include <machine/bus.h> 90 91 #include <dev/pci/pcidevs.h> 92 #include <dev/pci/pcivar.h> 93 #include <dev/pci/amrreg.h> 94 #include <dev/pci/amrvar.h> 95 96 #include "locators.h" 97 98 void amr_attach(struct device *, struct device *, void *); 99 void amr_ccb_dump(struct amr_softc *, struct amr_ccb *); 100 void *amr_enquire(struct amr_softc *, u_int8_t, u_int8_t, u_int8_t, void *); 101 int amr_init(struct amr_softc *, const char *, 102 struct pci_attach_args *pa); 103 int amr_intr(void *); 104 int amr_match(struct device *, struct cfdata *, void *); 105 int amr_print(void *, const char *); 106 void amr_shutdown(void *); 107 int amr_submatch(struct device *, struct cfdata *, 108 const locdesc_t *, void *); 109 void amr_teardown(struct amr_softc *); 110 void amr_thread(void *); 111 void amr_thread_create(void *); 112 113 int amr_mbox_wait(struct amr_softc *); 114 int amr_quartz_get_work(struct amr_softc *, struct amr_mailbox_resp *); 115 int amr_quartz_submit(struct amr_softc *, struct amr_ccb *); 116 int amr_std_get_work(struct amr_softc *, struct amr_mailbox_resp *); 117 int amr_std_submit(struct amr_softc *, struct amr_ccb *); 118 119 static inline u_int8_t amr_inb(struct amr_softc *, int); 120 static inline u_int32_t amr_inl(struct amr_softc *, int); 121 static inline void amr_outb(struct amr_softc *, int, u_int8_t); 122 static inline void amr_outl(struct amr_softc *, int, u_int32_t); 123 124 CFATTACH_DECL(amr, sizeof(struct amr_softc), 125 amr_match, amr_attach, NULL, NULL); 126 127 #define AT_QUARTZ 0x01 /* `Quartz' chipset */ 128 #define AT_SIG 0x02 /* Check for signature */ 129 130 struct amr_pci_type { 131 u_short apt_vendor; 132 u_short apt_product; 133 u_short apt_flags; 134 } const amr_pci_type[] = { 135 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID, 0 }, 136 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID2, 0 }, 137 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 138 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ | AT_SIG }, 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, 142 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, 143 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI, AT_QUARTZ }, 144 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI_2, AT_QUARTZ }, 145 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4ESI, AT_QUARTZ }, 146 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_PERC_4SC, AT_QUARTZ }, 147 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, 148 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, 149 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, 150 }; 151 152 struct amr_typestr { 153 const char *at_str; 154 int at_sig; 155 } const amr_typestr[] = { 156 { "Series 431", AMR_SIG_431 }, 157 { "Series 438", AMR_SIG_438 }, 158 { "Series 466", AMR_SIG_466 }, 159 { "Series 467", AMR_SIG_467 }, 160 { "Series 490", AMR_SIG_490 }, 161 { "Series 762", AMR_SIG_762 }, 162 { "HP NetRAID (T5)", AMR_SIG_T5 }, 163 { "HP NetRAID (T7)", AMR_SIG_T7 }, 164 }; 165 166 struct { 167 const char *ds_descr; 168 int ds_happy; 169 } const amr_dstate[] = { 170 { "offline", 0 }, 171 { "degraded", 1 }, 172 { "optimal", 1 }, 173 { "online", 1 }, 174 { "failed", 0 }, 175 { "rebuilding", 1 }, 176 { "hotspare", 0 }, 177 }; 178 179 void *amr_sdh; 180 int amr_max_segs; 181 int amr_max_xfer; 182 183 static inline u_int8_t 184 amr_inb(struct amr_softc *amr, int off) 185 { 186 187 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 188 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 189 return (bus_space_read_1(amr->amr_iot, amr->amr_ioh, off)); 190 } 191 192 static inline u_int32_t 193 amr_inl(struct amr_softc *amr, int off) 194 { 195 196 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 197 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 198 return (bus_space_read_4(amr->amr_iot, amr->amr_ioh, off)); 199 } 200 201 static inline void 202 amr_outb(struct amr_softc *amr, int off, u_int8_t val) 203 { 204 205 bus_space_write_1(amr->amr_iot, amr->amr_ioh, off, val); 206 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 207 BUS_SPACE_BARRIER_WRITE); 208 } 209 210 static inline void 211 amr_outl(struct amr_softc *amr, int off, u_int32_t val) 212 { 213 214 bus_space_write_4(amr->amr_iot, amr->amr_ioh, off, val); 215 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 216 BUS_SPACE_BARRIER_WRITE); 217 } 218 219 /* 220 * Match a supported device. 221 */ 222 int 223 amr_match(struct device *parent, struct cfdata *match, void *aux) 224 { 225 struct pci_attach_args *pa; 226 pcireg_t s; 227 int i; 228 229 pa = (struct pci_attach_args *)aux; 230 231 /* 232 * Don't match the device if it's operating in I2O mode. In this 233 * case it should be handled by the `iop' driver. 234 */ 235 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 236 return (0); 237 238 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 239 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 240 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 241 break; 242 243 if (i == sizeof(amr_pci_type) / sizeof(amr_pci_type[0])) 244 return (0); 245 246 if ((amr_pci_type[i].apt_flags & AT_SIG) == 0) 247 return (1); 248 249 s = pci_conf_read(pa->pa_pc, pa->pa_tag, AMR_QUARTZ_SIG_REG) & 0xffff; 250 return (s == AMR_QUARTZ_SIG0 || s == AMR_QUARTZ_SIG1); 251 } 252 253 /* 254 * Attach a supported device. 255 */ 256 void 257 amr_attach(struct device *parent, struct device *self, void *aux) 258 { 259 struct pci_attach_args *pa; 260 struct amr_attach_args amra; 261 const struct amr_pci_type *apt; 262 struct amr_softc *amr; 263 pci_chipset_tag_t pc; 264 pci_intr_handle_t ih; 265 const char *intrstr; 266 pcireg_t reg; 267 int rseg, i, j, size, rv, memreg, ioreg; 268 struct amr_ccb *ac; 269 int help[2]; 270 locdesc_t *ldesc = (void *)help; /* XXX */ 271 272 aprint_naive(": RAID controller\n"); 273 274 amr = (struct amr_softc *)self; 275 pa = (struct pci_attach_args *)aux; 276 pc = pa->pa_pc; 277 278 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 279 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 280 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 281 break; 282 apt = amr_pci_type + i; 283 284 memreg = ioreg = 0; 285 for (i = 0x10; i <= 0x14; i += 4) { 286 reg = pci_conf_read(pc, pa->pa_tag, i); 287 switch (PCI_MAPREG_TYPE(reg)) { 288 case PCI_MAPREG_TYPE_MEM: 289 if (PCI_MAPREG_MEM_SIZE(reg) != 0) 290 memreg = i; 291 break; 292 case PCI_MAPREG_TYPE_IO: 293 if (PCI_MAPREG_IO_SIZE(reg) != 0) 294 ioreg = i; 295 break; 296 297 } 298 } 299 300 if (memreg && pci_mapreg_map(pa, memreg, PCI_MAPREG_TYPE_MEM, 0, 301 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 302 ; 303 else if (ioreg && pci_mapreg_map(pa, ioreg, PCI_MAPREG_TYPE_IO, 0, 304 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 305 ; 306 else { 307 aprint_error("can't map control registers\n"); 308 amr_teardown(amr); 309 return; 310 } 311 312 amr->amr_flags |= AMRF_PCI_REGS; 313 amr->amr_dmat = pa->pa_dmat; 314 amr->amr_pc = pa->pa_pc; 315 316 /* Enable the device. */ 317 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 318 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 319 reg | PCI_COMMAND_MASTER_ENABLE); 320 321 /* Map and establish the interrupt. */ 322 if (pci_intr_map(pa, &ih)) { 323 aprint_error("can't map interrupt\n"); 324 amr_teardown(amr); 325 return; 326 } 327 intrstr = pci_intr_string(pc, ih); 328 amr->amr_ih = pci_intr_establish(pc, ih, IPL_BIO, amr_intr, amr); 329 if (amr->amr_ih == NULL) { 330 aprint_error("can't establish interrupt"); 331 if (intrstr != NULL) 332 aprint_normal(" at %s", intrstr); 333 aprint_normal("\n"); 334 amr_teardown(amr); 335 return; 336 } 337 amr->amr_flags |= AMRF_PCI_INTR; 338 339 /* 340 * Allocate space for the mailbox and S/G lists. Some controllers 341 * don't like S/G lists to be located below 0x2000, so we allocate 342 * enough slop to enable us to compensate. 343 * 344 * The standard mailbox structure needs to be aligned on a 16-byte 345 * boundary. The 64-bit mailbox has one extra field, 4 bytes in 346 * size, which preceeds the standard mailbox. 347 */ 348 size = AMR_SGL_SIZE * AMR_MAX_CMDS + 0x2000; 349 amr->amr_dmasize = size; 350 351 if ((rv = bus_dmamem_alloc(amr->amr_dmat, size, PAGE_SIZE, 0, 352 &amr->amr_dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 353 aprint_error("%s: unable to allocate buffer, rv = %d\n", 354 amr->amr_dv.dv_xname, rv); 355 amr_teardown(amr); 356 return; 357 } 358 amr->amr_flags |= AMRF_DMA_ALLOC; 359 360 if ((rv = bus_dmamem_map(amr->amr_dmat, &amr->amr_dmaseg, rseg, size, 361 (caddr_t *)&amr->amr_mbox, 362 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 363 aprint_error("%s: unable to map buffer, rv = %d\n", 364 amr->amr_dv.dv_xname, rv); 365 amr_teardown(amr); 366 return; 367 } 368 amr->amr_flags |= AMRF_DMA_MAP; 369 370 if ((rv = bus_dmamap_create(amr->amr_dmat, size, 1, size, 0, 371 BUS_DMA_NOWAIT, &amr->amr_dmamap)) != 0) { 372 aprint_error("%s: unable to create buffer DMA map, rv = %d\n", 373 amr->amr_dv.dv_xname, rv); 374 amr_teardown(amr); 375 return; 376 } 377 amr->amr_flags |= AMRF_DMA_CREATE; 378 379 if ((rv = bus_dmamap_load(amr->amr_dmat, amr->amr_dmamap, 380 amr->amr_mbox, size, NULL, BUS_DMA_NOWAIT)) != 0) { 381 aprint_error("%s: unable to load buffer DMA map, rv = %d\n", 382 amr->amr_dv.dv_xname, rv); 383 amr_teardown(amr); 384 return; 385 } 386 amr->amr_flags |= AMRF_DMA_LOAD; 387 388 memset(amr->amr_mbox, 0, size); 389 390 amr->amr_mbox_paddr = amr->amr_dmamap->dm_segs[0].ds_addr; 391 amr->amr_sgls_paddr = (amr->amr_mbox_paddr + 0x1fff) & ~0x1fff; 392 amr->amr_sgls = (struct amr_sgentry *)((caddr_t)amr->amr_mbox + 393 amr->amr_sgls_paddr - amr->amr_dmamap->dm_segs[0].ds_addr); 394 395 /* 396 * Allocate and initalise the command control blocks. 397 */ 398 ac = malloc(sizeof(*ac) * AMR_MAX_CMDS, M_DEVBUF, M_NOWAIT | M_ZERO); 399 amr->amr_ccbs = ac; 400 SLIST_INIT(&amr->amr_ccb_freelist); 401 TAILQ_INIT(&amr->amr_ccb_active); 402 amr->amr_flags |= AMRF_CCBS; 403 404 if (amr_max_xfer == 0) { 405 amr_max_xfer = min(((AMR_MAX_SEGS - 1) * PAGE_SIZE), MAXPHYS); 406 amr_max_segs = (amr_max_xfer + (PAGE_SIZE * 2) - 1) / PAGE_SIZE; 407 } 408 409 for (i = 0; i < AMR_MAX_CMDS; i++, ac++) { 410 rv = bus_dmamap_create(amr->amr_dmat, amr_max_xfer, 411 amr_max_segs, amr_max_xfer, 0, 412 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ac->ac_xfer_map); 413 if (rv != 0) 414 break; 415 416 ac->ac_ident = i; 417 amr_ccb_free(amr, ac); 418 } 419 if (i != AMR_MAX_CMDS) { 420 aprint_error("%s: memory exhausted\n", amr->amr_dv.dv_xname); 421 amr_teardown(amr); 422 return; 423 } 424 425 /* 426 * Take care of model-specific tasks. 427 */ 428 if ((apt->apt_flags & AT_QUARTZ) != 0) { 429 amr->amr_submit = amr_quartz_submit; 430 amr->amr_get_work = amr_quartz_get_work; 431 } else { 432 amr->amr_submit = amr_std_submit; 433 amr->amr_get_work = amr_std_get_work; 434 435 /* Notify the controller of the mailbox location. */ 436 amr_outl(amr, AMR_SREG_MBOX, (u_int32_t)amr->amr_mbox_paddr + 16); 437 amr_outb(amr, AMR_SREG_MBOX_ENABLE, AMR_SMBOX_ENABLE_ADDR); 438 439 /* Clear outstanding interrupts and enable interrupts. */ 440 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 441 amr_outb(amr, AMR_SREG_TOGL, 442 amr_inb(amr, AMR_SREG_TOGL) | AMR_STOGL_ENABLE); 443 } 444 445 /* 446 * Retrieve parameters, and tell the world about us. 447 */ 448 amr->amr_enqbuf = malloc(AMR_ENQUIRY_BUFSIZE, M_DEVBUF, M_NOWAIT); 449 amr->amr_flags |= AMRF_ENQBUF; 450 amr->amr_maxqueuecnt = i; 451 aprint_normal(": AMI RAID "); 452 if (amr_init(amr, intrstr, pa) != 0) { 453 amr_teardown(amr); 454 return; 455 } 456 457 /* 458 * Cap the maximum number of outstanding commands. AMI's Linux 459 * driver doesn't trust the controller's reported value, and lockups 460 * have been seen when we do. 461 */ 462 amr->amr_maxqueuecnt = min(amr->amr_maxqueuecnt, AMR_MAX_CMDS); 463 if (amr->amr_maxqueuecnt > i) 464 amr->amr_maxqueuecnt = i; 465 466 /* Set our `shutdownhook' before we start any device activity. */ 467 if (amr_sdh == NULL) 468 amr_sdh = shutdownhook_establish(amr_shutdown, NULL); 469 470 /* Attach sub-devices. */ 471 for (j = 0; j < amr->amr_numdrives; j++) { 472 if (amr->amr_drive[j].al_size == 0) 473 continue; 474 amra.amra_unit = j; 475 476 ldesc->len = 1; 477 ldesc->locs[AMRCF_UNIT] = j; 478 479 amr->amr_drive[j].al_dv = config_found_sm_loc(&amr->amr_dv, 480 "amr", ldesc, &amra, amr_print, amr_submatch); 481 } 482 483 SIMPLEQ_INIT(&amr->amr_ccb_queue); 484 485 /* XXX This doesn't work for newer boards yet. */ 486 if ((apt->apt_flags & AT_QUARTZ) == 0) 487 kthread_create(amr_thread_create, amr); 488 } 489 490 /* 491 * Free up resources. 492 */ 493 void 494 amr_teardown(struct amr_softc *amr) 495 { 496 struct amr_ccb *ac; 497 int fl; 498 499 fl = amr->amr_flags; 500 501 if ((fl & AMRF_THREAD) != 0) { 502 amr->amr_flags |= AMRF_THREAD_EXIT; 503 wakeup(amr_thread); 504 while ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) 505 tsleep(&amr->amr_flags, PWAIT, "amrexit", 0); 506 } 507 if ((fl & AMRF_CCBS) != 0) { 508 SLIST_FOREACH(ac, &amr->amr_ccb_freelist, ac_chain.slist) { 509 bus_dmamap_destroy(amr->amr_dmat, ac->ac_xfer_map); 510 } 511 free(amr->amr_ccbs, M_DEVBUF); 512 } 513 if ((fl & AMRF_ENQBUF) != 0) 514 free(amr->amr_enqbuf, M_DEVBUF); 515 if ((fl & AMRF_DMA_LOAD) != 0) 516 bus_dmamap_unload(amr->amr_dmat, amr->amr_dmamap); 517 if ((fl & AMRF_DMA_MAP) != 0) 518 bus_dmamem_unmap(amr->amr_dmat, (caddr_t)amr->amr_mbox, 519 amr->amr_dmasize); 520 if ((fl & AMRF_DMA_ALLOC) != 0) 521 bus_dmamem_free(amr->amr_dmat, &amr->amr_dmaseg, 1); 522 if ((fl & AMRF_DMA_CREATE) != 0) 523 bus_dmamap_destroy(amr->amr_dmat, amr->amr_dmamap); 524 if ((fl & AMRF_PCI_INTR) != 0) 525 pci_intr_disestablish(amr->amr_pc, amr->amr_ih); 526 if ((fl & AMRF_PCI_REGS) != 0) 527 bus_space_unmap(amr->amr_iot, amr->amr_ioh, amr->amr_ios); 528 } 529 530 /* 531 * Print autoconfiguration message for a sub-device. 532 */ 533 int 534 amr_print(void *aux, const char *pnp) 535 { 536 struct amr_attach_args *amra; 537 538 amra = (struct amr_attach_args *)aux; 539 540 if (pnp != NULL) 541 aprint_normal("block device at %s", pnp); 542 aprint_normal(" unit %d", amra->amra_unit); 543 return (UNCONF); 544 } 545 546 /* 547 * Match a sub-device. 548 */ 549 int 550 amr_submatch(struct device *parent, struct cfdata *cf, 551 const locdesc_t *ldesc, void *aux) 552 { 553 struct amr_attach_args *amra; 554 555 amra = (struct amr_attach_args *)aux; 556 557 if (cf->cf_loc[AMRCF_UNIT] != AMRCF_UNIT_DEFAULT && 558 cf->cf_loc[AMRCF_UNIT] != ldesc->locs[AMRCF_UNIT]) 559 return (0); 560 561 return (config_match(parent, cf, aux)); 562 } 563 564 /* 565 * Retrieve operational parameters and describe the controller. 566 */ 567 int 568 amr_init(struct amr_softc *amr, const char *intrstr, 569 struct pci_attach_args *pa) 570 { 571 struct amr_adapter_info *aa; 572 struct amr_prodinfo *ap; 573 struct amr_enquiry *ae; 574 struct amr_enquiry3 *aex; 575 const char *prodstr; 576 u_int i, sig, ishp; 577 char buf[64]; 578 579 /* 580 * Try to get 40LD product info, which tells us what the card is 581 * labelled as. 582 */ 583 ap = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_PRODUCT_INFO, 0, 584 amr->amr_enqbuf); 585 if (ap != NULL) { 586 aprint_normal("<%.80s>\n", ap->ap_product); 587 if (intrstr != NULL) 588 aprint_normal("%s: interrupting at %s\n", 589 amr->amr_dv.dv_xname, intrstr); 590 aprint_normal("%s: firmware %.16s, BIOS %.16s, %dMB RAM\n", 591 amr->amr_dv.dv_xname, ap->ap_firmware, ap->ap_bios, 592 le16toh(ap->ap_memsize)); 593 594 amr->amr_maxqueuecnt = ap->ap_maxio; 595 596 /* 597 * Fetch and record state of logical drives. 598 */ 599 aex = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_ENQ3, 600 AMR_CONFIG_ENQ3_SOLICITED_FULL, amr->amr_enqbuf); 601 if (aex == NULL) { 602 aprint_error("%s ENQUIRY3 failed\n", 603 amr->amr_dv.dv_xname); 604 return (-1); 605 } 606 607 if (aex->ae_numldrives > AMR_MAX_UNITS) { 608 aprint_error( 609 "%s: adjust AMR_MAX_UNITS to %d (currently %d)" 610 "\n", amr->amr_dv.dv_xname, AMR_MAX_UNITS, 611 amr->amr_numdrives); 612 amr->amr_numdrives = AMR_MAX_UNITS; 613 } else 614 amr->amr_numdrives = aex->ae_numldrives; 615 616 for (i = 0; i < amr->amr_numdrives; i++) { 617 amr->amr_drive[i].al_size = 618 le32toh(aex->ae_drivesize[i]); 619 amr->amr_drive[i].al_state = aex->ae_drivestate[i]; 620 amr->amr_drive[i].al_properties = aex->ae_driveprop[i]; 621 } 622 623 return (0); 624 } 625 626 /* 627 * Try 8LD extended ENQUIRY to get the controller signature. Once 628 * found, search for a product description. 629 */ 630 ae = amr_enquire(amr, AMR_CMD_EXT_ENQUIRY2, 0, 0, amr->amr_enqbuf); 631 if (ae != NULL) { 632 i = 0; 633 sig = le32toh(ae->ae_signature); 634 635 while (i < sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 636 if (amr_typestr[i].at_sig == sig) 637 break; 638 i++; 639 } 640 if (i == sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 641 snprintf(buf, sizeof(buf), 642 "unknown ENQUIRY2 sig (0x%08x)", sig); 643 prodstr = buf; 644 } else 645 prodstr = amr_typestr[i].at_str; 646 } else { 647 ae = amr_enquire(amr, AMR_CMD_ENQUIRY, 0, 0, amr->amr_enqbuf); 648 if (ae == NULL) { 649 aprint_error("%s: unsupported controller\n", 650 amr->amr_dv.dv_xname); 651 return (-1); 652 } 653 654 switch (PCI_PRODUCT(pa->pa_id)) { 655 case PCI_PRODUCT_AMI_MEGARAID: 656 prodstr = "Series 428"; 657 break; 658 case PCI_PRODUCT_AMI_MEGARAID2: 659 prodstr = "Series 434"; 660 break; 661 default: 662 snprintf(buf, sizeof(buf), "unknown PCI dev (0x%04x)", 663 PCI_PRODUCT(pa->pa_id)); 664 prodstr = buf; 665 break; 666 } 667 } 668 669 /* 670 * HP NetRaid controllers have a special encoding of the firmware 671 * and BIOS versions. The AMI version seems to have it as strings 672 * whereas the HP version does it with a leading uppercase character 673 * and two binary numbers. 674 */ 675 aa = &ae->ae_adapter; 676 677 if (aa->aa_firmware[2] >= 'A' && aa->aa_firmware[2] <= 'Z' && 678 aa->aa_firmware[1] < ' ' && aa->aa_firmware[0] < ' ' && 679 aa->aa_bios[2] >= 'A' && aa->aa_bios[2] <= 'Z' && 680 aa->aa_bios[1] < ' ' && aa->aa_bios[0] < ' ') { 681 if (le32toh(ae->ae_signature) == AMR_SIG_438) { 682 /* The AMI 438 is a NetRaid 3si in HP-land. */ 683 prodstr = "HP NetRaid 3si"; 684 } 685 ishp = 1; 686 } else 687 ishp = 0; 688 689 aprint_normal("<%s>\n", prodstr); 690 if (intrstr != NULL) 691 aprint_normal("%s: interrupting at %s\n", amr->amr_dv.dv_xname, 692 intrstr); 693 694 if (ishp) 695 aprint_normal("%s: firmware <%c.%02d.%02d>, BIOS <%c.%02d.%02d>" 696 ", %dMB RAM\n", amr->amr_dv.dv_xname, aa->aa_firmware[2], 697 aa->aa_firmware[1], aa->aa_firmware[0], aa->aa_bios[2], 698 aa->aa_bios[1], aa->aa_bios[0], aa->aa_memorysize); 699 else 700 aprint_normal("%s: firmware <%.4s>, BIOS <%.4s>, %dMB RAM\n", 701 amr->amr_dv.dv_xname, aa->aa_firmware, aa->aa_bios, 702 aa->aa_memorysize); 703 704 amr->amr_maxqueuecnt = aa->aa_maxio; 705 706 /* 707 * Record state of logical drives. 708 */ 709 if (ae->ae_ldrv.al_numdrives > AMR_MAX_UNITS) { 710 aprint_error("%s: adjust AMR_MAX_UNITS to %d (currently %d)\n", 711 amr->amr_dv.dv_xname, ae->ae_ldrv.al_numdrives, 712 AMR_MAX_UNITS); 713 amr->amr_numdrives = AMR_MAX_UNITS; 714 } else 715 amr->amr_numdrives = ae->ae_ldrv.al_numdrives; 716 717 for (i = 0; i < AMR_MAX_UNITS; i++) { 718 amr->amr_drive[i].al_size = le32toh(ae->ae_ldrv.al_size[i]); 719 amr->amr_drive[i].al_state = ae->ae_ldrv.al_state[i]; 720 amr->amr_drive[i].al_properties = ae->ae_ldrv.al_properties[i]; 721 } 722 723 return (0); 724 } 725 726 /* 727 * Flush the internal cache on each configured controller. Called at 728 * shutdown time. 729 */ 730 void 731 amr_shutdown(void *cookie) 732 { 733 extern struct cfdriver amr_cd; 734 struct amr_softc *amr; 735 struct amr_ccb *ac; 736 int i, rv, s; 737 738 for (i = 0; i < amr_cd.cd_ndevs; i++) { 739 if ((amr = device_lookup(&amr_cd, i)) == NULL) 740 continue; 741 742 if ((rv = amr_ccb_alloc(amr, &ac)) == 0) { 743 ac->ac_cmd.mb_command = AMR_CMD_FLUSH; 744 s = splbio(); 745 rv = amr_ccb_poll(amr, ac, 30000); 746 splx(s); 747 amr_ccb_free(amr, ac); 748 } 749 if (rv != 0) 750 printf("%s: unable to flush cache (%d)\n", 751 amr->amr_dv.dv_xname, rv); 752 } 753 } 754 755 /* 756 * Interrupt service routine. 757 */ 758 int 759 amr_intr(void *cookie) 760 { 761 struct amr_softc *amr; 762 struct amr_ccb *ac; 763 struct amr_mailbox_resp mbox; 764 u_int i, forus, idx; 765 766 amr = cookie; 767 forus = 0; 768 769 while ((*amr->amr_get_work)(amr, &mbox) == 0) { 770 /* Iterate over completed commands in this result. */ 771 for (i = 0; i < mbox.mb_nstatus; i++) { 772 idx = mbox.mb_completed[i] - 1; 773 ac = amr->amr_ccbs + idx; 774 775 if (idx >= amr->amr_maxqueuecnt) { 776 printf("%s: bad status (bogus ID: %u=%u)\n", 777 amr->amr_dv.dv_xname, i, idx); 778 continue; 779 } 780 781 if ((ac->ac_flags & AC_ACTIVE) == 0) { 782 printf("%s: bad status (not active; 0x04%x)\n", 783 amr->amr_dv.dv_xname, ac->ac_flags); 784 continue; 785 } 786 787 ac->ac_status = mbox.mb_status; 788 ac->ac_flags = (ac->ac_flags & ~AC_ACTIVE) | 789 AC_COMPLETE; 790 TAILQ_REMOVE(&amr->amr_ccb_active, ac, ac_chain.tailq); 791 792 if ((ac->ac_flags & AC_MOAN) != 0) 793 printf("%s: ccb %d completed\n", 794 amr->amr_dv.dv_xname, ac->ac_ident); 795 796 /* Pass notification to upper layers. */ 797 if (ac->ac_handler != NULL) 798 (*ac->ac_handler)(ac); 799 else 800 wakeup(ac); 801 } 802 forus = 1; 803 } 804 805 if (forus) 806 amr_ccb_enqueue(amr, NULL); 807 808 return (forus); 809 } 810 811 /* 812 * Create the watchdog thread. 813 */ 814 void 815 amr_thread_create(void *cookie) 816 { 817 struct amr_softc *amr; 818 int rv; 819 820 amr = cookie; 821 822 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 823 amr->amr_flags ^= AMRF_THREAD_EXIT; 824 wakeup(&amr->amr_flags); 825 return; 826 } 827 828 rv = kthread_create1(amr_thread, amr, &amr->amr_thread, "%s", 829 amr->amr_dv.dv_xname); 830 if (rv != 0) 831 aprint_error("%s: unable to create thread (%d)", 832 amr->amr_dv.dv_xname, rv); 833 else 834 amr->amr_flags |= AMRF_THREAD; 835 } 836 837 /* 838 * Watchdog thread. 839 */ 840 void 841 amr_thread(void *cookie) 842 { 843 struct amr_softc *amr; 844 struct amr_ccb *ac; 845 struct amr_logdrive *al; 846 struct amr_enquiry *ae; 847 time_t curtime; 848 int rv, i, s; 849 850 amr = cookie; 851 ae = amr->amr_enqbuf; 852 853 for (;;) { 854 tsleep(amr_thread, PWAIT, "amrwdog", AMR_WDOG_TICKS); 855 856 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 857 amr->amr_flags ^= AMRF_THREAD_EXIT; 858 wakeup(&amr->amr_flags); 859 kthread_exit(0); 860 } 861 862 s = splbio(); 863 amr_intr(cookie); 864 curtime = (time_t)mono_time.tv_sec; 865 ac = TAILQ_FIRST(&amr->amr_ccb_active); 866 while (ac != NULL) { 867 if (ac->ac_start_time + AMR_TIMEOUT > curtime) 868 break; 869 if ((ac->ac_flags & AC_MOAN) == 0) { 870 printf("%s: ccb %d timed out; mailbox:\n", 871 amr->amr_dv.dv_xname, ac->ac_ident); 872 amr_ccb_dump(amr, ac); 873 ac->ac_flags |= AC_MOAN; 874 } 875 ac = TAILQ_NEXT(ac, ac_chain.tailq); 876 } 877 splx(s); 878 879 if ((rv = amr_ccb_alloc(amr, &ac)) != 0) { 880 printf("%s: ccb_alloc failed (%d)\n", 881 amr->amr_dv.dv_xname, rv); 882 continue; 883 } 884 885 ac->ac_cmd.mb_command = AMR_CMD_ENQUIRY; 886 887 rv = amr_ccb_map(amr, ac, amr->amr_enqbuf, 888 AMR_ENQUIRY_BUFSIZE, 0); 889 if (rv != 0) { 890 printf("%s: ccb_map failed (%d)\n", 891 amr->amr_dv.dv_xname, rv); 892 amr_ccb_free(amr, ac); 893 continue; 894 } 895 896 rv = amr_ccb_wait(amr, ac); 897 amr_ccb_unmap(amr, ac); 898 if (rv != 0) { 899 printf("%s: enquiry failed (st=%d)\n", 900 amr->amr_dv.dv_xname, ac->ac_status); 901 continue; 902 } 903 amr_ccb_free(amr, ac); 904 905 al = amr->amr_drive; 906 for (i = 0; i < AMR_MAX_UNITS; i++, al++) { 907 if (al->al_dv == NULL) 908 continue; 909 if (al->al_state == ae->ae_ldrv.al_state[i]) 910 continue; 911 912 printf("%s: state changed: %s -> %s\n", 913 al->al_dv->dv_xname, 914 amr_drive_state(al->al_state, NULL), 915 amr_drive_state(ae->ae_ldrv.al_state[i], NULL)); 916 917 al->al_state = ae->ae_ldrv.al_state[i]; 918 } 919 } 920 } 921 922 /* 923 * Return a text description of a logical drive's current state. 924 */ 925 const char * 926 amr_drive_state(int state, int *happy) 927 { 928 const char *str; 929 930 state = AMR_DRV_CURSTATE(state); 931 if (state >= sizeof(amr_dstate) / sizeof(amr_dstate[0])) { 932 if (happy) 933 *happy = 1; 934 str = "status unknown"; 935 } else { 936 if (happy) 937 *happy = amr_dstate[state].ds_happy; 938 str = amr_dstate[state].ds_descr; 939 } 940 941 return (str); 942 } 943 944 /* 945 * Run a generic enquiry-style command. 946 */ 947 void * 948 amr_enquire(struct amr_softc *amr, u_int8_t cmd, u_int8_t cmdsub, 949 u_int8_t cmdqual, void *buf) 950 { 951 struct amr_ccb *ac; 952 u_int8_t *mb; 953 int rv; 954 955 if (amr_ccb_alloc(amr, &ac) != 0) 956 return (NULL); 957 958 /* Build the command proper. */ 959 mb = (u_int8_t *)&ac->ac_cmd; 960 mb[0] = cmd; 961 mb[2] = cmdsub; 962 mb[3] = cmdqual; 963 964 rv = amr_ccb_map(amr, ac, buf, AMR_ENQUIRY_BUFSIZE, 0); 965 if (rv == 0) { 966 rv = amr_ccb_poll(amr, ac, 2000); 967 amr_ccb_unmap(amr, ac); 968 } 969 amr_ccb_free(amr, ac); 970 971 return (rv ? NULL : buf); 972 } 973 974 /* 975 * Allocate and initialise a CCB. 976 */ 977 int 978 amr_ccb_alloc(struct amr_softc *amr, struct amr_ccb **acp) 979 { 980 int s; 981 982 s = splbio(); 983 if ((*acp = SLIST_FIRST(&amr->amr_ccb_freelist)) == NULL) { 984 splx(s); 985 return (EAGAIN); 986 } 987 SLIST_REMOVE_HEAD(&amr->amr_ccb_freelist, ac_chain.slist); 988 splx(s); 989 990 return (0); 991 } 992 993 /* 994 * Free a CCB. 995 */ 996 void 997 amr_ccb_free(struct amr_softc *amr, struct amr_ccb *ac) 998 { 999 int s; 1000 1001 memset(&ac->ac_cmd, 0, sizeof(ac->ac_cmd)); 1002 ac->ac_cmd.mb_ident = ac->ac_ident + 1; 1003 ac->ac_cmd.mb_busy = 1; 1004 ac->ac_handler = NULL; 1005 ac->ac_flags = 0; 1006 1007 s = splbio(); 1008 SLIST_INSERT_HEAD(&amr->amr_ccb_freelist, ac, ac_chain.slist); 1009 splx(s); 1010 } 1011 1012 /* 1013 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 1014 * the order that they were enqueued and try to submit their command blocks 1015 * to the controller for execution. 1016 */ 1017 void 1018 amr_ccb_enqueue(struct amr_softc *amr, struct amr_ccb *ac) 1019 { 1020 int s; 1021 1022 s = splbio(); 1023 1024 if (ac != NULL) 1025 SIMPLEQ_INSERT_TAIL(&amr->amr_ccb_queue, ac, ac_chain.simpleq); 1026 1027 while ((ac = SIMPLEQ_FIRST(&amr->amr_ccb_queue)) != NULL) { 1028 if ((*amr->amr_submit)(amr, ac) != 0) 1029 break; 1030 SIMPLEQ_REMOVE_HEAD(&amr->amr_ccb_queue, ac_chain.simpleq); 1031 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1032 } 1033 1034 splx(s); 1035 } 1036 1037 /* 1038 * Map the specified CCB's data buffer onto the bus, and fill the 1039 * scatter-gather list. 1040 */ 1041 int 1042 amr_ccb_map(struct amr_softc *amr, struct amr_ccb *ac, void *data, int size, 1043 int out) 1044 { 1045 struct amr_sgentry *sge; 1046 struct amr_mailbox_cmd *mb; 1047 int nsegs, i, rv, sgloff; 1048 bus_dmamap_t xfer; 1049 1050 xfer = ac->ac_xfer_map; 1051 1052 rv = bus_dmamap_load(amr->amr_dmat, xfer, data, size, NULL, 1053 BUS_DMA_NOWAIT); 1054 if (rv != 0) 1055 return (rv); 1056 1057 mb = &ac->ac_cmd; 1058 ac->ac_xfer_size = size; 1059 ac->ac_flags |= (out ? AC_XFER_OUT : AC_XFER_IN); 1060 sgloff = AMR_SGL_SIZE * ac->ac_ident; 1061 1062 /* We don't need to use a scatter/gather list for just 1 segment. */ 1063 nsegs = xfer->dm_nsegs; 1064 if (nsegs == 1) { 1065 mb->mb_nsgelem = 0; 1066 mb->mb_physaddr = htole32(xfer->dm_segs[0].ds_addr); 1067 ac->ac_flags |= AC_NOSGL; 1068 } else { 1069 mb->mb_nsgelem = nsegs; 1070 mb->mb_physaddr = htole32(amr->amr_sgls_paddr + sgloff); 1071 1072 sge = (struct amr_sgentry *)((caddr_t)amr->amr_sgls + sgloff); 1073 for (i = 0; i < nsegs; i++, sge++) { 1074 sge->sge_addr = htole32(xfer->dm_segs[i].ds_addr); 1075 sge->sge_count = htole32(xfer->dm_segs[i].ds_len); 1076 } 1077 } 1078 1079 bus_dmamap_sync(amr->amr_dmat, xfer, 0, ac->ac_xfer_size, 1080 out ? BUS_DMASYNC_PREWRITE : BUS_DMASYNC_PREREAD); 1081 1082 if ((ac->ac_flags & AC_NOSGL) == 0) 1083 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, sgloff, 1084 AMR_SGL_SIZE, BUS_DMASYNC_PREWRITE); 1085 1086 return (0); 1087 } 1088 1089 /* 1090 * Unmap the specified CCB's data buffer. 1091 */ 1092 void 1093 amr_ccb_unmap(struct amr_softc *amr, struct amr_ccb *ac) 1094 { 1095 1096 if ((ac->ac_flags & AC_NOSGL) == 0) 1097 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 1098 AMR_SGL_SIZE * ac->ac_ident, AMR_SGL_SIZE, 1099 BUS_DMASYNC_POSTWRITE); 1100 bus_dmamap_sync(amr->amr_dmat, ac->ac_xfer_map, 0, ac->ac_xfer_size, 1101 (ac->ac_flags & AC_XFER_IN) != 0 ? 1102 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1103 bus_dmamap_unload(amr->amr_dmat, ac->ac_xfer_map); 1104 } 1105 1106 /* 1107 * Submit a command to the controller and poll on completion. Return 1108 * non-zero on timeout or error. Must be called with interrupts blocked. 1109 */ 1110 int 1111 amr_ccb_poll(struct amr_softc *amr, struct amr_ccb *ac, int timo) 1112 { 1113 int rv; 1114 1115 if ((rv = (*amr->amr_submit)(amr, ac)) != 0) 1116 return (rv); 1117 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1118 1119 for (timo *= 10; timo != 0; timo--) { 1120 amr_intr(amr); 1121 if ((ac->ac_flags & AC_COMPLETE) != 0) 1122 break; 1123 DELAY(100); 1124 } 1125 1126 return (timo == 0 || ac->ac_status != 0 ? EIO : 0); 1127 } 1128 1129 /* 1130 * Submit a command to the controller and sleep on completion. Return 1131 * non-zero on error. 1132 */ 1133 int 1134 amr_ccb_wait(struct amr_softc *amr, struct amr_ccb *ac) 1135 { 1136 int s; 1137 1138 s = splbio(); 1139 amr_ccb_enqueue(amr, ac); 1140 tsleep(ac, PRIBIO, "amrcmd", 0); 1141 splx(s); 1142 1143 return (ac->ac_status != 0 ? EIO : 0); 1144 } 1145 1146 /* 1147 * Wait for the mailbox to become available. 1148 */ 1149 int 1150 amr_mbox_wait(struct amr_softc *amr) 1151 { 1152 int timo; 1153 1154 for (timo = 10000; timo != 0; timo--) { 1155 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1156 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1157 if (amr->amr_mbox->mb_cmd.mb_busy == 0) 1158 break; 1159 DELAY(100); 1160 } 1161 1162 if (timo == 0) 1163 printf("%s: controller wedged\n", amr->amr_dv.dv_xname); 1164 1165 return (timo != 0 ? 0 : EAGAIN); 1166 } 1167 1168 /* 1169 * Tell the controller that the mailbox contains a valid command. Must be 1170 * called with interrupts blocked. 1171 */ 1172 int 1173 amr_quartz_submit(struct amr_softc *amr, struct amr_ccb *ac) 1174 { 1175 u_int32_t v; 1176 1177 amr->amr_mbox->mb_poll = 0; 1178 amr->amr_mbox->mb_ack = 0; 1179 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1180 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1181 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1182 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1183 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1184 return (EAGAIN); 1185 1186 v = amr_inl(amr, AMR_QREG_IDB); 1187 if ((v & AMR_QIDB_SUBMIT) != 0) { 1188 amr->amr_mbox->mb_cmd.mb_busy = 0; 1189 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1190 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1191 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1192 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1193 return (EAGAIN); 1194 } 1195 1196 amr->amr_mbox->mb_segment = 0; 1197 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1198 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1199 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1200 1201 ac->ac_start_time = (time_t)mono_time.tv_sec; 1202 ac->ac_flags |= AC_ACTIVE; 1203 amr_outl(amr, AMR_QREG_IDB, 1204 (amr->amr_mbox_paddr + 16) | AMR_QIDB_SUBMIT); 1205 return (0); 1206 } 1207 1208 int 1209 amr_std_submit(struct amr_softc *amr, struct amr_ccb *ac) 1210 { 1211 1212 amr->amr_mbox->mb_poll = 0; 1213 amr->amr_mbox->mb_ack = 0; 1214 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1215 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1216 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1217 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1218 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1219 return (EAGAIN); 1220 1221 if ((amr_inb(amr, AMR_SREG_MBOX_BUSY) & AMR_SMBOX_BUSY_FLAG) != 0) { 1222 amr->amr_mbox->mb_cmd.mb_busy = 0; 1223 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1224 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1225 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1226 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1227 return (EAGAIN); 1228 } 1229 1230 amr->amr_mbox->mb_segment = 0; 1231 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1232 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1233 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1234 1235 ac->ac_start_time = (time_t)mono_time.tv_sec; 1236 ac->ac_flags |= AC_ACTIVE; 1237 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_POST); 1238 return (0); 1239 } 1240 1241 /* 1242 * Claim any work that the controller has completed; acknowledge completion, 1243 * save details of the completion in (mbsave). Must be called with 1244 * interrupts blocked. 1245 */ 1246 int 1247 amr_quartz_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1248 { 1249 1250 /* Work waiting for us? */ 1251 if (amr_inl(amr, AMR_QREG_ODB) != AMR_QODB_READY) 1252 return (-1); 1253 1254 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1255 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1256 1257 /* Save the mailbox, which contains a list of completed commands. */ 1258 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1259 1260 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1261 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1262 1263 /* Ack the interrupt and mailbox transfer. */ 1264 amr_outl(amr, AMR_QREG_ODB, AMR_QODB_READY); 1265 amr_outl(amr, AMR_QREG_IDB, (amr->amr_mbox_paddr+16) | AMR_QIDB_ACK); 1266 1267 /* 1268 * This waits for the controller to notice that we've taken the 1269 * command from it. It's very inefficient, and we shouldn't do it, 1270 * but if we remove this code, we stop completing commands under 1271 * load. 1272 * 1273 * Peter J says we shouldn't do this. The documentation says we 1274 * should. Who is right? 1275 */ 1276 while ((amr_inl(amr, AMR_QREG_IDB) & AMR_QIDB_ACK) != 0) 1277 DELAY(10); 1278 1279 return (0); 1280 } 1281 1282 int 1283 amr_std_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1284 { 1285 u_int8_t istat; 1286 1287 /* Check for valid interrupt status. */ 1288 if (((istat = amr_inb(amr, AMR_SREG_INTR)) & AMR_SINTR_VALID) == 0) 1289 return (-1); 1290 1291 /* Ack the interrupt. */ 1292 amr_outb(amr, AMR_SREG_INTR, istat); 1293 1294 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1295 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1296 1297 /* Save mailbox, which contains a list of completed commands. */ 1298 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1299 1300 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1301 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1302 1303 /* Ack mailbox transfer. */ 1304 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 1305 1306 return (0); 1307 } 1308 1309 void 1310 amr_ccb_dump(struct amr_softc *amr, struct amr_ccb *ac) 1311 { 1312 int i; 1313 1314 printf("%s: ", amr->amr_dv.dv_xname); 1315 for (i = 0; i < 4; i++) 1316 printf("%08x ", ((u_int32_t *)&ac->ac_cmd)[i]); 1317 printf("\n"); 1318 } 1319
Indexes created Thu Oct 02 14:10:14 GMT 2025