amr.c revision 1.25.2.2
1 /* $NetBSD: amr.c,v 1.25.2.2 2006/07/30 16:38:59 tron Exp $ */ 2 3 /*- 4 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999,2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: amr_pci.c,v 1.5 2000/08/30 07:52:40 msmith Exp 66 * from FreeBSD: amr.c,v 1.16 2000/08/30 07:52:40 msmith Exp 67 */ 68 69 /* 70 * Driver for AMI RAID controllers. 71 */ 72 73 #include <sys/cdefs.h> 74 __KERNEL_RCSID(0, "$NetBSD: amr.c,v 1.25.2.2 2006/07/30 16:38:59 tron Exp $"); 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/device.h> 80 #include <sys/queue.h> 81 #include <sys/proc.h> 82 #include <sys/buf.h> 83 #include <sys/malloc.h> 84 #include <sys/conf.h> 85 #include <sys/kthread.h> 86 87 #include <uvm/uvm_extern.h> 88 89 #include <machine/endian.h> 90 #include <machine/bus.h> 91 92 #include <dev/pci/pcidevs.h> 93 #include <dev/pci/pcivar.h> 94 #include <dev/pci/amrreg.h> 95 #include <dev/pci/amrvar.h> 96 #include <dev/pci/amrio.h> 97 98 #include "locators.h" 99 100 void amr_attach(struct device *, struct device *, void *); 101 void amr_ccb_dump(struct amr_softc *, struct amr_ccb *); 102 void *amr_enquire(struct amr_softc *, u_int8_t, u_int8_t, u_int8_t, void *); 103 int amr_init(struct amr_softc *, const char *, 104 struct pci_attach_args *pa); 105 int amr_intr(void *); 106 int amr_match(struct device *, struct cfdata *, void *); 107 int amr_print(void *, const char *); 108 void amr_shutdown(void *); 109 int amr_submatch(struct device *, struct cfdata *, 110 const locdesc_t *, void *); 111 void amr_teardown(struct amr_softc *); 112 void amr_thread(void *); 113 void amr_thread_create(void *); 114 115 int amr_mbox_wait(struct amr_softc *); 116 int amr_quartz_get_work(struct amr_softc *, struct amr_mailbox_resp *); 117 int amr_quartz_submit(struct amr_softc *, struct amr_ccb *); 118 int amr_std_get_work(struct amr_softc *, struct amr_mailbox_resp *); 119 int amr_std_submit(struct amr_softc *, struct amr_ccb *); 120 121 static inline u_int8_t amr_inb(struct amr_softc *, int); 122 static inline u_int32_t amr_inl(struct amr_softc *, int); 123 static inline void amr_outb(struct amr_softc *, int, u_int8_t); 124 static inline void amr_outl(struct amr_softc *, int, u_int32_t); 125 126 static dev_type_open(amropen); 127 static dev_type_close(amrclose); 128 static dev_type_ioctl(amrioctl); 129 130 CFATTACH_DECL(amr, sizeof(struct amr_softc), 131 amr_match, amr_attach, NULL, NULL); 132 133 const struct cdevsw amr_cdevsw = { 134 amropen, amrclose, noread, nowrite, amrioctl, 135 nostop, notty, nopoll, nommap, 136 }; 137 138 extern struct cfdriver amr_cd; 139 140 #define AT_QUARTZ 0x01 /* `Quartz' chipset */ 141 #define AT_SIG 0x02 /* Check for signature */ 142 143 struct amr_pci_type { 144 u_short apt_vendor; 145 u_short apt_product; 146 u_short apt_flags; 147 } const amr_pci_type[] = { 148 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID, 0 }, 149 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID2, 0 }, 150 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 151 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 152 { PCI_VENDOR_INTEL, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ | AT_SIG }, 153 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, 154 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, 155 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, 156 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI, AT_QUARTZ }, 157 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI_2, AT_QUARTZ }, 158 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4ESI, AT_QUARTZ }, 159 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_PERC_4SC, AT_QUARTZ }, 160 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, 161 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, 162 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, 163 }; 164 165 struct amr_typestr { 166 const char *at_str; 167 int at_sig; 168 } const amr_typestr[] = { 169 { "Series 431", AMR_SIG_431 }, 170 { "Series 438", AMR_SIG_438 }, 171 { "Series 466", AMR_SIG_466 }, 172 { "Series 467", AMR_SIG_467 }, 173 { "Series 490", AMR_SIG_490 }, 174 { "Series 762", AMR_SIG_762 }, 175 { "HP NetRAID (T5)", AMR_SIG_T5 }, 176 { "HP NetRAID (T7)", AMR_SIG_T7 }, 177 }; 178 179 struct { 180 const char *ds_descr; 181 int ds_happy; 182 } const amr_dstate[] = { 183 { "offline", 0 }, 184 { "degraded", 1 }, 185 { "optimal", 1 }, 186 { "online", 1 }, 187 { "failed", 0 }, 188 { "rebuilding", 1 }, 189 { "hotspare", 0 }, 190 }; 191 192 void *amr_sdh; 193 int amr_max_segs; 194 int amr_max_xfer; 195 196 static inline u_int8_t 197 amr_inb(struct amr_softc *amr, int off) 198 { 199 200 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 201 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 202 return (bus_space_read_1(amr->amr_iot, amr->amr_ioh, off)); 203 } 204 205 static inline u_int32_t 206 amr_inl(struct amr_softc *amr, int off) 207 { 208 209 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 210 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 211 return (bus_space_read_4(amr->amr_iot, amr->amr_ioh, off)); 212 } 213 214 static inline void 215 amr_outb(struct amr_softc *amr, int off, u_int8_t val) 216 { 217 218 bus_space_write_1(amr->amr_iot, amr->amr_ioh, off, val); 219 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 220 BUS_SPACE_BARRIER_WRITE); 221 } 222 223 static inline void 224 amr_outl(struct amr_softc *amr, int off, u_int32_t val) 225 { 226 227 bus_space_write_4(amr->amr_iot, amr->amr_ioh, off, val); 228 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 229 BUS_SPACE_BARRIER_WRITE); 230 } 231 232 /* 233 * Match a supported device. 234 */ 235 int 236 amr_match(struct device *parent, struct cfdata *match, void *aux) 237 { 238 struct pci_attach_args *pa; 239 pcireg_t s; 240 int i; 241 242 pa = (struct pci_attach_args *)aux; 243 244 /* 245 * Don't match the device if it's operating in I2O mode. In this 246 * case it should be handled by the `iop' driver. 247 */ 248 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 249 return (0); 250 251 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 252 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 253 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 254 break; 255 256 if (i == sizeof(amr_pci_type) / sizeof(amr_pci_type[0])) 257 return (0); 258 259 if ((amr_pci_type[i].apt_flags & AT_SIG) == 0) 260 return (1); 261 262 s = pci_conf_read(pa->pa_pc, pa->pa_tag, AMR_QUARTZ_SIG_REG) & 0xffff; 263 return (s == AMR_QUARTZ_SIG0 || s == AMR_QUARTZ_SIG1); 264 } 265 266 /* 267 * Attach a supported device. 268 */ 269 void 270 amr_attach(struct device *parent, struct device *self, void *aux) 271 { 272 struct pci_attach_args *pa; 273 struct amr_attach_args amra; 274 const struct amr_pci_type *apt; 275 struct amr_softc *amr; 276 pci_chipset_tag_t pc; 277 pci_intr_handle_t ih; 278 const char *intrstr; 279 pcireg_t reg; 280 int rseg, i, j, size, rv, memreg, ioreg; 281 struct amr_ccb *ac; 282 int help[2]; 283 locdesc_t *ldesc = (void *)help; /* XXX */ 284 285 aprint_naive(": RAID controller\n"); 286 287 amr = (struct amr_softc *)self; 288 pa = (struct pci_attach_args *)aux; 289 pc = pa->pa_pc; 290 291 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 292 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 293 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 294 break; 295 apt = amr_pci_type + i; 296 297 memreg = ioreg = 0; 298 for (i = 0x10; i <= 0x14; i += 4) { 299 reg = pci_conf_read(pc, pa->pa_tag, i); 300 switch (PCI_MAPREG_TYPE(reg)) { 301 case PCI_MAPREG_TYPE_MEM: 302 if (PCI_MAPREG_MEM_SIZE(reg) != 0) 303 memreg = i; 304 break; 305 case PCI_MAPREG_TYPE_IO: 306 if (PCI_MAPREG_IO_SIZE(reg) != 0) 307 ioreg = i; 308 break; 309 310 } 311 } 312 313 if (memreg && pci_mapreg_map(pa, memreg, PCI_MAPREG_TYPE_MEM, 0, 314 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 315 ; 316 else if (ioreg && pci_mapreg_map(pa, ioreg, PCI_MAPREG_TYPE_IO, 0, 317 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 318 ; 319 else { 320 aprint_error("can't map control registers\n"); 321 amr_teardown(amr); 322 return; 323 } 324 325 amr->amr_flags |= AMRF_PCI_REGS; 326 amr->amr_dmat = pa->pa_dmat; 327 amr->amr_pc = pa->pa_pc; 328 329 /* Enable the device. */ 330 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 331 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 332 reg | PCI_COMMAND_MASTER_ENABLE); 333 334 /* Map and establish the interrupt. */ 335 if (pci_intr_map(pa, &ih)) { 336 aprint_error("can't map interrupt\n"); 337 amr_teardown(amr); 338 return; 339 } 340 intrstr = pci_intr_string(pc, ih); 341 amr->amr_ih = pci_intr_establish(pc, ih, IPL_BIO, amr_intr, amr); 342 if (amr->amr_ih == NULL) { 343 aprint_error("can't establish interrupt"); 344 if (intrstr != NULL) 345 aprint_normal(" at %s", intrstr); 346 aprint_normal("\n"); 347 amr_teardown(amr); 348 return; 349 } 350 amr->amr_flags |= AMRF_PCI_INTR; 351 352 /* 353 * Allocate space for the mailbox and S/G lists. Some controllers 354 * don't like S/G lists to be located below 0x2000, so we allocate 355 * enough slop to enable us to compensate. 356 * 357 * The standard mailbox structure needs to be aligned on a 16-byte 358 * boundary. The 64-bit mailbox has one extra field, 4 bytes in 359 * size, which preceeds the standard mailbox. 360 */ 361 size = AMR_SGL_SIZE * AMR_MAX_CMDS + 0x2000; 362 amr->amr_dmasize = size; 363 364 if ((rv = bus_dmamem_alloc(amr->amr_dmat, size, PAGE_SIZE, 0, 365 &amr->amr_dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 366 aprint_error("%s: unable to allocate buffer, rv = %d\n", 367 amr->amr_dv.dv_xname, rv); 368 amr_teardown(amr); 369 return; 370 } 371 amr->amr_flags |= AMRF_DMA_ALLOC; 372 373 if ((rv = bus_dmamem_map(amr->amr_dmat, &amr->amr_dmaseg, rseg, size, 374 (caddr_t *)&amr->amr_mbox, 375 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 376 aprint_error("%s: unable to map buffer, rv = %d\n", 377 amr->amr_dv.dv_xname, rv); 378 amr_teardown(amr); 379 return; 380 } 381 amr->amr_flags |= AMRF_DMA_MAP; 382 383 if ((rv = bus_dmamap_create(amr->amr_dmat, size, 1, size, 0, 384 BUS_DMA_NOWAIT, &amr->amr_dmamap)) != 0) { 385 aprint_error("%s: unable to create buffer DMA map, rv = %d\n", 386 amr->amr_dv.dv_xname, rv); 387 amr_teardown(amr); 388 return; 389 } 390 amr->amr_flags |= AMRF_DMA_CREATE; 391 392 if ((rv = bus_dmamap_load(amr->amr_dmat, amr->amr_dmamap, 393 amr->amr_mbox, size, NULL, BUS_DMA_NOWAIT)) != 0) { 394 aprint_error("%s: unable to load buffer DMA map, rv = %d\n", 395 amr->amr_dv.dv_xname, rv); 396 amr_teardown(amr); 397 return; 398 } 399 amr->amr_flags |= AMRF_DMA_LOAD; 400 401 memset(amr->amr_mbox, 0, size); 402 403 amr->amr_mbox_paddr = amr->amr_dmamap->dm_segs[0].ds_addr; 404 amr->amr_sgls_paddr = (amr->amr_mbox_paddr + 0x1fff) & ~0x1fff; 405 amr->amr_sgls = (struct amr_sgentry *)((caddr_t)amr->amr_mbox + 406 amr->amr_sgls_paddr - amr->amr_dmamap->dm_segs[0].ds_addr); 407 408 /* 409 * Allocate and initalise the command control blocks. 410 */ 411 ac = malloc(sizeof(*ac) * AMR_MAX_CMDS, M_DEVBUF, M_NOWAIT | M_ZERO); 412 amr->amr_ccbs = ac; 413 SLIST_INIT(&amr->amr_ccb_freelist); 414 TAILQ_INIT(&amr->amr_ccb_active); 415 amr->amr_flags |= AMRF_CCBS; 416 417 if (amr_max_xfer == 0) { 418 amr_max_xfer = min(((AMR_MAX_SEGS - 1) * PAGE_SIZE), MAXPHYS); 419 amr_max_segs = (amr_max_xfer + (PAGE_SIZE * 2) - 1) / PAGE_SIZE; 420 } 421 422 for (i = 0; i < AMR_MAX_CMDS; i++, ac++) { 423 rv = bus_dmamap_create(amr->amr_dmat, amr_max_xfer, 424 amr_max_segs, amr_max_xfer, 0, 425 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ac->ac_xfer_map); 426 if (rv != 0) 427 break; 428 429 ac->ac_ident = i; 430 amr_ccb_free(amr, ac); 431 } 432 if (i != AMR_MAX_CMDS) { 433 aprint_error("%s: memory exhausted\n", amr->amr_dv.dv_xname); 434 amr_teardown(amr); 435 return; 436 } 437 438 /* 439 * Take care of model-specific tasks. 440 */ 441 if ((apt->apt_flags & AT_QUARTZ) != 0) { 442 amr->amr_submit = amr_quartz_submit; 443 amr->amr_get_work = amr_quartz_get_work; 444 } else { 445 amr->amr_submit = amr_std_submit; 446 amr->amr_get_work = amr_std_get_work; 447 448 /* Notify the controller of the mailbox location. */ 449 amr_outl(amr, AMR_SREG_MBOX, (u_int32_t)amr->amr_mbox_paddr + 16); 450 amr_outb(amr, AMR_SREG_MBOX_ENABLE, AMR_SMBOX_ENABLE_ADDR); 451 452 /* Clear outstanding interrupts and enable interrupts. */ 453 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 454 amr_outb(amr, AMR_SREG_TOGL, 455 amr_inb(amr, AMR_SREG_TOGL) | AMR_STOGL_ENABLE); 456 } 457 458 /* 459 * Retrieve parameters, and tell the world about us. 460 */ 461 amr->amr_enqbuf = malloc(AMR_ENQUIRY_BUFSIZE, M_DEVBUF, M_NOWAIT); 462 amr->amr_flags |= AMRF_ENQBUF; 463 amr->amr_maxqueuecnt = i; 464 aprint_normal(": AMI RAID "); 465 if (amr_init(amr, intrstr, pa) != 0) { 466 amr_teardown(amr); 467 return; 468 } 469 470 /* 471 * Cap the maximum number of outstanding commands. AMI's Linux 472 * driver doesn't trust the controller's reported value, and lockups 473 * have been seen when we do. 474 */ 475 amr->amr_maxqueuecnt = min(amr->amr_maxqueuecnt, AMR_MAX_CMDS); 476 if (amr->amr_maxqueuecnt > i) 477 amr->amr_maxqueuecnt = i; 478 479 /* Set our `shutdownhook' before we start any device activity. */ 480 if (amr_sdh == NULL) 481 amr_sdh = shutdownhook_establish(amr_shutdown, NULL); 482 483 /* Attach sub-devices. */ 484 for (j = 0; j < amr->amr_numdrives; j++) { 485 if (amr->amr_drive[j].al_size == 0) 486 continue; 487 amra.amra_unit = j; 488 489 ldesc->len = 1; 490 ldesc->locs[AMRCF_UNIT] = j; 491 492 amr->amr_drive[j].al_dv = config_found_sm_loc(&amr->amr_dv, 493 "amr", ldesc, &amra, amr_print, amr_submatch); 494 } 495 496 SIMPLEQ_INIT(&amr->amr_ccb_queue); 497 498 /* XXX This doesn't work for newer boards yet. */ 499 if ((apt->apt_flags & AT_QUARTZ) == 0) 500 kthread_create(amr_thread_create, amr); 501 } 502 503 /* 504 * Free up resources. 505 */ 506 void 507 amr_teardown(struct amr_softc *amr) 508 { 509 struct amr_ccb *ac; 510 int fl; 511 512 fl = amr->amr_flags; 513 514 if ((fl & AMRF_THREAD) != 0) { 515 amr->amr_flags |= AMRF_THREAD_EXIT; 516 wakeup(amr_thread); 517 while ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) 518 tsleep(&amr->amr_flags, PWAIT, "amrexit", 0); 519 } 520 if ((fl & AMRF_CCBS) != 0) { 521 SLIST_FOREACH(ac, &amr->amr_ccb_freelist, ac_chain.slist) { 522 bus_dmamap_destroy(amr->amr_dmat, ac->ac_xfer_map); 523 } 524 free(amr->amr_ccbs, M_DEVBUF); 525 } 526 if ((fl & AMRF_ENQBUF) != 0) 527 free(amr->amr_enqbuf, M_DEVBUF); 528 if ((fl & AMRF_DMA_LOAD) != 0) 529 bus_dmamap_unload(amr->amr_dmat, amr->amr_dmamap); 530 if ((fl & AMRF_DMA_MAP) != 0) 531 bus_dmamem_unmap(amr->amr_dmat, (caddr_t)amr->amr_mbox, 532 amr->amr_dmasize); 533 if ((fl & AMRF_DMA_ALLOC) != 0) 534 bus_dmamem_free(amr->amr_dmat, &amr->amr_dmaseg, 1); 535 if ((fl & AMRF_DMA_CREATE) != 0) 536 bus_dmamap_destroy(amr->amr_dmat, amr->amr_dmamap); 537 if ((fl & AMRF_PCI_INTR) != 0) 538 pci_intr_disestablish(amr->amr_pc, amr->amr_ih); 539 if ((fl & AMRF_PCI_REGS) != 0) 540 bus_space_unmap(amr->amr_iot, amr->amr_ioh, amr->amr_ios); 541 } 542 543 /* 544 * Print autoconfiguration message for a sub-device. 545 */ 546 int 547 amr_print(void *aux, const char *pnp) 548 { 549 struct amr_attach_args *amra; 550 551 amra = (struct amr_attach_args *)aux; 552 553 if (pnp != NULL) 554 aprint_normal("block device at %s", pnp); 555 aprint_normal(" unit %d", amra->amra_unit); 556 return (UNCONF); 557 } 558 559 /* 560 * Match a sub-device. 561 */ 562 int 563 amr_submatch(struct device *parent, struct cfdata *cf, 564 const locdesc_t *ldesc, void *aux) 565 { 566 struct amr_attach_args *amra; 567 568 amra = (struct amr_attach_args *)aux; 569 570 if (cf->cf_loc[AMRCF_UNIT] != AMRCF_UNIT_DEFAULT && 571 cf->cf_loc[AMRCF_UNIT] != ldesc->locs[AMRCF_UNIT]) 572 return (0); 573 574 return (config_match(parent, cf, aux)); 575 } 576 577 /* 578 * Retrieve operational parameters and describe the controller. 579 */ 580 int 581 amr_init(struct amr_softc *amr, const char *intrstr, 582 struct pci_attach_args *pa) 583 { 584 struct amr_adapter_info *aa; 585 struct amr_prodinfo *ap; 586 struct amr_enquiry *ae; 587 struct amr_enquiry3 *aex; 588 const char *prodstr; 589 u_int i, sig, ishp; 590 char buf[64]; 591 592 /* 593 * Try to get 40LD product info, which tells us what the card is 594 * labelled as. 595 */ 596 ap = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_PRODUCT_INFO, 0, 597 amr->amr_enqbuf); 598 if (ap != NULL) { 599 aprint_normal("<%.80s>\n", ap->ap_product); 600 if (intrstr != NULL) 601 aprint_normal("%s: interrupting at %s\n", 602 amr->amr_dv.dv_xname, intrstr); 603 aprint_normal("%s: firmware %.16s, BIOS %.16s, %dMB RAM\n", 604 amr->amr_dv.dv_xname, ap->ap_firmware, ap->ap_bios, 605 le16toh(ap->ap_memsize)); 606 607 amr->amr_maxqueuecnt = ap->ap_maxio; 608 609 /* 610 * Fetch and record state of logical drives. 611 */ 612 aex = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_ENQ3, 613 AMR_CONFIG_ENQ3_SOLICITED_FULL, amr->amr_enqbuf); 614 if (aex == NULL) { 615 aprint_error("%s ENQUIRY3 failed\n", 616 amr->amr_dv.dv_xname); 617 return (-1); 618 } 619 620 if (aex->ae_numldrives > AMR_MAX_UNITS) { 621 aprint_error( 622 "%s: adjust AMR_MAX_UNITS to %d (currently %d)" 623 "\n", amr->amr_dv.dv_xname, AMR_MAX_UNITS, 624 amr->amr_numdrives); 625 amr->amr_numdrives = AMR_MAX_UNITS; 626 } else 627 amr->amr_numdrives = aex->ae_numldrives; 628 629 for (i = 0; i < amr->amr_numdrives; i++) { 630 amr->amr_drive[i].al_size = 631 le32toh(aex->ae_drivesize[i]); 632 amr->amr_drive[i].al_state = aex->ae_drivestate[i]; 633 amr->amr_drive[i].al_properties = aex->ae_driveprop[i]; 634 } 635 636 return (0); 637 } 638 639 /* 640 * Try 8LD extended ENQUIRY to get the controller signature. Once 641 * found, search for a product description. 642 */ 643 ae = amr_enquire(amr, AMR_CMD_EXT_ENQUIRY2, 0, 0, amr->amr_enqbuf); 644 if (ae != NULL) { 645 i = 0; 646 sig = le32toh(ae->ae_signature); 647 648 while (i < sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 649 if (amr_typestr[i].at_sig == sig) 650 break; 651 i++; 652 } 653 if (i == sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 654 snprintf(buf, sizeof(buf), 655 "unknown ENQUIRY2 sig (0x%08x)", sig); 656 prodstr = buf; 657 } else 658 prodstr = amr_typestr[i].at_str; 659 } else { 660 ae = amr_enquire(amr, AMR_CMD_ENQUIRY, 0, 0, amr->amr_enqbuf); 661 if (ae == NULL) { 662 aprint_error("%s: unsupported controller\n", 663 amr->amr_dv.dv_xname); 664 return (-1); 665 } 666 667 switch (PCI_PRODUCT(pa->pa_id)) { 668 case PCI_PRODUCT_AMI_MEGARAID: 669 prodstr = "Series 428"; 670 break; 671 case PCI_PRODUCT_AMI_MEGARAID2: 672 prodstr = "Series 434"; 673 break; 674 default: 675 snprintf(buf, sizeof(buf), "unknown PCI dev (0x%04x)", 676 PCI_PRODUCT(pa->pa_id)); 677 prodstr = buf; 678 break; 679 } 680 } 681 682 /* 683 * HP NetRaid controllers have a special encoding of the firmware 684 * and BIOS versions. The AMI version seems to have it as strings 685 * whereas the HP version does it with a leading uppercase character 686 * and two binary numbers. 687 */ 688 aa = &ae->ae_adapter; 689 690 if (aa->aa_firmware[2] >= 'A' && aa->aa_firmware[2] <= 'Z' && 691 aa->aa_firmware[1] < ' ' && aa->aa_firmware[0] < ' ' && 692 aa->aa_bios[2] >= 'A' && aa->aa_bios[2] <= 'Z' && 693 aa->aa_bios[1] < ' ' && aa->aa_bios[0] < ' ') { 694 if (le32toh(ae->ae_signature) == AMR_SIG_438) { 695 /* The AMI 438 is a NetRaid 3si in HP-land. */ 696 prodstr = "HP NetRaid 3si"; 697 } 698 ishp = 1; 699 } else 700 ishp = 0; 701 702 aprint_normal("<%s>\n", prodstr); 703 if (intrstr != NULL) 704 aprint_normal("%s: interrupting at %s\n", amr->amr_dv.dv_xname, 705 intrstr); 706 707 if (ishp) 708 aprint_normal("%s: firmware <%c.%02d.%02d>, BIOS <%c.%02d.%02d>" 709 ", %dMB RAM\n", amr->amr_dv.dv_xname, aa->aa_firmware[2], 710 aa->aa_firmware[1], aa->aa_firmware[0], aa->aa_bios[2], 711 aa->aa_bios[1], aa->aa_bios[0], aa->aa_memorysize); 712 else 713 aprint_normal("%s: firmware <%.4s>, BIOS <%.4s>, %dMB RAM\n", 714 amr->amr_dv.dv_xname, aa->aa_firmware, aa->aa_bios, 715 aa->aa_memorysize); 716 717 amr->amr_maxqueuecnt = aa->aa_maxio; 718 719 /* 720 * Record state of logical drives. 721 */ 722 if (ae->ae_ldrv.al_numdrives > AMR_MAX_UNITS) { 723 aprint_error("%s: adjust AMR_MAX_UNITS to %d (currently %d)\n", 724 amr->amr_dv.dv_xname, ae->ae_ldrv.al_numdrives, 725 AMR_MAX_UNITS); 726 amr->amr_numdrives = AMR_MAX_UNITS; 727 } else 728 amr->amr_numdrives = ae->ae_ldrv.al_numdrives; 729 730 for (i = 0; i < AMR_MAX_UNITS; i++) { 731 amr->amr_drive[i].al_size = le32toh(ae->ae_ldrv.al_size[i]); 732 amr->amr_drive[i].al_state = ae->ae_ldrv.al_state[i]; 733 amr->amr_drive[i].al_properties = ae->ae_ldrv.al_properties[i]; 734 } 735 736 return (0); 737 } 738 739 /* 740 * Flush the internal cache on each configured controller. Called at 741 * shutdown time. 742 */ 743 void 744 amr_shutdown(void *cookie) 745 { 746 extern struct cfdriver amr_cd; 747 struct amr_softc *amr; 748 struct amr_ccb *ac; 749 int i, rv, s; 750 751 for (i = 0; i < amr_cd.cd_ndevs; i++) { 752 if ((amr = device_lookup(&amr_cd, i)) == NULL) 753 continue; 754 755 if ((rv = amr_ccb_alloc(amr, &ac)) == 0) { 756 ac->ac_cmd.mb_command = AMR_CMD_FLUSH; 757 s = splbio(); 758 rv = amr_ccb_poll(amr, ac, 30000); 759 splx(s); 760 amr_ccb_free(amr, ac); 761 } 762 if (rv != 0) 763 printf("%s: unable to flush cache (%d)\n", 764 amr->amr_dv.dv_xname, rv); 765 } 766 } 767 768 /* 769 * Interrupt service routine. 770 */ 771 int 772 amr_intr(void *cookie) 773 { 774 struct amr_softc *amr; 775 struct amr_ccb *ac; 776 struct amr_mailbox_resp mbox; 777 u_int i, forus, idx; 778 779 amr = cookie; 780 forus = 0; 781 782 while ((*amr->amr_get_work)(amr, &mbox) == 0) { 783 /* Iterate over completed commands in this result. */ 784 for (i = 0; i < mbox.mb_nstatus; i++) { 785 idx = mbox.mb_completed[i] - 1; 786 ac = amr->amr_ccbs + idx; 787 788 if (idx >= amr->amr_maxqueuecnt) { 789 printf("%s: bad status (bogus ID: %u=%u)\n", 790 amr->amr_dv.dv_xname, i, idx); 791 continue; 792 } 793 794 if ((ac->ac_flags & AC_ACTIVE) == 0) { 795 printf("%s: bad status (not active; 0x04%x)\n", 796 amr->amr_dv.dv_xname, ac->ac_flags); 797 continue; 798 } 799 800 ac->ac_status = mbox.mb_status; 801 ac->ac_flags = (ac->ac_flags & ~AC_ACTIVE) | 802 AC_COMPLETE; 803 TAILQ_REMOVE(&amr->amr_ccb_active, ac, ac_chain.tailq); 804 805 if ((ac->ac_flags & AC_MOAN) != 0) 806 printf("%s: ccb %d completed\n", 807 amr->amr_dv.dv_xname, ac->ac_ident); 808 809 /* Pass notification to upper layers. */ 810 if (ac->ac_handler != NULL) 811 (*ac->ac_handler)(ac); 812 else 813 wakeup(ac); 814 } 815 forus = 1; 816 } 817 818 if (forus) 819 amr_ccb_enqueue(amr, NULL); 820 821 return (forus); 822 } 823 824 /* 825 * Create the watchdog thread. 826 */ 827 void 828 amr_thread_create(void *cookie) 829 { 830 struct amr_softc *amr; 831 int rv; 832 833 amr = cookie; 834 835 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 836 amr->amr_flags ^= AMRF_THREAD_EXIT; 837 wakeup(&amr->amr_flags); 838 return; 839 } 840 841 rv = kthread_create1(amr_thread, amr, &amr->amr_thread, "%s", 842 amr->amr_dv.dv_xname); 843 if (rv != 0) 844 aprint_error("%s: unable to create thread (%d)", 845 amr->amr_dv.dv_xname, rv); 846 else 847 amr->amr_flags |= AMRF_THREAD; 848 } 849 850 /* 851 * Watchdog thread. 852 */ 853 void 854 amr_thread(void *cookie) 855 { 856 struct amr_softc *amr; 857 struct amr_ccb *ac; 858 struct amr_logdrive *al; 859 struct amr_enquiry *ae; 860 time_t curtime; 861 int rv, i, s; 862 863 amr = cookie; 864 ae = amr->amr_enqbuf; 865 866 for (;;) { 867 tsleep(amr_thread, PWAIT, "amrwdog", AMR_WDOG_TICKS); 868 869 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 870 amr->amr_flags ^= AMRF_THREAD_EXIT; 871 wakeup(&amr->amr_flags); 872 kthread_exit(0); 873 } 874 875 s = splbio(); 876 amr_intr(cookie); 877 curtime = (time_t)mono_time.tv_sec; 878 ac = TAILQ_FIRST(&amr->amr_ccb_active); 879 while (ac != NULL) { 880 if (ac->ac_start_time + AMR_TIMEOUT > curtime) 881 break; 882 if ((ac->ac_flags & AC_MOAN) == 0) { 883 printf("%s: ccb %d timed out; mailbox:\n", 884 amr->amr_dv.dv_xname, ac->ac_ident); 885 amr_ccb_dump(amr, ac); 886 ac->ac_flags |= AC_MOAN; 887 } 888 ac = TAILQ_NEXT(ac, ac_chain.tailq); 889 } 890 splx(s); 891 892 if ((rv = amr_ccb_alloc(amr, &ac)) != 0) { 893 printf("%s: ccb_alloc failed (%d)\n", 894 amr->amr_dv.dv_xname, rv); 895 continue; 896 } 897 898 ac->ac_cmd.mb_command = AMR_CMD_ENQUIRY; 899 900 rv = amr_ccb_map(amr, ac, amr->amr_enqbuf, 901 AMR_ENQUIRY_BUFSIZE, AC_XFER_IN); 902 if (rv != 0) { 903 printf("%s: ccb_map failed (%d)\n", 904 amr->amr_dv.dv_xname, rv); 905 amr_ccb_free(amr, ac); 906 continue; 907 } 908 909 rv = amr_ccb_wait(amr, ac); 910 amr_ccb_unmap(amr, ac); 911 if (rv != 0) { 912 printf("%s: enquiry failed (st=%d)\n", 913 amr->amr_dv.dv_xname, ac->ac_status); 914 continue; 915 } 916 amr_ccb_free(amr, ac); 917 918 al = amr->amr_drive; 919 for (i = 0; i < AMR_MAX_UNITS; i++, al++) { 920 if (al->al_dv == NULL) 921 continue; 922 if (al->al_state == ae->ae_ldrv.al_state[i]) 923 continue; 924 925 printf("%s: state changed: %s -> %s\n", 926 al->al_dv->dv_xname, 927 amr_drive_state(al->al_state, NULL), 928 amr_drive_state(ae->ae_ldrv.al_state[i], NULL)); 929 930 al->al_state = ae->ae_ldrv.al_state[i]; 931 } 932 } 933 } 934 935 /* 936 * Return a text description of a logical drive's current state. 937 */ 938 const char * 939 amr_drive_state(int state, int *happy) 940 { 941 const char *str; 942 943 state = AMR_DRV_CURSTATE(state); 944 if (state >= sizeof(amr_dstate) / sizeof(amr_dstate[0])) { 945 if (happy) 946 *happy = 1; 947 str = "status unknown"; 948 } else { 949 if (happy) 950 *happy = amr_dstate[state].ds_happy; 951 str = amr_dstate[state].ds_descr; 952 } 953 954 return (str); 955 } 956 957 /* 958 * Run a generic enquiry-style command. 959 */ 960 void * 961 amr_enquire(struct amr_softc *amr, u_int8_t cmd, u_int8_t cmdsub, 962 u_int8_t cmdqual, void *buf) 963 { 964 struct amr_ccb *ac; 965 u_int8_t *mb; 966 int rv; 967 968 if (amr_ccb_alloc(amr, &ac) != 0) 969 return (NULL); 970 971 /* Build the command proper. */ 972 mb = (u_int8_t *)&ac->ac_cmd; 973 mb[0] = cmd; 974 mb[2] = cmdsub; 975 mb[3] = cmdqual; 976 977 rv = amr_ccb_map(amr, ac, buf, AMR_ENQUIRY_BUFSIZE, AC_XFER_IN); 978 if (rv == 0) { 979 rv = amr_ccb_poll(amr, ac, 2000); 980 amr_ccb_unmap(amr, ac); 981 } 982 amr_ccb_free(amr, ac); 983 984 return (rv ? NULL : buf); 985 } 986 987 /* 988 * Allocate and initialise a CCB. 989 */ 990 int 991 amr_ccb_alloc(struct amr_softc *amr, struct amr_ccb **acp) 992 { 993 int s; 994 995 s = splbio(); 996 if ((*acp = SLIST_FIRST(&amr->amr_ccb_freelist)) == NULL) { 997 splx(s); 998 return (EAGAIN); 999 } 1000 SLIST_REMOVE_HEAD(&amr->amr_ccb_freelist, ac_chain.slist); 1001 splx(s); 1002 1003 return (0); 1004 } 1005 1006 /* 1007 * Free a CCB. 1008 */ 1009 void 1010 amr_ccb_free(struct amr_softc *amr, struct amr_ccb *ac) 1011 { 1012 int s; 1013 1014 memset(&ac->ac_cmd, 0, sizeof(ac->ac_cmd)); 1015 ac->ac_cmd.mb_ident = ac->ac_ident + 1; 1016 ac->ac_cmd.mb_busy = 1; 1017 ac->ac_handler = NULL; 1018 ac->ac_flags = 0; 1019 1020 s = splbio(); 1021 SLIST_INSERT_HEAD(&amr->amr_ccb_freelist, ac, ac_chain.slist); 1022 splx(s); 1023 } 1024 1025 /* 1026 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 1027 * the order that they were enqueued and try to submit their command blocks 1028 * to the controller for execution. 1029 */ 1030 void 1031 amr_ccb_enqueue(struct amr_softc *amr, struct amr_ccb *ac) 1032 { 1033 int s; 1034 1035 s = splbio(); 1036 1037 if (ac != NULL) 1038 SIMPLEQ_INSERT_TAIL(&amr->amr_ccb_queue, ac, ac_chain.simpleq); 1039 1040 while ((ac = SIMPLEQ_FIRST(&amr->amr_ccb_queue)) != NULL) { 1041 if ((*amr->amr_submit)(amr, ac) != 0) 1042 break; 1043 SIMPLEQ_REMOVE_HEAD(&amr->amr_ccb_queue, ac_chain.simpleq); 1044 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1045 } 1046 1047 splx(s); 1048 } 1049 1050 /* 1051 * Map the specified CCB's data buffer onto the bus, and fill the 1052 * scatter-gather list. 1053 */ 1054 int 1055 amr_ccb_map(struct amr_softc *amr, struct amr_ccb *ac, void *data, int size, 1056 int tflag) 1057 { 1058 struct amr_sgentry *sge; 1059 struct amr_mailbox_cmd *mb; 1060 int nsegs, i, rv, sgloff; 1061 bus_dmamap_t xfer; 1062 int dmaflag = 0; 1063 1064 xfer = ac->ac_xfer_map; 1065 1066 rv = bus_dmamap_load(amr->amr_dmat, xfer, data, size, NULL, 1067 BUS_DMA_NOWAIT); 1068 if (rv != 0) 1069 return (rv); 1070 1071 mb = &ac->ac_cmd; 1072 ac->ac_xfer_size = size; 1073 ac->ac_flags |= (tflag & (AC_XFER_OUT | AC_XFER_IN)); 1074 sgloff = AMR_SGL_SIZE * ac->ac_ident; 1075 1076 if (tflag & AC_XFER_OUT) 1077 dmaflag |= BUS_DMASYNC_PREWRITE; 1078 if (tflag & AC_XFER_IN) 1079 dmaflag |= BUS_DMASYNC_PREREAD; 1080 1081 /* We don't need to use a scatter/gather list for just 1 segment. */ 1082 nsegs = xfer->dm_nsegs; 1083 if (nsegs == 1) { 1084 mb->mb_nsgelem = 0; 1085 mb->mb_physaddr = htole32(xfer->dm_segs[0].ds_addr); 1086 ac->ac_flags |= AC_NOSGL; 1087 } else { 1088 mb->mb_nsgelem = nsegs; 1089 mb->mb_physaddr = htole32(amr->amr_sgls_paddr + sgloff); 1090 1091 sge = (struct amr_sgentry *)((caddr_t)amr->amr_sgls + sgloff); 1092 for (i = 0; i < nsegs; i++, sge++) { 1093 sge->sge_addr = htole32(xfer->dm_segs[i].ds_addr); 1094 sge->sge_count = htole32(xfer->dm_segs[i].ds_len); 1095 } 1096 } 1097 1098 bus_dmamap_sync(amr->amr_dmat, xfer, 0, ac->ac_xfer_size, dmaflag); 1099 1100 if ((ac->ac_flags & AC_NOSGL) == 0) 1101 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, sgloff, 1102 AMR_SGL_SIZE, BUS_DMASYNC_PREWRITE); 1103 1104 return (0); 1105 } 1106 1107 /* 1108 * Unmap the specified CCB's data buffer. 1109 */ 1110 void 1111 amr_ccb_unmap(struct amr_softc *amr, struct amr_ccb *ac) 1112 { 1113 int dmaflag = 0; 1114 1115 if (ac->ac_flags & AC_XFER_IN) 1116 dmaflag |= BUS_DMASYNC_POSTREAD; 1117 if (ac->ac_flags & AC_XFER_OUT) 1118 dmaflag |= BUS_DMASYNC_POSTWRITE; 1119 1120 if ((ac->ac_flags & AC_NOSGL) == 0) 1121 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 1122 AMR_SGL_SIZE * ac->ac_ident, AMR_SGL_SIZE, 1123 BUS_DMASYNC_POSTWRITE); 1124 bus_dmamap_sync(amr->amr_dmat, ac->ac_xfer_map, 0, ac->ac_xfer_size, 1125 dmaflag); 1126 bus_dmamap_unload(amr->amr_dmat, ac->ac_xfer_map); 1127 } 1128 1129 /* 1130 * Submit a command to the controller and poll on completion. Return 1131 * non-zero on timeout or error. Must be called with interrupts blocked. 1132 */ 1133 int 1134 amr_ccb_poll(struct amr_softc *amr, struct amr_ccb *ac, int timo) 1135 { 1136 int rv; 1137 1138 if ((rv = (*amr->amr_submit)(amr, ac)) != 0) 1139 return (rv); 1140 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1141 1142 for (timo *= 10; timo != 0; timo--) { 1143 amr_intr(amr); 1144 if ((ac->ac_flags & AC_COMPLETE) != 0) 1145 break; 1146 DELAY(100); 1147 } 1148 1149 return (timo == 0 || ac->ac_status != 0 ? EIO : 0); 1150 } 1151 1152 /* 1153 * Submit a command to the controller and sleep on completion. Return 1154 * non-zero on error. 1155 */ 1156 int 1157 amr_ccb_wait(struct amr_softc *amr, struct amr_ccb *ac) 1158 { 1159 int s; 1160 1161 s = splbio(); 1162 amr_ccb_enqueue(amr, ac); 1163 tsleep(ac, PRIBIO, "amrcmd", 0); 1164 splx(s); 1165 1166 return (ac->ac_status != 0 ? EIO : 0); 1167 } 1168 1169 /* 1170 * Wait for the mailbox to become available. 1171 */ 1172 int 1173 amr_mbox_wait(struct amr_softc *amr) 1174 { 1175 int timo; 1176 1177 for (timo = 10000; timo != 0; timo--) { 1178 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1179 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1180 if (amr->amr_mbox->mb_cmd.mb_busy == 0) 1181 break; 1182 DELAY(100); 1183 } 1184 1185 if (timo == 0) 1186 printf("%s: controller wedged\n", amr->amr_dv.dv_xname); 1187 1188 return (timo != 0 ? 0 : EAGAIN); 1189 } 1190 1191 /* 1192 * Tell the controller that the mailbox contains a valid command. Must be 1193 * called with interrupts blocked. 1194 */ 1195 int 1196 amr_quartz_submit(struct amr_softc *amr, struct amr_ccb *ac) 1197 { 1198 u_int32_t v; 1199 1200 amr->amr_mbox->mb_poll = 0; 1201 amr->amr_mbox->mb_ack = 0; 1202 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1203 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1204 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1205 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1206 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1207 return (EAGAIN); 1208 1209 v = amr_inl(amr, AMR_QREG_IDB); 1210 if ((v & AMR_QIDB_SUBMIT) != 0) { 1211 amr->amr_mbox->mb_cmd.mb_busy = 0; 1212 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1213 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1214 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1215 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1216 return (EAGAIN); 1217 } 1218 1219 amr->amr_mbox->mb_segment = 0; 1220 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1221 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1222 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1223 1224 ac->ac_start_time = (time_t)mono_time.tv_sec; 1225 ac->ac_flags |= AC_ACTIVE; 1226 amr_outl(amr, AMR_QREG_IDB, 1227 (amr->amr_mbox_paddr + 16) | AMR_QIDB_SUBMIT); 1228 return (0); 1229 } 1230 1231 int 1232 amr_std_submit(struct amr_softc *amr, struct amr_ccb *ac) 1233 { 1234 1235 amr->amr_mbox->mb_poll = 0; 1236 amr->amr_mbox->mb_ack = 0; 1237 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1238 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1239 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1240 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1241 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1242 return (EAGAIN); 1243 1244 if ((amr_inb(amr, AMR_SREG_MBOX_BUSY) & AMR_SMBOX_BUSY_FLAG) != 0) { 1245 amr->amr_mbox->mb_cmd.mb_busy = 0; 1246 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1247 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1248 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1249 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1250 return (EAGAIN); 1251 } 1252 1253 amr->amr_mbox->mb_segment = 0; 1254 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1255 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1256 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1257 1258 ac->ac_start_time = (time_t)mono_time.tv_sec; 1259 ac->ac_flags |= AC_ACTIVE; 1260 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_POST); 1261 return (0); 1262 } 1263 1264 /* 1265 * Claim any work that the controller has completed; acknowledge completion, 1266 * save details of the completion in (mbsave). Must be called with 1267 * interrupts blocked. 1268 */ 1269 int 1270 amr_quartz_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1271 { 1272 1273 /* Work waiting for us? */ 1274 if (amr_inl(amr, AMR_QREG_ODB) != AMR_QODB_READY) 1275 return (-1); 1276 1277 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1278 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1279 1280 /* Save the mailbox, which contains a list of completed commands. */ 1281 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1282 1283 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1284 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1285 1286 /* Ack the interrupt and mailbox transfer. */ 1287 amr_outl(amr, AMR_QREG_ODB, AMR_QODB_READY); 1288 amr_outl(amr, AMR_QREG_IDB, (amr->amr_mbox_paddr+16) | AMR_QIDB_ACK); 1289 1290 /* 1291 * This waits for the controller to notice that we've taken the 1292 * command from it. It's very inefficient, and we shouldn't do it, 1293 * but if we remove this code, we stop completing commands under 1294 * load. 1295 * 1296 * Peter J says we shouldn't do this. The documentation says we 1297 * should. Who is right? 1298 */ 1299 while ((amr_inl(amr, AMR_QREG_IDB) & AMR_QIDB_ACK) != 0) 1300 DELAY(10); 1301 1302 return (0); 1303 } 1304 1305 int 1306 amr_std_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1307 { 1308 u_int8_t istat; 1309 1310 /* Check for valid interrupt status. */ 1311 if (((istat = amr_inb(amr, AMR_SREG_INTR)) & AMR_SINTR_VALID) == 0) 1312 return (-1); 1313 1314 /* Ack the interrupt. */ 1315 amr_outb(amr, AMR_SREG_INTR, istat); 1316 1317 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1318 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1319 1320 /* Save mailbox, which contains a list of completed commands. */ 1321 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1322 1323 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1324 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1325 1326 /* Ack mailbox transfer. */ 1327 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 1328 1329 return (0); 1330 } 1331 1332 void 1333 amr_ccb_dump(struct amr_softc *amr, struct amr_ccb *ac) 1334 { 1335 int i; 1336 1337 printf("%s: ", amr->amr_dv.dv_xname); 1338 for (i = 0; i < 4; i++) 1339 printf("%08x ", ((u_int32_t *)&ac->ac_cmd)[i]); 1340 printf("\n"); 1341 } 1342 1343 static int 1344 amropen(dev_t dev, int flag, int mode, struct proc *p) 1345 { 1346 struct amr_softc *amr; 1347 1348 if ((amr = device_lookup(&amr_cd, minor(dev))) == NULL) 1349 return (ENXIO); 1350 if ((amr->amr_flags & AMRF_OPEN) != 0) 1351 return (EBUSY); 1352 1353 amr->amr_flags |= AMRF_OPEN; 1354 return (0); 1355 } 1356 1357 static int 1358 amrclose(dev_t dev, int flag, int mode, struct proc *p) 1359 { 1360 struct amr_softc *amr; 1361 1362 amr = device_lookup(&amr_cd, minor(dev)); 1363 amr->amr_flags &= ~AMRF_OPEN; 1364 return (0); 1365 } 1366 1367 static int 1368 amrioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 1369 { 1370 struct amr_softc *amr; 1371 struct amr_user_ioctl *au; 1372 struct amr_ccb *ac; 1373 struct amr_mailbox_ioctl *mbi; 1374 unsigned long au_length; 1375 uint8_t *au_cmd; 1376 int error; 1377 void *dp = NULL, *au_buffer; 1378 1379 if (securelevel >= 2) 1380 return (EPERM); 1381 1382 amr = device_lookup(&amr_cd, minor(dev)); 1383 1384 /* This should be compatible with the FreeBSD interface */ 1385 1386 switch (cmd) { 1387 case AMR_IO_VERSION: 1388 *(int *)data = AMR_IO_VERSION_NUMBER; 1389 return 0; 1390 case AMR_IO_COMMAND: 1391 au = (struct amr_user_ioctl *)data; 1392 au_cmd = au->au_cmd; 1393 au_buffer = au->au_buffer; 1394 au_length = au->au_length; 1395 break; 1396 default: 1397 return ENOTTY; 1398 } 1399 1400 if (au_cmd[0] == AMR_CMD_PASS) { 1401 /* not yet */ 1402 return EOPNOTSUPP; 1403 } 1404 1405 if (au_length <= 0 || au_length > MAXPHYS || au_cmd[0] == 0x06) 1406 return (EINVAL); 1407 1408 /* 1409 * allocate kernel memory for data, doing I/O directly to user 1410 * buffer isn't that easy. 1411 */ 1412 dp = malloc(au_length, M_DEVBUF, M_WAITOK|M_ZERO); 1413 if (dp == NULL) 1414 return ENOMEM; 1415 if ((error = copyin(au_buffer, dp, au_length)) != 0) 1416 goto out; 1417 1418 /* direct command to controller */ 1419 while (amr_ccb_alloc(amr, &ac) != 0) { 1420 error = tsleep(NULL, PRIBIO | PCATCH, "armmbx", hz); 1421 if (error == EINTR) 1422 goto out; 1423 } 1424 1425 mbi = (struct amr_mailbox_ioctl *)&ac->ac_cmd; 1426 mbi->mb_command = au_cmd[0]; 1427 mbi->mb_channel = au_cmd[1]; 1428 mbi->mb_param = au_cmd[2]; 1429 mbi->mb_pad[0] = au_cmd[3]; 1430 mbi->mb_drive = au_cmd[4]; 1431 error = amr_ccb_map(amr, ac, dp, (int)au_length, 1432 AC_XFER_IN | AC_XFER_OUT); 1433 if (error == 0) { 1434 error = amr_ccb_wait(amr, ac); 1435 amr_ccb_unmap(amr, ac); 1436 if (error == 0) 1437 error = copyout(dp, au_buffer, au_length); 1438 1439 } 1440 amr_ccb_free(amr, ac); 1441 out: 1442 free(dp, M_DEVBUF); 1443 return (error); 1444 } 1445
Indexes created Thu Oct 02 14:10:14 GMT 2025