amr.c revision 1.34.2.1
1 /* $NetBSD: amr.c,v 1.34.2.1 2006/06/19 04:01:35 chap Exp $ */ 2 3 /*- 4 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999,2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: amr_pci.c,v 1.5 2000/08/30 07:52:40 msmith Exp 66 * from FreeBSD: amr.c,v 1.16 2000/08/30 07:52:40 msmith Exp 67 */ 68 69 /* 70 * Driver for AMI RAID controllers. 71 */ 72 73 #include <sys/cdefs.h> 74 __KERNEL_RCSID(0, "$NetBSD: amr.c,v 1.34.2.1 2006/06/19 04:01:35 chap Exp $"); 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/device.h> 80 #include <sys/queue.h> 81 #include <sys/proc.h> 82 #include <sys/buf.h> 83 #include <sys/malloc.h> 84 #include <sys/kthread.h> 85 86 #include <uvm/uvm_extern.h> 87 88 #include <machine/endian.h> 89 #include <machine/bus.h> 90 91 #include <dev/pci/pcidevs.h> 92 #include <dev/pci/pcivar.h> 93 #include <dev/pci/amrreg.h> 94 #include <dev/pci/amrvar.h> 95 96 #include "locators.h" 97 98 static void amr_attach(struct device *, struct device *, void *); 99 static void amr_ccb_dump(struct amr_softc *, struct amr_ccb *); 100 static void *amr_enquire(struct amr_softc *, u_int8_t, u_int8_t, u_int8_t, 101 void *); 102 static int amr_init(struct amr_softc *, const char *, 103 struct pci_attach_args *pa); 104 static int amr_intr(void *); 105 static int amr_match(struct device *, struct cfdata *, void *); 106 static int amr_print(void *, const char *); 107 static void amr_shutdown(void *); 108 static void amr_teardown(struct amr_softc *); 109 static void amr_thread(void *); 110 static void amr_thread_create(void *); 111 112 static int amr_quartz_get_work(struct amr_softc *, 113 struct amr_mailbox_resp *); 114 static int amr_quartz_submit(struct amr_softc *, struct amr_ccb *); 115 static int amr_std_get_work(struct amr_softc *, struct amr_mailbox_resp *); 116 static int amr_std_submit(struct amr_softc *, struct amr_ccb *); 117 118 CFATTACH_DECL(amr, sizeof(struct amr_softc), 119 amr_match, amr_attach, NULL, NULL); 120 121 #define AT_QUARTZ 0x01 /* `Quartz' chipset */ 122 #define AT_SIG 0x02 /* Check for signature */ 123 124 struct amr_pci_type { 125 u_short apt_vendor; 126 u_short apt_product; 127 u_short apt_flags; 128 } static const amr_pci_type[] = { 129 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID, 0 }, 130 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID2, 0 }, 131 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 132 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ | AT_SIG }, 134 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, 136 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, 137 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI, AT_QUARTZ }, 138 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI_2, AT_QUARTZ }, 139 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4ESI, AT_QUARTZ }, 140 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_PERC_4SC, AT_QUARTZ }, 141 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, 142 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, 143 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, 144 }; 145 146 struct amr_typestr { 147 const char *at_str; 148 int at_sig; 149 } static const amr_typestr[] = { 150 { "Series 431", AMR_SIG_431 }, 151 { "Series 438", AMR_SIG_438 }, 152 { "Series 466", AMR_SIG_466 }, 153 { "Series 467", AMR_SIG_467 }, 154 { "Series 490", AMR_SIG_490 }, 155 { "Series 762", AMR_SIG_762 }, 156 { "HP NetRAID (T5)", AMR_SIG_T5 }, 157 { "HP NetRAID (T7)", AMR_SIG_T7 }, 158 }; 159 160 struct { 161 const char *ds_descr; 162 int ds_happy; 163 } static const amr_dstate[] = { 164 { "offline", 0 }, 165 { "degraded", 1 }, 166 { "optimal", 1 }, 167 { "online", 1 }, 168 { "failed", 0 }, 169 { "rebuilding", 1 }, 170 { "hotspare", 0 }, 171 }; 172 173 static void *amr_sdh; 174 175 static int amr_max_segs; 176 int amr_max_xfer; 177 178 static inline u_int8_t 179 amr_inb(struct amr_softc *amr, int off) 180 { 181 182 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 183 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 184 return (bus_space_read_1(amr->amr_iot, amr->amr_ioh, off)); 185 } 186 187 static inline u_int32_t 188 amr_inl(struct amr_softc *amr, int off) 189 { 190 191 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 192 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 193 return (bus_space_read_4(amr->amr_iot, amr->amr_ioh, off)); 194 } 195 196 static inline void 197 amr_outb(struct amr_softc *amr, int off, u_int8_t val) 198 { 199 200 bus_space_write_1(amr->amr_iot, amr->amr_ioh, off, val); 201 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 202 BUS_SPACE_BARRIER_WRITE); 203 } 204 205 static inline void 206 amr_outl(struct amr_softc *amr, int off, u_int32_t val) 207 { 208 209 bus_space_write_4(amr->amr_iot, amr->amr_ioh, off, val); 210 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 211 BUS_SPACE_BARRIER_WRITE); 212 } 213 214 /* 215 * Match a supported device. 216 */ 217 static int 218 amr_match(struct device *parent, struct cfdata *match, void *aux) 219 { 220 struct pci_attach_args *pa; 221 pcireg_t s; 222 int i; 223 224 pa = (struct pci_attach_args *)aux; 225 226 /* 227 * Don't match the device if it's operating in I2O mode. In this 228 * case it should be handled by the `iop' driver. 229 */ 230 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 231 return (0); 232 233 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 234 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 235 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 236 break; 237 238 if (i == sizeof(amr_pci_type) / sizeof(amr_pci_type[0])) 239 return (0); 240 241 if ((amr_pci_type[i].apt_flags & AT_SIG) == 0) 242 return (1); 243 244 s = pci_conf_read(pa->pa_pc, pa->pa_tag, AMR_QUARTZ_SIG_REG) & 0xffff; 245 return (s == AMR_QUARTZ_SIG0 || s == AMR_QUARTZ_SIG1); 246 } 247 248 /* 249 * Attach a supported device. 250 */ 251 static void 252 amr_attach(struct device *parent, struct device *self, void *aux) 253 { 254 struct pci_attach_args *pa; 255 struct amr_attach_args amra; 256 const struct amr_pci_type *apt; 257 struct amr_softc *amr; 258 pci_chipset_tag_t pc; 259 pci_intr_handle_t ih; 260 const char *intrstr; 261 pcireg_t reg; 262 int rseg, i, j, size, rv, memreg, ioreg; 263 struct amr_ccb *ac; 264 int locs[AMRCF_NLOCS]; 265 266 aprint_naive(": RAID controller\n"); 267 268 amr = (struct amr_softc *)self; 269 pa = (struct pci_attach_args *)aux; 270 pc = pa->pa_pc; 271 272 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 273 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 274 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 275 break; 276 apt = amr_pci_type + i; 277 278 memreg = ioreg = 0; 279 for (i = 0x10; i <= 0x14; i += 4) { 280 reg = pci_conf_read(pc, pa->pa_tag, i); 281 switch (PCI_MAPREG_TYPE(reg)) { 282 case PCI_MAPREG_TYPE_MEM: 283 if (PCI_MAPREG_MEM_SIZE(reg) != 0) 284 memreg = i; 285 break; 286 case PCI_MAPREG_TYPE_IO: 287 if (PCI_MAPREG_IO_SIZE(reg) != 0) 288 ioreg = i; 289 break; 290 291 } 292 } 293 294 if (memreg && pci_mapreg_map(pa, memreg, PCI_MAPREG_TYPE_MEM, 0, 295 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 296 ; 297 else if (ioreg && pci_mapreg_map(pa, ioreg, PCI_MAPREG_TYPE_IO, 0, 298 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 299 ; 300 else { 301 aprint_error("can't map control registers\n"); 302 amr_teardown(amr); 303 return; 304 } 305 306 amr->amr_flags |= AMRF_PCI_REGS; 307 amr->amr_dmat = pa->pa_dmat; 308 amr->amr_pc = pa->pa_pc; 309 310 /* Enable the device. */ 311 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 312 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 313 reg | PCI_COMMAND_MASTER_ENABLE); 314 315 /* Map and establish the interrupt. */ 316 if (pci_intr_map(pa, &ih)) { 317 aprint_error("can't map interrupt\n"); 318 amr_teardown(amr); 319 return; 320 } 321 intrstr = pci_intr_string(pc, ih); 322 amr->amr_ih = pci_intr_establish(pc, ih, IPL_BIO, amr_intr, amr); 323 if (amr->amr_ih == NULL) { 324 aprint_error("can't establish interrupt"); 325 if (intrstr != NULL) 326 aprint_normal(" at %s", intrstr); 327 aprint_normal("\n"); 328 amr_teardown(amr); 329 return; 330 } 331 amr->amr_flags |= AMRF_PCI_INTR; 332 333 /* 334 * Allocate space for the mailbox and S/G lists. Some controllers 335 * don't like S/G lists to be located below 0x2000, so we allocate 336 * enough slop to enable us to compensate. 337 * 338 * The standard mailbox structure needs to be aligned on a 16-byte 339 * boundary. The 64-bit mailbox has one extra field, 4 bytes in 340 * size, which preceeds the standard mailbox. 341 */ 342 size = AMR_SGL_SIZE * AMR_MAX_CMDS + 0x2000; 343 amr->amr_dmasize = size; 344 345 if ((rv = bus_dmamem_alloc(amr->amr_dmat, size, PAGE_SIZE, 0, 346 &amr->amr_dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 347 aprint_error("%s: unable to allocate buffer, rv = %d\n", 348 amr->amr_dv.dv_xname, rv); 349 amr_teardown(amr); 350 return; 351 } 352 amr->amr_flags |= AMRF_DMA_ALLOC; 353 354 if ((rv = bus_dmamem_map(amr->amr_dmat, &amr->amr_dmaseg, rseg, size, 355 (caddr_t *)&amr->amr_mbox, 356 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 357 aprint_error("%s: unable to map buffer, rv = %d\n", 358 amr->amr_dv.dv_xname, rv); 359 amr_teardown(amr); 360 return; 361 } 362 amr->amr_flags |= AMRF_DMA_MAP; 363 364 if ((rv = bus_dmamap_create(amr->amr_dmat, size, 1, size, 0, 365 BUS_DMA_NOWAIT, &amr->amr_dmamap)) != 0) { 366 aprint_error("%s: unable to create buffer DMA map, rv = %d\n", 367 amr->amr_dv.dv_xname, rv); 368 amr_teardown(amr); 369 return; 370 } 371 amr->amr_flags |= AMRF_DMA_CREATE; 372 373 if ((rv = bus_dmamap_load(amr->amr_dmat, amr->amr_dmamap, 374 amr->amr_mbox, size, NULL, BUS_DMA_NOWAIT)) != 0) { 375 aprint_error("%s: unable to load buffer DMA map, rv = %d\n", 376 amr->amr_dv.dv_xname, rv); 377 amr_teardown(amr); 378 return; 379 } 380 amr->amr_flags |= AMRF_DMA_LOAD; 381 382 memset(amr->amr_mbox, 0, size); 383 384 amr->amr_mbox_paddr = amr->amr_dmamap->dm_segs[0].ds_addr; 385 amr->amr_sgls_paddr = (amr->amr_mbox_paddr + 0x1fff) & ~0x1fff; 386 amr->amr_sgls = (struct amr_sgentry *)((caddr_t)amr->amr_mbox + 387 amr->amr_sgls_paddr - amr->amr_dmamap->dm_segs[0].ds_addr); 388 389 /* 390 * Allocate and initalise the command control blocks. 391 */ 392 ac = malloc(sizeof(*ac) * AMR_MAX_CMDS, M_DEVBUF, M_NOWAIT | M_ZERO); 393 amr->amr_ccbs = ac; 394 SLIST_INIT(&amr->amr_ccb_freelist); 395 TAILQ_INIT(&amr->amr_ccb_active); 396 amr->amr_flags |= AMRF_CCBS; 397 398 if (amr_max_xfer == 0) { 399 amr_max_xfer = min(((AMR_MAX_SEGS - 1) * PAGE_SIZE), MAXPHYS); 400 amr_max_segs = (amr_max_xfer + (PAGE_SIZE * 2) - 1) / PAGE_SIZE; 401 } 402 403 for (i = 0; i < AMR_MAX_CMDS; i++, ac++) { 404 rv = bus_dmamap_create(amr->amr_dmat, amr_max_xfer, 405 amr_max_segs, amr_max_xfer, 0, 406 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ac->ac_xfer_map); 407 if (rv != 0) 408 break; 409 410 ac->ac_ident = i; 411 amr_ccb_free(amr, ac); 412 } 413 if (i != AMR_MAX_CMDS) { 414 aprint_error("%s: memory exhausted\n", amr->amr_dv.dv_xname); 415 amr_teardown(amr); 416 return; 417 } 418 419 /* 420 * Take care of model-specific tasks. 421 */ 422 if ((apt->apt_flags & AT_QUARTZ) != 0) { 423 amr->amr_submit = amr_quartz_submit; 424 amr->amr_get_work = amr_quartz_get_work; 425 } else { 426 amr->amr_submit = amr_std_submit; 427 amr->amr_get_work = amr_std_get_work; 428 429 /* Notify the controller of the mailbox location. */ 430 amr_outl(amr, AMR_SREG_MBOX, (u_int32_t)amr->amr_mbox_paddr + 16); 431 amr_outb(amr, AMR_SREG_MBOX_ENABLE, AMR_SMBOX_ENABLE_ADDR); 432 433 /* Clear outstanding interrupts and enable interrupts. */ 434 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 435 amr_outb(amr, AMR_SREG_TOGL, 436 amr_inb(amr, AMR_SREG_TOGL) | AMR_STOGL_ENABLE); 437 } 438 439 /* 440 * Retrieve parameters, and tell the world about us. 441 */ 442 amr->amr_enqbuf = malloc(AMR_ENQUIRY_BUFSIZE, M_DEVBUF, M_NOWAIT); 443 amr->amr_flags |= AMRF_ENQBUF; 444 amr->amr_maxqueuecnt = i; 445 aprint_normal(": AMI RAID "); 446 if (amr_init(amr, intrstr, pa) != 0) { 447 amr_teardown(amr); 448 return; 449 } 450 451 /* 452 * Cap the maximum number of outstanding commands. AMI's Linux 453 * driver doesn't trust the controller's reported value, and lockups 454 * have been seen when we do. 455 */ 456 amr->amr_maxqueuecnt = min(amr->amr_maxqueuecnt, AMR_MAX_CMDS); 457 if (amr->amr_maxqueuecnt > i) 458 amr->amr_maxqueuecnt = i; 459 460 /* Set our `shutdownhook' before we start any device activity. */ 461 if (amr_sdh == NULL) 462 amr_sdh = shutdownhook_establish(amr_shutdown, NULL); 463 464 /* Attach sub-devices. */ 465 for (j = 0; j < amr->amr_numdrives; j++) { 466 if (amr->amr_drive[j].al_size == 0) 467 continue; 468 amra.amra_unit = j; 469 470 locs[AMRCF_UNIT] = j; 471 472 amr->amr_drive[j].al_dv = config_found_sm_loc(&amr->amr_dv, 473 "amr", locs, &amra, amr_print, config_stdsubmatch); 474 } 475 476 SIMPLEQ_INIT(&amr->amr_ccb_queue); 477 478 /* XXX This doesn't work for newer boards yet. */ 479 if ((apt->apt_flags & AT_QUARTZ) == 0) 480 kthread_create(amr_thread_create, amr); 481 } 482 483 /* 484 * Free up resources. 485 */ 486 static void 487 amr_teardown(struct amr_softc *amr) 488 { 489 struct amr_ccb *ac; 490 int fl; 491 492 fl = amr->amr_flags; 493 494 if ((fl & AMRF_THREAD) != 0) { 495 amr->amr_flags |= AMRF_THREAD_EXIT; 496 wakeup(amr_thread); 497 while ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) 498 tsleep(&amr->amr_flags, PWAIT, "amrexit", 0); 499 } 500 if ((fl & AMRF_CCBS) != 0) { 501 SLIST_FOREACH(ac, &amr->amr_ccb_freelist, ac_chain.slist) { 502 bus_dmamap_destroy(amr->amr_dmat, ac->ac_xfer_map); 503 } 504 free(amr->amr_ccbs, M_DEVBUF); 505 } 506 if ((fl & AMRF_ENQBUF) != 0) 507 free(amr->amr_enqbuf, M_DEVBUF); 508 if ((fl & AMRF_DMA_LOAD) != 0) 509 bus_dmamap_unload(amr->amr_dmat, amr->amr_dmamap); 510 if ((fl & AMRF_DMA_MAP) != 0) 511 bus_dmamem_unmap(amr->amr_dmat, (caddr_t)amr->amr_mbox, 512 amr->amr_dmasize); 513 if ((fl & AMRF_DMA_ALLOC) != 0) 514 bus_dmamem_free(amr->amr_dmat, &amr->amr_dmaseg, 1); 515 if ((fl & AMRF_DMA_CREATE) != 0) 516 bus_dmamap_destroy(amr->amr_dmat, amr->amr_dmamap); 517 if ((fl & AMRF_PCI_INTR) != 0) 518 pci_intr_disestablish(amr->amr_pc, amr->amr_ih); 519 if ((fl & AMRF_PCI_REGS) != 0) 520 bus_space_unmap(amr->amr_iot, amr->amr_ioh, amr->amr_ios); 521 } 522 523 /* 524 * Print autoconfiguration message for a sub-device. 525 */ 526 static int 527 amr_print(void *aux, const char *pnp) 528 { 529 struct amr_attach_args *amra; 530 531 amra = (struct amr_attach_args *)aux; 532 533 if (pnp != NULL) 534 aprint_normal("block device at %s", pnp); 535 aprint_normal(" unit %d", amra->amra_unit); 536 return (UNCONF); 537 } 538 539 /* 540 * Retrieve operational parameters and describe the controller. 541 */ 542 static int 543 amr_init(struct amr_softc *amr, const char *intrstr, 544 struct pci_attach_args *pa) 545 { 546 struct amr_adapter_info *aa; 547 struct amr_prodinfo *ap; 548 struct amr_enquiry *ae; 549 struct amr_enquiry3 *aex; 550 const char *prodstr; 551 u_int i, sig, ishp; 552 char sbuf[64]; 553 554 /* 555 * Try to get 40LD product info, which tells us what the card is 556 * labelled as. 557 */ 558 ap = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_PRODUCT_INFO, 0, 559 amr->amr_enqbuf); 560 if (ap != NULL) { 561 aprint_normal("<%.80s>\n", ap->ap_product); 562 if (intrstr != NULL) 563 aprint_normal("%s: interrupting at %s\n", 564 amr->amr_dv.dv_xname, intrstr); 565 aprint_normal("%s: firmware %.16s, BIOS %.16s, %dMB RAM\n", 566 amr->amr_dv.dv_xname, ap->ap_firmware, ap->ap_bios, 567 le16toh(ap->ap_memsize)); 568 569 amr->amr_maxqueuecnt = ap->ap_maxio; 570 571 /* 572 * Fetch and record state of logical drives. 573 */ 574 aex = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_ENQ3, 575 AMR_CONFIG_ENQ3_SOLICITED_FULL, amr->amr_enqbuf); 576 if (aex == NULL) { 577 aprint_error("%s ENQUIRY3 failed\n", 578 amr->amr_dv.dv_xname); 579 return (-1); 580 } 581 582 if (aex->ae_numldrives > __arraycount(aex->ae_drivestate)) { 583 aprint_error("%s: Inquiry returned more drives (%d)" 584 " than the array can handle (%zu)\n", 585 amr->amr_dv.dv_xname, aex->ae_numldrives, 586 __arraycount(aex->ae_drivestate)); 587 aex->ae_numldrives = __arraycount(aex->ae_drivestate); 588 } 589 if (aex->ae_numldrives > AMR_MAX_UNITS) { 590 aprint_error( 591 "%s: adjust AMR_MAX_UNITS to %d (currently %d)" 592 "\n", amr->amr_dv.dv_xname, AMR_MAX_UNITS, 593 amr->amr_numdrives); 594 amr->amr_numdrives = AMR_MAX_UNITS; 595 } else 596 amr->amr_numdrives = aex->ae_numldrives; 597 598 for (i = 0; i < amr->amr_numdrives; i++) { 599 amr->amr_drive[i].al_size = 600 le32toh(aex->ae_drivesize[i]); 601 amr->amr_drive[i].al_state = aex->ae_drivestate[i]; 602 amr->amr_drive[i].al_properties = aex->ae_driveprop[i]; 603 } 604 605 return (0); 606 } 607 608 /* 609 * Try 8LD extended ENQUIRY to get the controller signature. Once 610 * found, search for a product description. 611 */ 612 ae = amr_enquire(amr, AMR_CMD_EXT_ENQUIRY2, 0, 0, amr->amr_enqbuf); 613 if (ae != NULL) { 614 i = 0; 615 sig = le32toh(ae->ae_signature); 616 617 while (i < sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 618 if (amr_typestr[i].at_sig == sig) 619 break; 620 i++; 621 } 622 if (i == sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 623 snprintf(sbuf, sizeof(sbuf), 624 "unknown ENQUIRY2 sig (0x%08x)", sig); 625 prodstr = sbuf; 626 } else 627 prodstr = amr_typestr[i].at_str; 628 } else { 629 ae = amr_enquire(amr, AMR_CMD_ENQUIRY, 0, 0, amr->amr_enqbuf); 630 if (ae == NULL) { 631 aprint_error("%s: unsupported controller\n", 632 amr->amr_dv.dv_xname); 633 return (-1); 634 } 635 636 switch (PCI_PRODUCT(pa->pa_id)) { 637 case PCI_PRODUCT_AMI_MEGARAID: 638 prodstr = "Series 428"; 639 break; 640 case PCI_PRODUCT_AMI_MEGARAID2: 641 prodstr = "Series 434"; 642 break; 643 default: 644 snprintf(sbuf, sizeof(sbuf), "unknown PCI dev (0x%04x)", 645 PCI_PRODUCT(pa->pa_id)); 646 prodstr = sbuf; 647 break; 648 } 649 } 650 651 /* 652 * HP NetRaid controllers have a special encoding of the firmware 653 * and BIOS versions. The AMI version seems to have it as strings 654 * whereas the HP version does it with a leading uppercase character 655 * and two binary numbers. 656 */ 657 aa = &ae->ae_adapter; 658 659 if (aa->aa_firmware[2] >= 'A' && aa->aa_firmware[2] <= 'Z' && 660 aa->aa_firmware[1] < ' ' && aa->aa_firmware[0] < ' ' && 661 aa->aa_bios[2] >= 'A' && aa->aa_bios[2] <= 'Z' && 662 aa->aa_bios[1] < ' ' && aa->aa_bios[0] < ' ') { 663 if (le32toh(ae->ae_signature) == AMR_SIG_438) { 664 /* The AMI 438 is a NetRaid 3si in HP-land. */ 665 prodstr = "HP NetRaid 3si"; 666 } 667 ishp = 1; 668 } else 669 ishp = 0; 670 671 aprint_normal("<%s>\n", prodstr); 672 if (intrstr != NULL) 673 aprint_normal("%s: interrupting at %s\n", amr->amr_dv.dv_xname, 674 intrstr); 675 676 if (ishp) 677 aprint_normal("%s: firmware <%c.%02d.%02d>, BIOS <%c.%02d.%02d>" 678 ", %dMB RAM\n", amr->amr_dv.dv_xname, aa->aa_firmware[2], 679 aa->aa_firmware[1], aa->aa_firmware[0], aa->aa_bios[2], 680 aa->aa_bios[1], aa->aa_bios[0], aa->aa_memorysize); 681 else 682 aprint_normal("%s: firmware <%.4s>, BIOS <%.4s>, %dMB RAM\n", 683 amr->amr_dv.dv_xname, aa->aa_firmware, aa->aa_bios, 684 aa->aa_memorysize); 685 686 amr->amr_maxqueuecnt = aa->aa_maxio; 687 688 /* 689 * Record state of logical drives. 690 */ 691 if (ae->ae_ldrv.al_numdrives > __arraycount(ae->ae_ldrv.al_size)) { 692 aprint_error("%s: Inquiry returned more drives (%d)" 693 " than the array can handle (%zu)\n", 694 amr->amr_dv.dv_xname, ae->ae_ldrv.al_numdrives, 695 __arraycount(ae->ae_ldrv.al_size)); 696 ae->ae_ldrv.al_numdrives = __arraycount(ae->ae_ldrv.al_size); 697 } 698 if (ae->ae_ldrv.al_numdrives > AMR_MAX_UNITS) { 699 aprint_error("%s: adjust AMR_MAX_UNITS to %d (currently %d)\n", 700 amr->amr_dv.dv_xname, ae->ae_ldrv.al_numdrives, 701 AMR_MAX_UNITS); 702 amr->amr_numdrives = AMR_MAX_UNITS; 703 } else 704 amr->amr_numdrives = ae->ae_ldrv.al_numdrives; 705 706 for (i = 0; i < amr->amr_numdrives; i++) { 707 amr->amr_drive[i].al_size = le32toh(ae->ae_ldrv.al_size[i]); 708 amr->amr_drive[i].al_state = ae->ae_ldrv.al_state[i]; 709 amr->amr_drive[i].al_properties = ae->ae_ldrv.al_properties[i]; 710 } 711 712 return (0); 713 } 714 715 /* 716 * Flush the internal cache on each configured controller. Called at 717 * shutdown time. 718 */ 719 static void 720 amr_shutdown(void *cookie) 721 { 722 extern struct cfdriver amr_cd; 723 struct amr_softc *amr; 724 struct amr_ccb *ac; 725 int i, rv, s; 726 727 for (i = 0; i < amr_cd.cd_ndevs; i++) { 728 if ((amr = device_lookup(&amr_cd, i)) == NULL) 729 continue; 730 731 if ((rv = amr_ccb_alloc(amr, &ac)) == 0) { 732 ac->ac_cmd.mb_command = AMR_CMD_FLUSH; 733 s = splbio(); 734 rv = amr_ccb_poll(amr, ac, 30000); 735 splx(s); 736 amr_ccb_free(amr, ac); 737 } 738 if (rv != 0) 739 printf("%s: unable to flush cache (%d)\n", 740 amr->amr_dv.dv_xname, rv); 741 } 742 } 743 744 /* 745 * Interrupt service routine. 746 */ 747 static int 748 amr_intr(void *cookie) 749 { 750 struct amr_softc *amr; 751 struct amr_ccb *ac; 752 struct amr_mailbox_resp mbox; 753 u_int i, forus, idx; 754 755 amr = cookie; 756 forus = 0; 757 758 while ((*amr->amr_get_work)(amr, &mbox) == 0) { 759 /* Iterate over completed commands in this result. */ 760 for (i = 0; i < mbox.mb_nstatus; i++) { 761 idx = mbox.mb_completed[i] - 1; 762 ac = amr->amr_ccbs + idx; 763 764 if (idx >= amr->amr_maxqueuecnt) { 765 printf("%s: bad status (bogus ID: %u=%u)\n", 766 amr->amr_dv.dv_xname, i, idx); 767 continue; 768 } 769 770 if ((ac->ac_flags & AC_ACTIVE) == 0) { 771 printf("%s: bad status (not active; 0x04%x)\n", 772 amr->amr_dv.dv_xname, ac->ac_flags); 773 continue; 774 } 775 776 ac->ac_status = mbox.mb_status; 777 ac->ac_flags = (ac->ac_flags & ~AC_ACTIVE) | 778 AC_COMPLETE; 779 TAILQ_REMOVE(&amr->amr_ccb_active, ac, ac_chain.tailq); 780 781 if ((ac->ac_flags & AC_MOAN) != 0) 782 printf("%s: ccb %d completed\n", 783 amr->amr_dv.dv_xname, ac->ac_ident); 784 785 /* Pass notification to upper layers. */ 786 if (ac->ac_handler != NULL) 787 (*ac->ac_handler)(ac); 788 else 789 wakeup(ac); 790 } 791 forus = 1; 792 } 793 794 if (forus) 795 amr_ccb_enqueue(amr, NULL); 796 797 return (forus); 798 } 799 800 /* 801 * Create the watchdog thread. 802 */ 803 static void 804 amr_thread_create(void *cookie) 805 { 806 struct amr_softc *amr; 807 int rv; 808 809 amr = cookie; 810 811 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 812 amr->amr_flags ^= AMRF_THREAD_EXIT; 813 wakeup(&amr->amr_flags); 814 return; 815 } 816 817 rv = kthread_create1(amr_thread, amr, &amr->amr_thread, "%s", 818 amr->amr_dv.dv_xname); 819 if (rv != 0) 820 aprint_error("%s: unable to create thread (%d)", 821 amr->amr_dv.dv_xname, rv); 822 else 823 amr->amr_flags |= AMRF_THREAD; 824 } 825 826 /* 827 * Watchdog thread. 828 */ 829 static void 830 amr_thread(void *cookie) 831 { 832 struct amr_softc *amr; 833 struct amr_ccb *ac; 834 struct amr_logdrive *al; 835 struct amr_enquiry *ae; 836 int rv, i, s; 837 838 amr = cookie; 839 ae = amr->amr_enqbuf; 840 841 for (;;) { 842 tsleep(amr_thread, PWAIT, "amrwdog", AMR_WDOG_TICKS); 843 844 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 845 amr->amr_flags ^= AMRF_THREAD_EXIT; 846 wakeup(&amr->amr_flags); 847 kthread_exit(0); 848 } 849 850 s = splbio(); 851 amr_intr(cookie); 852 ac = TAILQ_FIRST(&amr->amr_ccb_active); 853 while (ac != NULL) { 854 if (ac->ac_start_time + AMR_TIMEOUT > time_uptime) 855 break; 856 if ((ac->ac_flags & AC_MOAN) == 0) { 857 printf("%s: ccb %d timed out; mailbox:\n", 858 amr->amr_dv.dv_xname, ac->ac_ident); 859 amr_ccb_dump(amr, ac); 860 ac->ac_flags |= AC_MOAN; 861 } 862 ac = TAILQ_NEXT(ac, ac_chain.tailq); 863 } 864 splx(s); 865 866 if ((rv = amr_ccb_alloc(amr, &ac)) != 0) { 867 printf("%s: ccb_alloc failed (%d)\n", 868 amr->amr_dv.dv_xname, rv); 869 continue; 870 } 871 872 ac->ac_cmd.mb_command = AMR_CMD_ENQUIRY; 873 874 rv = amr_ccb_map(amr, ac, amr->amr_enqbuf, 875 AMR_ENQUIRY_BUFSIZE, 0); 876 if (rv != 0) { 877 printf("%s: ccb_map failed (%d)\n", 878 amr->amr_dv.dv_xname, rv); 879 amr_ccb_free(amr, ac); 880 continue; 881 } 882 883 rv = amr_ccb_wait(amr, ac); 884 amr_ccb_unmap(amr, ac); 885 if (rv != 0) { 886 printf("%s: enquiry failed (st=%d)\n", 887 amr->amr_dv.dv_xname, ac->ac_status); 888 continue; 889 } 890 amr_ccb_free(amr, ac); 891 892 al = amr->amr_drive; 893 for (i = 0; i < __arraycount(ae->ae_ldrv.al_state); i++, al++) { 894 if (al->al_dv == NULL) 895 continue; 896 if (al->al_state == ae->ae_ldrv.al_state[i]) 897 continue; 898 899 printf("%s: state changed: %s -> %s\n", 900 al->al_dv->dv_xname, 901 amr_drive_state(al->al_state, NULL), 902 amr_drive_state(ae->ae_ldrv.al_state[i], NULL)); 903 904 al->al_state = ae->ae_ldrv.al_state[i]; 905 } 906 } 907 } 908 909 /* 910 * Return a text description of a logical drive's current state. 911 */ 912 const char * 913 amr_drive_state(int state, int *happy) 914 { 915 const char *str; 916 917 state = AMR_DRV_CURSTATE(state); 918 if (state >= sizeof(amr_dstate) / sizeof(amr_dstate[0])) { 919 if (happy) 920 *happy = 1; 921 str = "status unknown"; 922 } else { 923 if (happy) 924 *happy = amr_dstate[state].ds_happy; 925 str = amr_dstate[state].ds_descr; 926 } 927 928 return (str); 929 } 930 931 /* 932 * Run a generic enquiry-style command. 933 */ 934 static void * 935 amr_enquire(struct amr_softc *amr, u_int8_t cmd, u_int8_t cmdsub, 936 u_int8_t cmdqual, void *sbuf) 937 { 938 struct amr_ccb *ac; 939 u_int8_t *mb; 940 int rv; 941 942 if (amr_ccb_alloc(amr, &ac) != 0) 943 return (NULL); 944 945 /* Build the command proper. */ 946 mb = (u_int8_t *)&ac->ac_cmd; 947 mb[0] = cmd; 948 mb[2] = cmdsub; 949 mb[3] = cmdqual; 950 951 rv = amr_ccb_map(amr, ac, sbuf, AMR_ENQUIRY_BUFSIZE, 0); 952 if (rv == 0) { 953 rv = amr_ccb_poll(amr, ac, 2000); 954 amr_ccb_unmap(amr, ac); 955 } 956 amr_ccb_free(amr, ac); 957 958 return (rv ? NULL : sbuf); 959 } 960 961 /* 962 * Allocate and initialise a CCB. 963 */ 964 int 965 amr_ccb_alloc(struct amr_softc *amr, struct amr_ccb **acp) 966 { 967 int s; 968 969 s = splbio(); 970 if ((*acp = SLIST_FIRST(&amr->amr_ccb_freelist)) == NULL) { 971 splx(s); 972 return (EAGAIN); 973 } 974 SLIST_REMOVE_HEAD(&amr->amr_ccb_freelist, ac_chain.slist); 975 splx(s); 976 977 return (0); 978 } 979 980 /* 981 * Free a CCB. 982 */ 983 void 984 amr_ccb_free(struct amr_softc *amr, struct amr_ccb *ac) 985 { 986 int s; 987 988 memset(&ac->ac_cmd, 0, sizeof(ac->ac_cmd)); 989 ac->ac_cmd.mb_ident = ac->ac_ident + 1; 990 ac->ac_cmd.mb_busy = 1; 991 ac->ac_handler = NULL; 992 ac->ac_flags = 0; 993 994 s = splbio(); 995 SLIST_INSERT_HEAD(&amr->amr_ccb_freelist, ac, ac_chain.slist); 996 splx(s); 997 } 998 999 /* 1000 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 1001 * the order that they were enqueued and try to submit their command blocks 1002 * to the controller for execution. 1003 */ 1004 void 1005 amr_ccb_enqueue(struct amr_softc *amr, struct amr_ccb *ac) 1006 { 1007 int s; 1008 1009 s = splbio(); 1010 1011 if (ac != NULL) 1012 SIMPLEQ_INSERT_TAIL(&amr->amr_ccb_queue, ac, ac_chain.simpleq); 1013 1014 while ((ac = SIMPLEQ_FIRST(&amr->amr_ccb_queue)) != NULL) { 1015 if ((*amr->amr_submit)(amr, ac) != 0) 1016 break; 1017 SIMPLEQ_REMOVE_HEAD(&amr->amr_ccb_queue, ac_chain.simpleq); 1018 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1019 } 1020 1021 splx(s); 1022 } 1023 1024 /* 1025 * Map the specified CCB's data buffer onto the bus, and fill the 1026 * scatter-gather list. 1027 */ 1028 int 1029 amr_ccb_map(struct amr_softc *amr, struct amr_ccb *ac, void *data, int size, 1030 int out) 1031 { 1032 struct amr_sgentry *sge; 1033 struct amr_mailbox_cmd *mb; 1034 int nsegs, i, rv, sgloff; 1035 bus_dmamap_t xfer; 1036 1037 xfer = ac->ac_xfer_map; 1038 1039 rv = bus_dmamap_load(amr->amr_dmat, xfer, data, size, NULL, 1040 BUS_DMA_NOWAIT); 1041 if (rv != 0) 1042 return (rv); 1043 1044 mb = &ac->ac_cmd; 1045 ac->ac_xfer_size = size; 1046 ac->ac_flags |= (out ? AC_XFER_OUT : AC_XFER_IN); 1047 sgloff = AMR_SGL_SIZE * ac->ac_ident; 1048 1049 /* We don't need to use a scatter/gather list for just 1 segment. */ 1050 nsegs = xfer->dm_nsegs; 1051 if (nsegs == 1) { 1052 mb->mb_nsgelem = 0; 1053 mb->mb_physaddr = htole32(xfer->dm_segs[0].ds_addr); 1054 ac->ac_flags |= AC_NOSGL; 1055 } else { 1056 mb->mb_nsgelem = nsegs; 1057 mb->mb_physaddr = htole32(amr->amr_sgls_paddr + sgloff); 1058 1059 sge = (struct amr_sgentry *)((caddr_t)amr->amr_sgls + sgloff); 1060 for (i = 0; i < nsegs; i++, sge++) { 1061 sge->sge_addr = htole32(xfer->dm_segs[i].ds_addr); 1062 sge->sge_count = htole32(xfer->dm_segs[i].ds_len); 1063 } 1064 } 1065 1066 bus_dmamap_sync(amr->amr_dmat, xfer, 0, ac->ac_xfer_size, 1067 out ? BUS_DMASYNC_PREWRITE : BUS_DMASYNC_PREREAD); 1068 1069 if ((ac->ac_flags & AC_NOSGL) == 0) 1070 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, sgloff, 1071 AMR_SGL_SIZE, BUS_DMASYNC_PREWRITE); 1072 1073 return (0); 1074 } 1075 1076 /* 1077 * Unmap the specified CCB's data buffer. 1078 */ 1079 void 1080 amr_ccb_unmap(struct amr_softc *amr, struct amr_ccb *ac) 1081 { 1082 1083 if ((ac->ac_flags & AC_NOSGL) == 0) 1084 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 1085 AMR_SGL_SIZE * ac->ac_ident, AMR_SGL_SIZE, 1086 BUS_DMASYNC_POSTWRITE); 1087 bus_dmamap_sync(amr->amr_dmat, ac->ac_xfer_map, 0, ac->ac_xfer_size, 1088 (ac->ac_flags & AC_XFER_IN) != 0 ? 1089 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1090 bus_dmamap_unload(amr->amr_dmat, ac->ac_xfer_map); 1091 } 1092 1093 /* 1094 * Submit a command to the controller and poll on completion. Return 1095 * non-zero on timeout or error. Must be called with interrupts blocked. 1096 */ 1097 int 1098 amr_ccb_poll(struct amr_softc *amr, struct amr_ccb *ac, int timo) 1099 { 1100 int rv; 1101 1102 if ((rv = (*amr->amr_submit)(amr, ac)) != 0) 1103 return (rv); 1104 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1105 1106 for (timo *= 10; timo != 0; timo--) { 1107 amr_intr(amr); 1108 if ((ac->ac_flags & AC_COMPLETE) != 0) 1109 break; 1110 DELAY(100); 1111 } 1112 1113 return (timo == 0 || ac->ac_status != 0 ? EIO : 0); 1114 } 1115 1116 /* 1117 * Submit a command to the controller and sleep on completion. Return 1118 * non-zero on error. 1119 */ 1120 int 1121 amr_ccb_wait(struct amr_softc *amr, struct amr_ccb *ac) 1122 { 1123 int s; 1124 1125 s = splbio(); 1126 amr_ccb_enqueue(amr, ac); 1127 tsleep(ac, PRIBIO, "amrcmd", 0); 1128 splx(s); 1129 1130 return (ac->ac_status != 0 ? EIO : 0); 1131 } 1132 1133 #if 0 1134 /* 1135 * Wait for the mailbox to become available. 1136 */ 1137 static int 1138 amr_mbox_wait(struct amr_softc *amr) 1139 { 1140 int timo; 1141 1142 for (timo = 10000; timo != 0; timo--) { 1143 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1144 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1145 if (amr->amr_mbox->mb_cmd.mb_busy == 0) 1146 break; 1147 DELAY(100); 1148 } 1149 1150 if (timo == 0) 1151 printf("%s: controller wedged\n", amr->amr_dv.dv_xname); 1152 1153 return (timo != 0 ? 0 : EAGAIN); 1154 } 1155 #endif 1156 1157 /* 1158 * Tell the controller that the mailbox contains a valid command. Must be 1159 * called with interrupts blocked. 1160 */ 1161 static int 1162 amr_quartz_submit(struct amr_softc *amr, struct amr_ccb *ac) 1163 { 1164 u_int32_t v; 1165 1166 amr->amr_mbox->mb_poll = 0; 1167 amr->amr_mbox->mb_ack = 0; 1168 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1169 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1170 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1171 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1172 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1173 return (EAGAIN); 1174 1175 v = amr_inl(amr, AMR_QREG_IDB); 1176 if ((v & AMR_QIDB_SUBMIT) != 0) { 1177 amr->amr_mbox->mb_cmd.mb_busy = 0; 1178 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1179 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1180 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1181 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1182 return (EAGAIN); 1183 } 1184 1185 amr->amr_mbox->mb_segment = 0; 1186 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1187 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1188 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1189 1190 ac->ac_start_time = time_uptime; 1191 ac->ac_flags |= AC_ACTIVE; 1192 amr_outl(amr, AMR_QREG_IDB, 1193 (amr->amr_mbox_paddr + 16) | AMR_QIDB_SUBMIT); 1194 return (0); 1195 } 1196 1197 static int 1198 amr_std_submit(struct amr_softc *amr, struct amr_ccb *ac) 1199 { 1200 1201 amr->amr_mbox->mb_poll = 0; 1202 amr->amr_mbox->mb_ack = 0; 1203 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1204 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1205 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1206 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1207 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1208 return (EAGAIN); 1209 1210 if ((amr_inb(amr, AMR_SREG_MBOX_BUSY) & AMR_SMBOX_BUSY_FLAG) != 0) { 1211 amr->amr_mbox->mb_cmd.mb_busy = 0; 1212 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1213 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1214 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1215 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1216 return (EAGAIN); 1217 } 1218 1219 amr->amr_mbox->mb_segment = 0; 1220 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1221 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1222 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1223 1224 ac->ac_start_time = time_uptime; 1225 ac->ac_flags |= AC_ACTIVE; 1226 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_POST); 1227 return (0); 1228 } 1229 1230 /* 1231 * Claim any work that the controller has completed; acknowledge completion, 1232 * save details of the completion in (mbsave). Must be called with 1233 * interrupts blocked. 1234 */ 1235 static int 1236 amr_quartz_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1237 { 1238 1239 /* Work waiting for us? */ 1240 if (amr_inl(amr, AMR_QREG_ODB) != AMR_QODB_READY) 1241 return (-1); 1242 1243 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1244 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1245 1246 /* Save the mailbox, which contains a list of completed commands. */ 1247 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1248 1249 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1250 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1251 1252 /* Ack the interrupt and mailbox transfer. */ 1253 amr_outl(amr, AMR_QREG_ODB, AMR_QODB_READY); 1254 amr_outl(amr, AMR_QREG_IDB, (amr->amr_mbox_paddr+16) | AMR_QIDB_ACK); 1255 1256 /* 1257 * This waits for the controller to notice that we've taken the 1258 * command from it. It's very inefficient, and we shouldn't do it, 1259 * but if we remove this code, we stop completing commands under 1260 * load. 1261 * 1262 * Peter J says we shouldn't do this. The documentation says we 1263 * should. Who is right? 1264 */ 1265 while ((amr_inl(amr, AMR_QREG_IDB) & AMR_QIDB_ACK) != 0) 1266 DELAY(10); 1267 1268 return (0); 1269 } 1270 1271 static int 1272 amr_std_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1273 { 1274 u_int8_t istat; 1275 1276 /* Check for valid interrupt status. */ 1277 if (((istat = amr_inb(amr, AMR_SREG_INTR)) & AMR_SINTR_VALID) == 0) 1278 return (-1); 1279 1280 /* Ack the interrupt. */ 1281 amr_outb(amr, AMR_SREG_INTR, istat); 1282 1283 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1284 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1285 1286 /* Save mailbox, which contains a list of completed commands. */ 1287 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1288 1289 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1290 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1291 1292 /* Ack mailbox transfer. */ 1293 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 1294 1295 return (0); 1296 } 1297 1298 static void 1299 amr_ccb_dump(struct amr_softc *amr, struct amr_ccb *ac) 1300 { 1301 int i; 1302 1303 printf("%s: ", amr->amr_dv.dv_xname); 1304 for (i = 0; i < 4; i++) 1305 printf("%08x ", ((u_int32_t *)&ac->ac_cmd)[i]); 1306 printf("\n"); 1307 } 1308
Indexes created Thu Oct 02 14:10:14 GMT 2025